This is an archive of the discontinued LLVM Phabricator instance.

Differential D7611

[mips][microMIPS] Make usage of AND16, OR16 and XOR16 by code generator
ClosedPublic

Authored by jkolek on Feb 13 2015, 6:16 AM.

Details

Reviewers
dsanders
zoran.jovanovic
Commits
rG5d171fc29178: [mips][microMIPS] Make usage of AND16, OR16 and XOR16 by code generator
rL229845: [mips][microMIPS] Make usage of AND16, OR16 and XOR16 by code generator
Summary

Make usage of microMIPS 16-bit instructions AND16, OR16 and XOR16 by code generator.

Diff Detail

Repository
rL LLVM

Event Timeline

jkolek updated this revision to Diff 19884.Feb 13 2015, 6:16 AM
jkolek retitled this revision from to [mips][microMIPS] Make usage of AND16, OR16 and XOR16 by code generator.
jkolek updated this object.
jkolek edited the test plan for this revision. (Show Details)
jkolek added reviewers: zoran.jovanovic, dsanders.
jkolek added subscribers: petarj, Unknown Object (MLST).
zoran.jovanovic accepted this revision.Feb 19 2015, 2:45 AM
zoran.jovanovic edited edge metadata.

LGTM

This revision is now accepted and ready to land.Feb 19 2015, 2:45 AM
Closed by commit rL229845: [mips][microMIPS] Make usage of AND16, OR16 and XOR16 by code generator (authored by jkolek). · Explain WhyFeb 19 2015, 3:53 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
2 lines
test/
CodeGen/
Mips/
18 lines
18 lines
18 lines

Diff 20273

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Show First 20 Lines • Show All 1,148 Lines • ▼ Show 20 Lines
} }
let Defs = [HI0, LO0] in let Defs = [HI0, LO0] in
def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>, def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6; ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>; def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>; def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>; def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>; def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
let AdditionalPredicates = [NotInMicroMips] in {
def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>, def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
ADD_FM<0, 0x24>; ADD_FM<0, 0x24>;
def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>, def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
ADD_FM<0, 0x25>; ADD_FM<0, 0x25>;
def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>, def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
ADD_FM<0, 0x26>; ADD_FM<0, 0x26>;
}
def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
/// Shift Instructions /// Shift Instructions
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl, def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
immZExt5>, SRA_FM<0, 0>; immZExt5>, SRA_FM<0, 0>;
def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl, def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
immZExt5>, SRA_FM<2, 0>; immZExt5>, SRA_FM<2, 0>;
▲ Show 20 Lines • Show All 731 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Mips/micromips-and16.ll

; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
define i32 @main() {
entry:
%retval = alloca i32, align 4
%a = alloca i32, align 4
%b = alloca i32, align 4
%c = alloca i32, align 4
store i32 0, i32* %retval
%0 = load i32* %b, align 4
%1 = load i32* %c, align 4
%and = and i32 %0, %1
store i32 %and, i32* %a, align 4
ret i32 0
}
; CHECK: and16

llvm/trunk/test/CodeGen/Mips/micromips-or16.ll

; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
define i32 @main() {
entry:
%retval = alloca i32, align 4
%a = alloca i32, align 4
%b = alloca i32, align 4
%c = alloca i32, align 4
store i32 0, i32* %retval
%0 = load i32* %b, align 4
%1 = load i32* %c, align 4
%or = or i32 %0, %1
store i32 %or, i32* %a, align 4
ret i32 0
}
; CHECK: or16

llvm/trunk/test/CodeGen/Mips/micromips-xor16.ll

; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
define i32 @main() {
entry:
%retval = alloca i32, align 4
%a = alloca i32, align 4
%b = alloca i32, align 4
%c = alloca i32, align 4
store i32 0, i32* %retval
%0 = load i32* %b, align 4
%1 = load i32* %c, align 4
%xor = xor i32 %0, %1
store i32 %xor, i32* %a, align 4
ret i32 0
}
; CHECK: xor16