[mips] Avoid redundant sign extension of the result of binary bitwise instructions.

[dsanders]

LGTM with a comment nit.

lib/Target/Mips/Mips64InstrInfo.td

489 ↗

(On Diff #19815)

Nit: Capitalize first letter and add full-stop

llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td

 // truncate
 def : MipsPat<(trunc (assertsext GPR64:$src)),
               (EXTRACT_SUBREG GPR64:$src, sub_32)>;
 def : MipsPat<(trunc (assertzext GPR64:$src)),
               (EXTRACT_SUBREG GPR64:$src, sub_32)>;
 def : MipsPat<(i32 (trunc GPR64:$src)),
               (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>;
 
+// Bypass trunc nodes for bitwise ops.
+def : MipsPat<(i32 (trunc (and GPR64:$lhs, GPR64:$rhs))),
+              (EXTRACT_SUBREG (AND64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
+def : MipsPat<(i32 (trunc (or GPR64:$lhs, GPR64:$rhs))),
+              (EXTRACT_SUBREG (OR64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
+def : MipsPat<(i32 (trunc (xor GPR64:$lhs, GPR64:$rhs))),
+              (EXTRACT_SUBREG (XOR64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
+
 // 32-to-64-bit extension
 def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
 def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
 
 // Sign extend in register
 def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
               (SLL64_64 GPR64:$src)>;

llvm/trunk/test/CodeGen/Mips/llvm-ir/and.ll

; ALL-LABEL: and_i16:
   %r = and i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @and_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: and_i32:
 
-  ; GP32:         and     $2, $4, $5
-
-  ; GP64:         and     $[[T0:[0-9]+]], $4, $5
-  ; GP64:         sll     $2, $[[T0]], 0
+  ; ALL:          and     $2, $4, $5
 
   %r = and i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @and_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: and_i64:

llvm/trunk/test/CodeGen/Mips/llvm-ir/or.ll

; ALL-LABEL: or_i16:
   %r = or i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @or_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: or_i32:
 
-  ; GP32:         or     $2, $4, $5
-
-  ; GP64:         or     $[[T0:[0-9]+]], $4, $5
-  ; FIXME: The sll instruction below is redundant.
-  ; GP64:         sll     $2, $[[T0]], 0
+  ; ALL:          or     $2, $4, $5
 
   %r = or i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @or_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: or_i64:

llvm/trunk/test/CodeGen/Mips/llvm-ir/xor.ll

; ALL-LABEL: xor_i16:
   %r = xor i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @xor_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: xor_i32:
 
-  ; GP32:         xor     $2, $4, $5
-
-  ; GP64:         xor     $[[T0:[0-9]+]], $4, $5
-  ; GP64:         sll     $2, $[[T0]], 0
+  ; ALL:          xor     $2, $4, $5
 
   %r = xor i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @xor_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: xor_i64: