[mips][microMIPS] Delay slot filler: Replace the microMIPS JR with the JRC

[jkolek]

Summary

This patch adds functionality in MIPS delay slot filler such as if delay slot filler have to put NOP instruction into the delay slot of microMIPS JR instruction, then instead of emitting NOP this instruction is replaced by compact jump instruction JRC.

[zoran.jovanovic]

LGTM.

llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp

public:
     }
 
   private:
     bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
 
     Iter replaceWithCompactBranch(MachineBasicBlock &MBB,
                                   Iter Branch, DebugLoc DL);
 
+    Iter replaceWithCompactJump(MachineBasicBlock &MBB,
+                                Iter Jump, DebugLoc DL);
+
     /// This function checks if it is valid to move Candidate to the delay slot
     /// and returns true if it isn't. It also updates memory and register
     /// dependence information.
     bool delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
                         InspectMemInstr &IM) const;
 
     /// This function searches range [Begin, End) for an instruction that can be
     /// moved to the delay slot. Returns true on success.
Iter Filler::replaceWithCompactBranch(MachineBasicBlock &MBB,
 
   Iter tmpIter = Branch;
   Branch = std::prev(Branch);
   MBB.erase(tmpIter);
 
   return Branch;
 }
 
+// Replace Jumps with the compact jump instruction.
+Iter Filler::replaceWithCompactJump(MachineBasicBlock &MBB,
+                                    Iter Jump, DebugLoc DL) {
+  const MipsInstrInfo *TII =
+      MBB.getParent()->getSubtarget<MipsSubtarget>().getInstrInfo();
+
+  const MCInstrDesc &NewDesc = TII->get(Mips::JRC16_MM);
+  MachineInstrBuilder MIB = BuildMI(MBB, Jump, DL, NewDesc);
+
+  MIB.addReg(Jump->getOperand(0).getReg());
+
+  Iter tmpIter = Jump;
+  Jump = std::prev(Jump);
+  MBB.erase(tmpIter);
+
+  return Jump;
+}
+
 // For given opcode returns opcode of corresponding instruction with short
 // delay slot.
 static int getEquivalentCallShort(int Opcode) {
   switch (Opcode) {
   case Mips::BGEZAL:
     return Mips::BGEZALS_MM;
   case Mips::BLTZAL:
     return Mips::BLTZALS_MM;
if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None)) {
         continue;
       }
     }
 
     // If instruction is BEQ or BNE with one ZERO register, then instead of
     // adding NOP replace this instruction with the corresponding compact
     // branch instruction, i.e. BEQZC or BNEZC.
     unsigned Opcode = I->getOpcode();
-    if (InMicroMipsMode &&
-        (Opcode == Mips::BEQ || Opcode == Mips::BNE) &&
-        ((unsigned) I->getOperand(1).getReg()) == Mips::ZERO) {
-
+    if (InMicroMipsMode) {
+      switch (Opcode) {
+        case Mips::BEQ:
+        case Mips::BNE:
+          if (((unsigned) I->getOperand(1).getReg()) == Mips::ZERO) {
             I = replaceWithCompactBranch(MBB, I, I->getDebugLoc());
-
-    } else {
-      // Bundle the NOP to the instruction with the delay slot.
-      BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
-      MIBundleBuilder(MBB, I, std::next(I, 2));
-    }
-  }
+            continue;
+          }
+          break;
+        case Mips::JR:
+        case Mips::PseudoReturn:
+        case Mips::PseudoIndirectBranch:
+          // For microMIPS the PseudoReturn and PseudoIndirectBranch are allways
+          // expanded to JR_MM, so they can be replaced with JRC16_MM.
+          I = replaceWithCompactJump(MBB, I, I->getDebugLoc());
+          continue;
+        default:
+          break;
+      }
+    }
 
   return Changed;
 }
 
 /// createMipsDelaySlotFillerPass - Returns a pass that fills in delay
 /// slots in Mips MachineFunctions
 FunctionPass *llvm::createMipsDelaySlotFillerPass(MipsTargetMachine &tm) {
   return new Filler(tm);

llvm/trunk/test/CodeGen/Mips/longbranch.ll

 ; MICROMIPS-NEXT:     jr      $1
 ; MICROMIPS-NEXT:     addiu   $sp, $sp, 8
 
 ; MICROMIPS:   $[[BB0]]:
 ; MICROMIPS:        lw      $[[R1:[0-9]+]], %got(x)($[[GP]])
 ; MICROMIPS:        li16    $[[R2:[0-9]+]], 1
 ; MICROMIPS:        sw16    $[[R2]], 0($[[R1]])
 ; MICROMIPS:   $[[BB2]]:
-; MICROMIPS:        jr      $ra
-; MICROMIPS:        nop
+; MICROMIPS:        jrc      $ra
 
 
 ; Check the NaCl version.  Check that sp change is not in the branch delay slot
 ; of "jr $1" instruction.  Check that target of indirect branch "jr $1" is
 ; bundle aligned.
 
 ; NACL:        lui     $[[R0:[0-9]+]], %hi(_gp_disp)
 ; NACL:        addiu   $[[R0]], $[[R0]], %lo(_gp_disp)

llvm/trunk/test/CodeGen/Mips/micromips-compact-jump.ll

+; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN:   -disable-mips-delay-filler -O3 < %s | FileCheck %s
+
+define i32 @foo(i32 signext %a) #0 {
+entry:
+  ret i32 0
+}
+
+declare i32 @bar(i32 signext) #1
+
+; CHECK:      jrc

llvm/trunk/test/CodeGen/Mips/micromips-delay-slot-jr.ll

 
 declare i32 @puts(i8* nocapture readonly) #1
 
 !1 = !{!2, !2, i64 0}
 !2 = !{!"any pointer", !3, i64 0}
 !3 = !{!"omnipotent char", !4, i64 0}
 !4 = !{!"Simple C/C++ TBAA"}
 
-; CHECK:      jr
-; CHECK-NEXT: nop
+; CHECK:      jrc
 
 %struct.foostruct = type { [3 x float] }
 %struct.barstruct = type { %struct.foostruct, float }
 @bar_ary = common global [4 x %struct.barstruct] zeroinitializer, align 4
 define float* @spooky(i32 signext %i) #0 {
 
   %safe = getelementptr inbounds [4 x %struct.barstruct]* @bar_ary, i32 0, i32 %i, i32 1
   store float 1.420000e+02, float* %safe, align 4, !tbaa !1
   ret float* %safe
 }
 
 ; CHECK:      spooky:
-; CHECK:      jr $ra
-; CHECK-NEXT: nop
+; CHECK:      jrc $ra