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Differential D7413

[mips] Optimize code generation for 64-bit variable shift instructions.
ClosedPublic

Authored by vkalintiris on Feb 4 2015, 9:50 AM.

Details

Reviewers
dsanders
Commits
rG32177d6becc3: [mips] Optimize code generation for 64-bit variable shift instructions.
rL235376: [mips] Optimize code generation for 64-bit variable shift instructions.
Summary

The 64-bit version of the variable shift instructions uses the
shift_rotate_reg class which uses a GPR32Opnd to specify the variable
shift amount. With this patch we avoid the generation of a redundant
SLL instruction for the variable shift instructions in 64-bit targets.

Diff Detail

Repository
rL LLVM

Event Timeline

vkalintiris updated this revision to Diff 19329.Feb 4 2015, 9:50 AM
vkalintiris retitled this revision from to [mips] Optimize code generation for 64-bit variable shift instructions..
vkalintiris updated this object.
vkalintiris edited the test plan for this revision. (Show Details)
vkalintiris added a reviewer: dsanders.
vkalintiris added a subscriber: Unknown Object (MLST).
dsanders accepted this revision.Apr 21 2015, 3:20 AM
dsanders edited edge metadata.

LGTM

This revision is now accepted and ready to land.Apr 21 2015, 3:20 AM
Closed by commit rL235376: [mips] Optimize code generation for 64-bit variable shift instructions. (authored by vkalintiris). · Explain WhyApr 21 2015, 3:52 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
10 lines
test/
CodeGen/
Mips/
llvm-ir/
39 lines
41 lines
41 lines
6 lines

Diff 24110

llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td

Show First 20 Lines • Show All 496 Lines • ▼ Show 20 Lines
// Bypass trunc nodes for bitwise ops. // Bypass trunc nodes for bitwise ops.
def : MipsPat<(i32 (trunc (and GPR64:$lhs, GPR64:$rhs))), def : MipsPat<(i32 (trunc (and GPR64:$lhs, GPR64:$rhs))),
(EXTRACT_SUBREG (AND64 GPR64:$lhs, GPR64:$rhs), sub_32)>; (EXTRACT_SUBREG (AND64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
def : MipsPat<(i32 (trunc (or GPR64:$lhs, GPR64:$rhs))), def : MipsPat<(i32 (trunc (or GPR64:$lhs, GPR64:$rhs))),
(EXTRACT_SUBREG (OR64 GPR64:$lhs, GPR64:$rhs), sub_32)>; (EXTRACT_SUBREG (OR64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
def : MipsPat<(i32 (trunc (xor GPR64:$lhs, GPR64:$rhs))), def : MipsPat<(i32 (trunc (xor GPR64:$lhs, GPR64:$rhs))),
(EXTRACT_SUBREG (XOR64 GPR64:$lhs, GPR64:$rhs), sub_32)>; (EXTRACT_SUBREG (XOR64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
// variable shift instructions patterns
def : MipsPat<(shl GPR64:$rt, (i32 (trunc GPR64:$rs))),
(DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
def : MipsPat<(srl GPR64:$rt, (i32 (trunc GPR64:$rs))),
(DSRLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
def : MipsPat<(sra GPR64:$rt, (i32 (trunc GPR64:$rs))),
(DSRAV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))),
(DROTRV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
// 32-to-64-bit extension // 32-to-64-bit extension
def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>; def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>; def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>; def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
// Sign extend in register // Sign extend in register
def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)), def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
(SLL64_64 GPR64:$src)>; (SLL64_64 GPR64:$src)>;
▲ Show 20 Lines • Show All 98 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll

Show First 20 Lines • Show All 125 Lines • ▼ Show 20 Lines; ALL-LABEL: ashr_i64:
; 32R6: sll $[[T8:[0-9]+]], $4, 1 ; 32R6: sll $[[T8:[0-9]+]], $4, 1
; 32R6: sllv $[[T9:[0-9]+]], $[[T8]], $[[T7]] ; 32R6: sllv $[[T9:[0-9]+]], $[[T8]], $[[T7]]
; 32R6: or $[[T10:[0-9]+]], $[[T9]], $[[T6]] ; 32R6: or $[[T10:[0-9]+]], $[[T9]], $[[T6]]
; 32R6: seleqz $[[T11:[0-9]+]], $[[T10]], $[[T1]] ; 32R6: seleqz $[[T11:[0-9]+]], $[[T10]], $[[T1]]
; 32R6: selnez $[[T12:[0-9]+]], $[[T0]], $[[T1]] ; 32R6: selnez $[[T12:[0-9]+]], $[[T0]], $[[T1]]
; 32R6: jr $ra ; 32R6: jr $ra
; 32R6: or $3, $[[T0]], $[[T11]] ; 32R6: or $3, $[[T0]], $[[T11]]
; FIXME: The sll instruction below is redundant. ; GP64: dsrav $2, $4, $5
; GP64: sll $[[T0:[0-9]+]], $5, 0
; GP64: dsrav $2, $4, $[[T0]]
%r = ashr i64 %a, %b %r = ashr i64 %a, %b
ret i64 %r ret i64 %r
} }
define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) { define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
entry: entry:
; ALL-LABEL: ashr_i128: ; ALL-LABEL: ashr_i128:
; GP32: lw $25, %call16(__ashrti3)($gp) ; GP32: lw $25, %call16(__ashrti3)($gp)
; M3: sll $[[T0:[0-9]+]], $7, 0 ; M3: sll $[[T0:[0-9]+]], $7, 0
; M3: dsrav $[[T1:[0-9]+]], $4, $[[T0]] ; M3: dsrav $[[T1:[0-9]+]], $4, $7
; M3: andi $[[T2:[0-9]+]], $[[T0]], 32 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 32
; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
; M3: move $3, $[[T1]] ; M3: move $3, $[[T1]]
; M3: dsrlv $[[T4:[0-9]+]], $5, $[[T0]] ; M3: dsrlv $[[T4:[0-9]+]], $5, $7
; M3: dsll $[[T5:[0-9]+]], $4, 1 ; M3: dsll $[[T5:[0-9]+]], $4, 1
; M3: not $[[T6:[0-9]+]], $[[T0]] ; M3: not $[[T6:[0-9]+]], $[[T0]]
; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]] ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
; M3: or $3, $[[T7]], $[[T4]] ; M3: or $3, $[[T7]], $[[T4]]
; M3: $[[BB0]]: ; M3: $[[BB0]]:
; M3: beqz $[[T3]], $[[BB1:BB[0-9_]+]] ; M3: beqz $[[T3]], $[[BB1:BB[0-9_]+]]
; M3: nop ; M3: nop
; M3: dsra $2, $4, 31 ; M3: dsra $2, $4, 31
; M3: $[[BB1]]: ; M3: $[[BB1]]:
; M3: jr $ra ; M3: jr $ra
; M3: nop ; M3: nop
; GP64-NOT-R6: sll $[[T0:[0-9]+]], $7, 0 ; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7
; GP64-NOT-R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]] ; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1
; GP64-NOT-R6: dsll $[[T2:[0-9]+]], $4, 1 ; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0
; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T0]] ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]]
; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]] ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
; GP64-NOT-R6: or $3, $[[T4]], $[[T1]] ; GP64-NOT-R6: or $3, $[[T4]], $[[T0]]
; GP64-NOT-R6: dsrav $2, $4, $[[T0]] ; GP64-NOT-R6: dsrav $2, $4, $7
; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 32 ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 32
; GP64-NOT-R6: movn $3, $2, $[[T5]] ; GP64-NOT-R6: movn $3, $2, $[[T5]]
; GP64-NOT-R6: dsra $[[T6:[0-9]+]], $4, 31 ; GP64-NOT-R6: dsra $[[T6:[0-9]+]], $4, 31
; GP64-NOT-R6: jr $ra ; GP64-NOT-R6: jr $ra
; GP64-NOT-R6: movn $2, $[[T6]], $[[T5]] ; GP64-NOT-R6: movn $2, $[[T6]], $[[T5]]
; 64R6: sll $[[T0:[0-9]+]], $7, 0 ; 64R6: dsrav $[[T0:[0-9]+]], $4, $7
; 64R6: dsrav $[[T1:[0-9]+]], $4, $[[T0]] ; 64R6: sll $[[T1:[0-9]+]], $7, 0
; 64R6: andi $[[T2:[0-9]+]], $[[T0]], 32 ; 64R6: andi $[[T2:[0-9]+]], $[[T1]], 32
; 64R6: sll $[[T3:[0-9]+]], $[[T2]], 0 ; 64R6: sll $[[T3:[0-9]+]], $[[T2]], 0
; 64R6: seleqz $[[T4:[0-9]+]], $[[T1]], $[[T3]] ; 64R6: seleqz $[[T4:[0-9]+]], $[[T0]], $[[T3]]
; 64R6: dsra $[[T5:[0-9]+]], $4, 31 ; 64R6: dsra $[[T5:[0-9]+]], $4, 31
; 64R6: selnez $[[T6:[0-9]+]], $[[T5]], $[[T3]] ; 64R6: selnez $[[T6:[0-9]+]], $[[T5]], $[[T3]]
; 64R6: or $2, $[[T6]], $[[T4]] ; 64R6: or $2, $[[T6]], $[[T4]]
; 64R6: dsrlv $[[T7:[0-9]+]], $5, $[[T0]] ; 64R6: dsrlv $[[T7:[0-9]+]], $5, $7
; 64R6: dsll $[[T8:[0-9]+]], $4, 1 ; 64R6: dsll $[[T8:[0-9]+]], $4, 1
; 64R6: not $[[T9:[0-9]+]], $[[T0]] ; 64R6: not $[[T9:[0-9]+]], $[[T1]]
; 64R6: dsllv $[[T10:[0-9]+]], $[[T8]], $[[T9]] ; 64R6: dsllv $[[T10:[0-9]+]], $[[T8]], $[[T9]]
; 64R6: or $[[T11:[0-9]+]], $[[T10]], $[[T7]] ; 64R6: or $[[T11:[0-9]+]], $[[T10]], $[[T7]]
; 64R6: seleqz $[[T12:[0-9]+]], $[[T11]], $[[T3]] ; 64R6: seleqz $[[T12:[0-9]+]], $[[T11]], $[[T3]]
; 64R6: selnez $[[T13:[0-9]+]], $[[T1]], $[[T3]] ; 64R6: selnez $[[T13:[0-9]+]], $[[T0]], $[[T3]]
; 64R6: jr $ra ; 64R6: jr $ra
; 64R6: or $3, $[[T13]], $[[T12]] ; 64R6: or $3, $[[T13]], $[[T12]]
%r = ashr i128 %a, %b %r = ashr i128 %a, %b
ret i128 %r ret i128 %r
} }

llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll

Show First 20 Lines • Show All 119 Lines • ▼ Show 20 Lines; ALL-LABEL: lshr_i64:
; 32R6: andi $[[T5:[0-9]+]], $7, 32 ; 32R6: andi $[[T5:[0-9]+]], $7, 32
; 32R6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T3]] ; 32R6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T3]]
; 32R6: srlv $[[T7:[0-9]+]], $4, $7 ; 32R6: srlv $[[T7:[0-9]+]], $4, $7
; 32R6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]] ; 32R6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]]
; 32R6: or $3, $[[T8]], $[[T6]] ; 32R6: or $3, $[[T8]], $[[T6]]
; 32R6: jr $ra ; 32R6: jr $ra
; 32R6: seleqz $2, $[[T7]], $[[T5]] ; 32R6: seleqz $2, $[[T7]], $[[T5]]
; GP64: sll $[[T0:[0-9]+]], $5, 0 ; GP64: dsrlv $2, $4, $5
; GP64: dsrlv $2, $4, $[[T0]]
%r = lshr i64 %a, %b %r = lshr i64 %a, %b
ret i64 %r ret i64 %r
} }
define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) { define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
entry: entry:
; ALL-LABEL: lshr_i128: ; ALL-LABEL: lshr_i128:
; GP32: lw $25, %call16(__lshrti3)($gp) ; GP32: lw $25, %call16(__lshrti3)($gp)
; M3: sll $[[T0:[0-9]+]], $7, 0 ; M3: sll $[[T0:[0-9]+]], $7, 0
; M3: dsrlv $[[T1:[0-9]+]], $4, $[[T0]] ; M3: dsrlv $[[T1:[0-9]+]], $4, $7
; M3: andi $[[T2:[0-9]+]], $[[T0]], 32 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 32
; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
; M3: move $3, $[[T1]] ; M3: move $3, $[[T1]]
; M3: dsrlv $[[T4:[0-9]+]], $5, $[[T0]] ; M3: dsrlv $[[T4:[0-9]+]], $5, $7
; M3: dsll $[[T5:[0-9]+]], $4, 1 ; M3: dsll $[[T5:[0-9]+]], $4, 1
; M3: not $[[T6:[0-9]+]], $[[T0]] ; M3: not $[[T6:[0-9]+]], $[[T0]]
; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]] ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
; M3: or $3, $[[T7]], $[[T4]] ; M3: or $3, $[[T7]], $[[T4]]
; M3: $[[BB0]]: ; M3: $[[BB0]]:
; M3: bnez $[[T3]], $[[BB1:BB[0-9_]+]] ; M3: bnez $[[T3]], $[[BB1:BB[0-9_]+]]
; M3: daddiu $2, $zero, 0 ; M3: daddiu $2, $zero, 0
; M3: move $2, $[[T1]] ; M3: move $2, $[[T1]]
; M3: $[[BB1]]: ; M3: $[[BB1]]:
; M3: jr $ra ; M3: jr $ra
; M3: nop ; M3: nop
; GP64-NOT-R6: sll $[[T0:[0-9]+]], $7, 0 ; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7
; GP64-NOT-R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]] ; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1
; GP64-NOT-R6: dsll $[[T2:[0-9]+]], $4, 1 ; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0
; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T0]] ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]]
; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]] ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
; GP64-NOT-R6: or $3, $[[T4]], $[[T1]] ; GP64-NOT-R6: or $3, $[[T4]], $[[T0]]
; GP64-NOT-R6: dsrlv $2, $4, $[[T0]] ; GP64-NOT-R6: dsrlv $2, $4, $7
; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 32 ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 32
; GP64-NOT-R6: movn $3, $2, $[[T5]] ; GP64-NOT-R6: movn $3, $2, $[[T5]]
; GP64-NOT-R6: jr $ra ; GP64-NOT-R6: jr $ra
; GP64-NOT-R6: movn $2, $zero, $1 ; GP64-NOT-R6: movn $2, $zero, $1
; 64R6: sll $[[T0:[0-9]+]], $7, 0 ; 64R6: dsrlv $[[T0:[0-9]+]], $5, $7
; 64R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]] ; 64R6: dsll $[[T1:[0-9]+]], $4, 1
; 64R6: dsll $[[T2:[0-9]+]], $4, 1 ; 64R6: sll $[[T2:[0-9]+]], $7, 0
; 64R6: not $[[T3:[0-9]+]], $[[T0]] ; 64R6: not $[[T3:[0-9]+]], $[[T2]]
; 64R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]] ; 64R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
; 64R6: or $[[T5:[0-9]+]], $[[T4]], $[[T1]] ; 64R6: or $[[T5:[0-9]+]], $[[T4]], $[[T0]]
; 64R6: andi $[[T6:[0-9]+]], $[[T0]], 32 ; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 32
; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0 ; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0
; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]] ; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]]
; 64R6: dsrlv $[[T9:[0-9]+]], $4, $[[T0]] ; 64R6: dsrlv $[[T9:[0-9]+]], $4, $7
; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]] ; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]]
; 64R6: or $3, $[[T10]], $[[T8]] ; 64R6: or $3, $[[T10]], $[[T8]]
; 64R6: jr $ra ; 64R6: jr $ra
; 64R6: seleqz $2, $[[T0]], $[[T7]] ; 64R6: seleqz $2, $[[T9]], $[[T7]]
%r = lshr i128 %a, %b %r = lshr i128 %a, %b
ret i128 %r ret i128 %r
} }

llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll

Show First 20 Lines • Show All 131 Lines • ▼ Show 20 Lines; ALL-LABEL: shl_i64:
; 32R6: andi $[[T5:[0-9]+]], $7, 32 ; 32R6: andi $[[T5:[0-9]+]], $7, 32
; 32R6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T2]] ; 32R6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T2]]
; 32R6: sllv $[[T7:[0-9]+]], $5, $7 ; 32R6: sllv $[[T7:[0-9]+]], $5, $7
; 32R6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]] ; 32R6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]]
; 32R6: or $2, $[[T8]], $[[T6]] ; 32R6: or $2, $[[T8]], $[[T6]]
; 32R6: jr $ra ; 32R6: jr $ra
; 32R6: seleqz $3, $[[T7]], $[[T5]] ; 32R6: seleqz $3, $[[T7]], $[[T5]]
; GP64: sll $[[T0:[0-9]+]], $5, 0 ; GP64: dsllv $2, $4, $5
; GP64: dsllv $2, $4, $1
%r = shl i64 %a, %b %r = shl i64 %a, %b
ret i64 %r ret i64 %r
} }
define signext i128 @shl_i128(i128 signext %a, i128 signext %b) { define signext i128 @shl_i128(i128 signext %a, i128 signext %b) {
entry: entry:
; ALL-LABEL: shl_i128: ; ALL-LABEL: shl_i128:
; GP32: lw $25, %call16(__ashlti3)($gp) ; GP32: lw $25, %call16(__ashlti3)($gp)
; M3: sll $[[T0:[0-9]+]], $7, 0 ; M3: sll $[[T0:[0-9]+]], $7, 0
; M3: dsllv $[[T1:[0-9]+]], $5, $[[T0]] ; M3: dsllv $[[T1:[0-9]+]], $5, $7
; M3: andi $[[T2:[0-9]+]], $[[T0]], 32 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 32
; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
; M3: move $2, $[[T1]] ; M3: move $2, $[[T1]]
; M3: dsllv $[[T4:[0-9]+]], $4, $[[T0]] ; M3: dsllv $[[T4:[0-9]+]], $4, $7
; M3: dsrl $[[T5:[0-9]+]], $5, 1 ; M3: dsrl $[[T5:[0-9]+]], $5, 1
; M3: not $[[T6:[0-9]+]], $[[T0]] ; M3: not $[[T6:[0-9]+]], $[[T0]]
; M3: dsrlv $[[T7:[0-9]+]], $[[T5]], $[[T6]] ; M3: dsrlv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
; M3: or $2, $[[T4]], $[[T7]] ; M3: or $2, $[[T4]], $[[T7]]
; M3: $[[BB0]]: ; M3: $[[BB0]]:
; M3: bnez $[[T3]], $[[BB1:BB[0-9_]+]] ; M3: bnez $[[T3]], $[[BB1:BB[0-9_]+]]
; M3: daddiu $3, $zero, 0 ; M3: daddiu $3, $zero, 0
; M3: move $3, $[[T1]] ; M3: move $3, $[[T1]]
; M3: $[[BB1]]: ; M3: $[[BB1]]:
; M3: jr $ra ; M3: jr $ra
; M3: nop ; M3: nop
; GP64-NOT-R6: sll $[[T0:[0-9]+]], $7, 0 ; GP64-NOT-R6: dsllv $[[T0:[0-9]+]], $4, $7
; GP64-NOT-R6: dsllv $[[T1:[0-9]+]], $4, $[[T0]] ; GP64-NOT-R6: dsrl $[[T1:[0-9]+]], $5, 1
; GP64-NOT-R6: dsrl $[[T2:[0-9]+]], $5, 1 ; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0
; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T0]] ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]]
; GP64-NOT-R6: dsrlv $[[T4:[0-9]+]], $[[T2]], $[[T3]] ; GP64-NOT-R6: dsrlv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
; GP64-NOT-R6: or $2, $[[T1]], $[[T4]] ; GP64-NOT-R6: or $2, $[[T0]], $[[T4]]
; GP64-NOT-R6: dsllv $3, $5, $[[T0]] ; GP64-NOT-R6: dsllv $3, $5, $7
; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 32 ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 32
; GP64-NOT-R6: movn $2, $3, $[[T5]] ; GP64-NOT-R6: movn $2, $3, $[[T5]]
; GP64-NOT-R6: jr $ra ; GP64-NOT-R6: jr $ra
; GP64-NOT-R6: movn $3, $zero, $1 ; GP64-NOT-R6: movn $3, $zero, $1
; 64R6: sll $[[T0:[0-9]+]], $7, 0 ; 64R6: dsllv $[[T0:[0-9]+]], $4, $7
; 64R6: dsllv $[[T1:[0-9]+]], $4, $[[T0]] ; 64R6: dsrl $[[T1:[0-9]+]], $5, 1
; 64R6: dsrl $[[T2:[0-9]+]], $5, 1 ; 64R6: sll $[[T2:[0-9]+]], $7, 0
; 64R6: not $[[T3:[0-9]+]], $[[T0]] ; 64R6: not $[[T3:[0-9]+]], $[[T2]]
; 64R6: dsrlv $[[T4:[0-9]+]], $[[T2]], $[[T3]] ; 64R6: dsrlv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
; 64R6: or $[[T5:[0-9]+]], $[[T1]], $[[T4]] ; 64R6: or $[[T5:[0-9]+]], $[[T0]], $[[T4]]
; 64R6: andi $[[T6:[0-9]+]], $[[T0]], 32 ; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 32
; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0 ; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0
; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]] ; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]]
; 64R6: dsllv $[[T9:[0-9]+]], $5, $[[T0]] ; 64R6: dsllv $[[T9:[0-9]+]], $5, $7
; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]] ; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]]
; 64R6: or $2, $[[T10]], $[[T8]] ; 64R6: or $2, $[[T10]], $[[T8]]
; 64R6: jr $ra ; 64R6: jr $ra
; 64R6: seleqz $3, $[[T0]], $[[T7]] ; 64R6: seleqz $3, $[[T9]], $[[T7]]
%r = shl i128 %a, %b %r = shl i128 %a, %b
ret i128 %r ret i128 %r
} }

llvm/trunk/test/CodeGen/Mips/mips64shift.ll

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entry: entry:
; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 40 ; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 40
%shr = lshr i64 %a0, 40 %shr = lshr i64 %a0, 40
ret i64 %shr ret i64 %shr
} }
define i64 @f9(i64 %a0, i64 %a1) nounwind readnone { define i64 @f9(i64 %a0, i64 %a1) nounwind readnone {
entry: entry:
; CHECK-NOT: sll
; CHECK: drotrv ; CHECK: drotrv
%shr = lshr i64 %a0, %a1 %shr = lshr i64 %a0, %a1
%sub = sub i64 64, %a1 %sub = sub i64 64, %a1
%shl = shl i64 %a0, %sub %shl = shl i64 %a0, %sub
%or = or i64 %shl, %shr %or = or i64 %shl, %shr
ret i64 %or ret i64 %or
} }
define i64 @f10(i64 %a0, i64 %a1) nounwind readnone { define i64 @f10(i64 %a0, i64 %a1) nounwind readnone {
entry: entry:
; CHECK-NOT: sll
; CHECK: drotrv ; CHECK: drotrv
%shl = shl i64 %a0, %a1 %shl = shl i64 %a0, %a1
%sub = sub i64 64, %a1 %sub = sub i64 64, %a1
%shr = lshr i64 %a0, %sub %shr = lshr i64 %a0, %sub
%or = or i64 %shr, %shl %or = or i64 %shr, %shl
ret i64 %or ret i64 %or
} }
define i64 @f11(i64 %a0) nounwind readnone { define i64 @f11(i64 %a0) nounwind readnone {
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