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Differential D6810

[Mips][Disassembler][R6] Disassembler crashes on cache/pref instructions for r6
ClosedPublic

Authored by vmedic on Dec 30 2014, 4:55 AM.

Details

Reviewers
sstankovic
dsanders
Summary

When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions.

Diff Detail

Event Timeline

vmedic updated this revision to Diff 17715.Dec 30 2014, 4:55 AM
vmedic retitled this revision from to [Mips][Disassembler][R6] Disassembler crashes on cache/pref instructions for r6.
vmedic updated this object.
vmedic edited the test plan for this revision. (Show Details)
vmedic added reviewers: dsanders, sstankovic.
vmedic added a subscriber: Unknown Object (MLST).
dsanders accepted this revision.Jan 28 2015, 8:05 AM
dsanders edited edge metadata.

LGTM with a few nits

lib/Target/Mips/Disassembler/MipsDisassembler.cpp
256–258

Nit: Indentation

1120–1122

Nit: Indentation

1123

Nit: Just for consistency, we should probably use 'fieldFromInstruction(Insn, 7, 9)' instead of '(Insn & 0xff90) >> 7'

1127

The same opcode is used for MIPS64r6 too. We should pick GPR32/GPR64 according to the subtarget

test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
144

Nit: Blank line at EOF

test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
144

Nit: Blank line at EOF

test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
162

Nit: Blank line at EOF

test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
162

Nit: Blank line at EOF

This revision is now accepted and ready to land.Jan 28 2015, 8:05 AM
vmedic closed this revision.Jan 29 2015, 3:35 AM

Suggested changes applied. Committed revision 227430.

Revision Contents

PathSize
lib/
Target/
Mips/
Disassembler/
22 lines
1 line
test/
MC/
Disassembler/
Mips/
mips32r6/
3 lines
3 lines
2 lines
mips64r6/
3 lines
3 lines
2 lines

Diff 17715

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

Context not available.
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
dsandersUnsubmitted
Not Done
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Nit: Indentation

dsanders: Nit: Indentation
static DecodeStatus DecodeCacheOpMM(MCInst &Inst, static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
unsigned Insn, unsigned Insn,
uint64_t Address, uint64_t Address,
Context not available.
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
dsandersUnsubmitted
Not Done
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Nit: Indentation

dsanders: Nit: Indentation
int Offset = SignExtend32<9>((Insn & 0xff80) >> 7);
dsandersUnsubmitted
Not Done
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Nit: Just for consistency, we should probably use 'fieldFromInstruction(Insn, 7, 9)' instead of '(Insn & 0xff90) >> 7'

dsanders: Nit: Just for consistency, we should probably use 'fieldFromInstruction(Insn, 7, 9)' instead of…
unsigned Hint = fieldFromInstruction(Insn, 16, 5);
unsigned Base = fieldFromInstruction(Insn, 21, 5);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
dsandersUnsubmitted
Not Done
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The same opcode is used for MIPS64r6 too. We should pick GPR32/GPR64 according to the subtarget

dsanders: The same opcode is used for MIPS64r6 too. We should pick GPR32/GPR64 according to the subtarget
Inst.addOperand(MCOperand::CreateReg(Base));
Inst.addOperand(MCOperand::CreateImm(Offset));
Inst.addOperand(MCOperand::CreateImm(Hint));
return MCDisassembler::Success;
}
static DecodeStatus DecodeSyncI(MCInst &Inst, static DecodeStatus DecodeSyncI(MCInst &Inst,
unsigned Insn, unsigned Insn,
uint64_t Address, uint64_t Address,
Context not available.

lib/Target/Mips/Mips32r6InstrInfo.td

Context not available.
dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint); dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
string AsmString = !strconcat(instr_asm, "\t$hint, $addr"); string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
list<dag> Pattern = []; list<dag> Pattern = [];
string DecoderMethod = "DecodeCacheOpR6";
} }
class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, GPR32Opnd>; class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, GPR32Opnd>;
Context not available.

test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt

Context not available.
0x33 0xfe 0x1d 0x02 # CHECK: tltu $16, $sp, 1016 0x33 0xfe 0x1d 0x02 # CHECK: tltu $16, $sp, 1016
0x36 0x00 0xd1 0x00 # CHECK: tne $6, $17 0x36 0x00 0xd1 0x00 # CHECK: tne $6, $17
0x76 0xdd 0xe8 0x00 # CHECK: tne $7, $8, 885 0x76 0xdd 0xe8 0x00 # CHECK: tne $7, $8, 885
0x25 0x04 0xa1 0x7c # CHECK: cache 1, 8($5)
0x35 0x04 0xa1 0x7c # CHECK: pref 1, 8($5
Context not available.
dsandersUnsubmitted
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Nit: Blank line at EOF

dsanders: Nit: Blank line at EOF

test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt

Context not available.
0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016 0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016
0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17 0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17
0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885 0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885
0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5)
0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5)
Context not available.
dsandersUnsubmitted
Not Done
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Nit: Blank line at EOF

dsanders: Nit: Blank line at EOF

test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt

Context not available.
0x60 0xc0 0x00 0x40 # CHECK: bnec $6, $zero, 256 0x60 0xc0 0x00 0x40 # CHECK: bnec $6, $zero, 256
0x60 0xa0 0x00 0x40 # CHECK: bnec $5, $zero, 256 0x60 0xa0 0x00 0x40 # CHECK: bnec $5, $zero, 256
0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256 0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256
0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5)
0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256 0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256
0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256 0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256
0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5)
0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1) 0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1)
0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6) 0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6)
0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18) 0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18)
Context not available.

test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt

Context not available.
0x33 0xfe 0x1d 0x02 # CHECK: tltu $16, $sp, 1016 0x33 0xfe 0x1d 0x02 # CHECK: tltu $16, $sp, 1016
0x36 0x00 0xd1 0x00 # CHECK: tne $6, $17 0x36 0x00 0xd1 0x00 # CHECK: tne $6, $17
0x76 0xdd 0xe8 0x00 # CHECK: tne $7, $8, 885 0x76 0xdd 0xe8 0x00 # CHECK: tne $7, $8, 885
0x25 0x04 0xa1 0x7c # CHECK: cache 1, 8($5)
0x35 0x04 0xa1 0x7c # CHECK: pref 1, 8($5
Context not available.
dsandersUnsubmitted
Not Done
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Nit: Blank line at EOF

dsanders: Nit: Blank line at EOF

test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt

Context not available.
0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016 0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016
0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17 0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17
0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885 0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885
0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5)
0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5)
Context not available.
dsandersUnsubmitted
Not Done
ReplyInline Actions

Nit: Blank line at EOF

dsanders: Nit: Blank line at EOF

test/MC/Disassembler/Mips/mips64r6/valid-xfail-mips64r6.txt

Context not available.
0x60 0xc0 0x00 0x40 # CHECK: bnec $6, $zero, 256 0x60 0xc0 0x00 0x40 # CHECK: bnec $6, $zero, 256
0x60 0xa0 0x00 0x40 # CHECK: bnec $5, $zero, 256 0x60 0xa0 0x00 0x40 # CHECK: bnec $5, $zero, 256
0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256 0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256
0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5)
0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256 0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256
0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256 0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256
0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5)
0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1) 0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1)
0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6) 0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6)
0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18) 0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18)
Context not available.