AVX-512 Intrinsics for ER instructions

[delena]

Summary

Intrinsics for ERI - 3 instructions vrcp28, vrsqrt28, vexp2, only vector forms.
Intrinsics include SAE (Suppres All Exceptions) parameter.

[rob.khasanov]

Hi Elena,

LGTM.

[anemet]

This looks awesome to me, thanks!

[delena]

Adam, Robert,
thank you for the quick response!

Committed revision 221774.

[delena]

Added comments, asked by Adam.

[anemet]

Elena,

Did you upload this to the wrong review?

Adam

[anemet]

lib/Target/X86/X86InstrAVX512.td

5

Please also mention that for scalar types we map them to the smallest (128-bit) vector type with the same element type. And the motivation: so that masking logic can be transferred to them.

LGTM with something like that.

[delena]

Thank you.
Committed revision 223761

• Elena

lib/Target/X86/X86ISelLowering.cpp

switch (Op.getOpcode()) {
       case X86ISD::CMPMU:
         return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
     }
     if (PreservedSrc.getOpcode() == ISD::UNDEF)
       PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
     return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
 }
 
+/// \brief Creates an SDNode for a predicated scalar operation.
+/// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
+/// The mask is comming as MVT::i8 and it should be truncated
+/// to MVT::i1 while lowering masking intrinsics.
+/// The main difference between ScalarMaskingNode and VectorMaskingNode is using
+/// "X86select" instead of "vselect". We just can't create the "vselect" node for 
+/// a scalar instruction.
 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
                                     SDValue PreservedSrc,
                                     const X86Subtarget *Subtarget,
                                     SelectionDAG &DAG) {
     if (isAllOnes(Mask))
       return Op;
 
     EVT VT = Op.getValueType();

lib/Target/X86/X86InstrAVX512.td

 // Group template arguments that can be derived from the vector type (EltNum x
 // EltVT).  These are things like the register class for the writemask, etc.
 // The idea is to pass one of these as the template argument rather than the
 // individual arguments.
+// The template is also used for scalar types, in this case numelts is 1.
 class X86VectorVTInfo<int numelts, ValueType EltVT, RegisterClass rc,
                       string suffix = ""> {
   RegisterClass RC = rc;
   int NumElts = numelts;
 
   // Corresponding mask register class.
   RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
 
   // Corresponding write-mask register class.
   RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
 
   // The GPR register class that can hold the write mask.  Use GR8 for fewer
   // than 8 elements.  Use shift-right and equal to work around the lack of
   // !lt in tablegen.
   RegisterClass MRC =
     !cast<RegisterClass>("GR" #
                          !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
 
   // Suffix used in the instruction mnemonic.
   string Suffix = suffix;
 
-  int NumEltsInVT = !if (!eq (NumElts, 1),
-                         !if (!eq (EltVT.Size, 32), 4,
-                         !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts);
-
-  string VTName = "v" # NumEltsInVT # EltVT;
+  // VTName is a string name for vector VT. For vector types it will be
+  // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
+  // It is a little bit complex for scalar types, where NumElts = 1.
+  // In this case we build v4f32 or v2f64
+  string VTName = "v" # !if (!eq (NumElts, 1),
+                        !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
 
   // The vector VT.
   ValueType VT = !cast<ValueType>(VTName);
 
   string EltTypeName = !cast<string>(EltVT);
   // Size of the element type in bits, e.g. 32 for v16i32.
   string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
   int EltSize = EltVT.Size;