LLVM incorrectly folds xor into select

[olista01]

Summary

LLVM replaces the SelectionDAG pattern (xor (set_cc cc x y) 1) with
(set_cc !cc x y), which is only correct when the xor has type i1.
Instead, we should check that the constant operand to the xor is all
ones.

[t.p.northover]

Hi Oliver,

This looks fine. Go for it.

Tim.

[olista01]

Thanks, committed revision 221693.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

SDValue DAGCombiner::visitXOR(SDNode *N) {
   if (N1C && N1C->isNullValue())
     return N0;
   // reassociate xor
   SDValue RXOR = ReassociateOps(ISD::XOR, SDLoc(N), N0, N1);
   if (RXOR.getNode())
     return RXOR;
 
   // fold !(x cc y) -> (x !cc y)
-  if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
+  if (N1C && N1C->getAPIntValue().isAllOnesValue() &&
+      isSetCCEquivalent(N0, LHS, RHS, CC)) {
     bool isInt = LHS.getValueType().isInteger();
     ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
                                                isInt);
 
     if (!LegalOperations ||
         TLI.isCondCodeLegal(NotCC, LHS.getSimpleValueType())) {
       switch (N0.getOpcode()) {
       default:

test/CodeGen/ARM/select_xform.ll

 ; T2: t14
 ; T2: cmp r1, #10
 ; T2: subgt r0, #1
   %cmp = icmp sgt i32 %a, 10
   %conv = sext i1 %cmp to i32
   %add = add i32 %conv, %c
   ret i32 %add
 }
+
+; Do not fold the xor into the select
+define i32 @t15(i32 %p1, i32 %p2, i32 %p3) {
+entry:
+; ARM: cmp            r0, #8
+; ARM: mov{{(le|gt)}} [[REG:r[0-9]+]], {{r[0-9]+}}
+; ARM: eor            r0, [[REG]], #1
+
+; T2: cmp       r0, #8
+; T2: it        [[CC:(le|gt)]]
+; T2: mov[[CC]] [[REG:r[0-9]+]], {{r[0-9]+}}
+; T2: eor       r0, [[REG:r[0-9]+]], #1
+  %cmp = icmp sgt i32 %p1, 8
+  %a = select i1 %cmp, i32 %p2, i32 %p3
+  %xor = xor i32 %a, 1
+  ret i32 %xor
+}