[X86] Use ADD/SUB instead of INC/DEC for Haswell and Broadwell CPUs

[volkalexey]

Summary

This patch enables FeatureSlowIncDec for Haswell and Broadwell processors.
This feature was enabled for KNL and SKX CPUs before.

[dblaikie]

Tests?

[volkalexey]

I added test for FeatureSlowIncDec.

[volkalexey]

Ping

[qcolombet]

I do not see the relationship between the test case and the feature you are adding.
I would expect the test case to use a Haswell and a Broadwell processor.

Any performance numbers on this change?

Thanks.
-Quentin

[volkalexey]

This test is for feature slow-incdec which is enabled also for Silvermont, KNL and SKX.
I see from other tests that this is common practice to test features itself and not to test that CPU has some feature.

I didn't see major performance impact due to this change, only small improvements on some SPEC2000 tests (by 1-2%).
I enabled this feature per Intel optimization manual:
Assembly/Compiler Coding Rule33. (M impact, H generality)INC and DEC instructions should
be replaced with ADD or SUB instructions, because ADD and SUB overwrite all flags, whereas INC and
DEC do not, therefore creating false dependencies on earlier instructions that set the flags.

Also GCC avoids generation of INC/DEC and uses ADD and SUB.

[qcolombet]

Thanks for update.

LGTM then.

-Quentin

Closed by commit rL222141 (authored by volkalex).

llvm/trunk/lib/Target/X86/X86.td

def : ProcessorModel<"core-avx-i", SandyBridgeModel,
                       FeatureF16C, FeatureFSGSBase]>;
 
 // Haswell
 def : ProcessorModel<"core-avx2", HaswellModel,
                      [FeatureAVX2, FeatureCMPXCHG16B, FeatureFastUAMem,
                       FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
                       FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT,
                       FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM,
-                      FeatureHLE]>;
+                      FeatureHLE, FeatureSlowIncDec]>;
 
 // Broadwell
 def : ProcessorModel<"broadwell", HaswellModel,
                      [FeatureAVX2, FeatureCMPXCHG16B, FeatureFastUAMem,
                       FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
                       FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT,
                       FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM,
-                      FeatureHLE, FeatureADX, FeatureRDSEED, FeatureSMAP]>;
+                      FeatureHLE, FeatureADX, FeatureRDSEED, FeatureSMAP,
+                      FeatureSlowIncDec]>;
 // KNL
 // FIXME: define KNL model
 def : ProcessorModel<"knl", HaswellModel,
                      [FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI,
                       FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
                       FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
                       FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
                       FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,

llvm/trunk/test/CodeGen/X86/fma-phi-213-to-231.ll

 ; RUN: llc < %s -mcpu=core-avx2 | FileCheck %s
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.10.0"
 
 ; CHECK-LABEL: fmaddsubpd_loop
 ; CHECK: [[BODYLBL:LBB.+]]:
 ; CHECK:   vfmaddsub231pd        %ymm{{[0-9]+}}, %ymm{{[0-9]+}}, %ymm{{[0-9]+}}
 ; CHECK: [[INCLBL:LBB.+]]:
-; CHECK:   incl  [[INDREG:%[a-z0-9]+]]
+; CHECK:   addl  $1, [[INDREG:%[a-z0-9]+]]
 ; CHECK:   cmpl  {{%.+}}, [[INDREG]]
 ; CHECK:   jl    [[BODYLBL]]
 define <4 x double> @fmaddsubpd_loop(i32 %iter, <4 x double> %a, <4 x double> %b, <4 x double> %c) {
 entry:
   br label %for.cond
 
 for.cond:
   %c.addr.0 = phi <4 x double> [ %c, %entry ], [ %0, %for.inc ]

 for.end:
   ret <4 x double> %c.addr.0
 }
 
 ; CHECK-LABEL: fmsubaddpd_loop
 ; CHECK: [[BODYLBL:LBB.+]]:
 ; CHECK:   vfmsubadd231pd        %ymm{{[0-9]+}}, %ymm{{[0-9]+}}, %ymm{{[0-9]+}}
 ; CHECK: [[INCLBL:LBB.+]]:
-; CHECK:   incl  [[INDREG:%[a-z0-9]+]]
+; CHECK:   addl  $1, [[INDREG:%[a-z0-9]+]]
 ; CHECK:   cmpl  {{%.+}}, [[INDREG]]
 ; CHECK:   jl    [[BODYLBL]]
 define <4 x double> @fmsubaddpd_loop(i32 %iter, <4 x double> %a, <4 x double> %b, <4 x double> %c) {
 entry:
   br label %for.cond
 
 for.cond:
   %c.addr.0 = phi <4 x double> [ %c, %entry ], [ %0, %for.inc ]

 for.end:
   ret <4 x double> %c.addr.0
 }
 
 ; CHECK-LABEL: fmaddpd_loop
 ; CHECK: [[BODYLBL:LBB.+]]:
 ; CHECK:   vfmadd231pd        %ymm{{[0-9]+}}, %ymm{{[0-9]+}}, %ymm{{[0-9]+}}
 ; CHECK: [[INCLBL:LBB.+]]:
-; CHECK:   incl  [[INDREG:%[a-z0-9]+]]
+; CHECK:   addl  $1, [[INDREG:%[a-z0-9]+]]
 ; CHECK:   cmpl  {{%.+}}, [[INDREG]]
 ; CHECK:   jl    [[BODYLBL]]
 define <4 x double> @fmaddpd_loop(i32 %iter, <4 x double> %a, <4 x double> %b, <4 x double> %c) {
 entry:
   br label %for.cond
 
 for.cond:
   %c.addr.0 = phi <4 x double> [ %c, %entry ], [ %0, %for.inc ]

 for.end:
   ret <4 x double> %c.addr.0
 }
 
 ; CHECK-LABEL: fmsubpd_loop
 ; CHECK: [[BODYLBL:LBB.+]]:
 ; CHECK:   vfmsub231pd        %ymm{{[0-9]+}}, %ymm{{[0-9]+}}, %ymm{{[0-9]+}}
 ; CHECK: [[INCLBL:LBB.+]]:
-; CHECK:   incl  [[INDREG:%[a-z0-9]+]]
+; CHECK:   addl  $1, [[INDREG:%[a-z0-9]+]]
 ; CHECK:   cmpl  {{%.+}}, [[INDREG]]
 ; CHECK:   jl    [[BODYLBL]]
 define <4 x double> @fmsubpd_loop(i32 %iter, <4 x double> %a, <4 x double> %b, <4 x double> %c) {
 entry:
   br label %for.cond
 
 for.cond:
   %c.addr.0 = phi <4 x double> [ %c, %entry ], [ %0, %for.inc ]

 declare <4 x double> @llvm.x86.fma.vfmadd.pd.256(<4 x double>, <4 x double>, <4 x double>)
 declare <4 x double> @llvm.x86.fma.vfmsub.pd.256(<4 x double>, <4 x double>, <4 x double>)
 
 
 ; CHECK-LABEL: fmaddsubps_loop
 ; CHECK: [[BODYLBL:LBB.+]]:
 ; CHECK:   vfmaddsub231ps        %ymm{{[0-9]+}}, %ymm{{[0-9]+}}, %ymm{{[0-9]+}}
 ; CHECK: [[INCLBL:LBB.+]]:
-; CHECK:   incl  [[INDREG:%[a-z0-9]+]]
+; CHECK:   addl  $1, [[INDREG:%[a-z0-9]+]]
 ; CHECK:   cmpl  {{%.+}}, [[INDREG]]
 ; CHECK:   jl    [[BODYLBL]]
 define <8 x float> @fmaddsubps_loop(i32 %iter, <8 x float> %a, <8 x float> %b, <8 x float> %c) {
 entry:
   br label %for.cond
 
 for.cond:
   %c.addr.0 = phi <8 x float> [ %c, %entry ], [ %0, %for.inc ]

 for.end:
   ret <8 x float> %c.addr.0
 }
 
 ; CHECK-LABEL: fmsubaddps_loop
 ; CHECK: [[BODYLBL:LBB.+]]:
 ; CHECK:   vfmsubadd231ps        %ymm{{[0-9]+}}, %ymm{{[0-9]+}}, %ymm{{[0-9]+}}
 ; CHECK: [[INCLBL:LBB.+]]:
-; CHECK:   incl  [[INDREG:%[a-z0-9]+]]
+; CHECK:   addl  $1, [[INDREG:%[a-z0-9]+]]
 ; CHECK:   cmpl  {{%.+}}, [[INDREG]]
 ; CHECK:   jl    [[BODYLBL]]
 define <8 x float> @fmsubaddps_loop(i32 %iter, <8 x float> %a, <8 x float> %b, <8 x float> %c) {
 entry:
   br label %for.cond
 
 for.cond:
   %c.addr.0 = phi <8 x float> [ %c, %entry ], [ %0, %for.inc ]

 for.end:
   ret <8 x float> %c.addr.0
 }
 
 ; CHECK-LABEL: fmaddps_loop
 ; CHECK: [[BODYLBL:LBB.+]]:
 ; CHECK:   vfmadd231ps        %ymm{{[0-9]+}}, %ymm{{[0-9]+}}, %ymm{{[0-9]+}}
 ; CHECK: [[INCLBL:LBB.+]]:
-; CHECK:   incl  [[INDREG:%[a-z0-9]+]]
+; CHECK:   addl  $1, [[INDREG:%[a-z0-9]+]]
 ; CHECK:   cmpl  {{%.+}}, [[INDREG]]
 ; CHECK:   jl    [[BODYLBL]]
 define <8 x float> @fmaddps_loop(i32 %iter, <8 x float> %a, <8 x float> %b, <8 x float> %c) {
 entry:
   br label %for.cond
 
 for.cond:
   %c.addr.0 = phi <8 x float> [ %c, %entry ], [ %0, %for.inc ]

 for.end:
   ret <8 x float> %c.addr.0
 }
 
 ; CHECK-LABEL: fmsubps_loop
 ; CHECK: [[BODYLBL:LBB.+]]:
 ; CHECK:   vfmsub231ps        %ymm{{[0-9]+}}, %ymm{{[0-9]+}}, %ymm{{[0-9]+}}
 ; CHECK: [[INCLBL:LBB.+]]:
-; CHECK:   incl  [[INDREG:%[a-z0-9]+]]
+; CHECK:   addl  $1, [[INDREG:%[a-z0-9]+]]
 ; CHECK:   cmpl  {{%.+}}, [[INDREG]]
 ; CHECK:   jl    [[BODYLBL]]
 define <8 x float> @fmsubps_loop(i32 %iter, <8 x float> %a, <8 x float> %b, <8 x float> %c) {
 entry:
   br label %for.cond
 
 for.cond:
   %c.addr.0 = phi <8 x float> [ %c, %entry ], [ %0, %for.inc ]

llvm/trunk/test/CodeGen/X86/slow-incdec.ll

+; RUN: llc -mtriple=i386-unknown-linux-gnu -mattr=-slow-incdec < %s | FileCheck -check-prefix=INCDEC %s
+; RUN: llc -mtriple=i386-unknown-linux-gnu -mattr=+slow-incdec < %s | FileCheck -check-prefix=ADD %s
+
+; check -mattr=-slow-incdec
+; INCDEC-NOT: addl $-1
+; INCDEC: dec
+; INCDEC-NOT: addl $1
+; INCDEC: inc
+
+; check -mattr=+slow-incdec
+; ADD: addl $-1
+; ADD-NOT: dec
+; ADD: addl $1
+; ADD-NOT: inc
+
+; Function Attrs: nounwind readonly
+define i32 @slow_1(i32* nocapture readonly %a, i32 %s) #0 {
+entry:
+  %cmp5 = icmp eq i32 %s, 0
+  br i1 %cmp5, label %for.end, label %for.body.preheader
+
+for.body.preheader:                               ; preds = %entry
+  br label %for.body
+
+for.cond:                                         ; preds = %for.body
+  %cmp = icmp eq i32 %dec, 0
+  br i1 %cmp, label %for.end.loopexit, label %for.body
+
+for.body:                                         ; preds = %for.body.preheader, %for.cond
+  %i.06 = phi i32 [ %dec, %for.cond ], [ %s, %for.body.preheader ]
+  %arrayidx = getelementptr inbounds i32* %a, i32 %i.06
+  %0 = load i32* %arrayidx, align 4, !tbaa !1
+  %cmp1 = icmp eq i32 %0, 0
+;
+  %dec = add nsw i32 %i.06, -1
+  br i1 %cmp1, label %for.end.loopexit, label %for.cond
+
+for.end.loopexit:                                 ; preds = %for.cond, %for.body
+  %i.0.lcssa.ph = phi i32 [ 0, %for.cond ], [ %i.06, %for.body ]
+  br label %for.end
+
+for.end:                                          ; preds = %for.end.loopexit, %entry
+  %i.0.lcssa = phi i32 [ 0, %entry ], [ %i.0.lcssa.ph, %for.end.loopexit ]
+  ret i32 %i.0.lcssa
+}
+
+; Function Attrs: nounwind readonly
+define i32 @slow_2(i32* nocapture readonly %a, i32 %s) #0 {
+entry:
+  %cmp5 = icmp eq i32 %s, 0
+  br i1 %cmp5, label %for.end, label %for.body.preheader
+
+for.body.preheader:                               ; preds = %entry
+  br label %for.body
+
+for.cond:                                         ; preds = %for.body
+  %cmp = icmp eq i32 %inc, 0
+  br i1 %cmp, label %for.end.loopexit, label %for.body
+
+for.body:                                         ; preds = %for.body.preheader, %for.cond
+  %i.06 = phi i32 [ %inc, %for.cond ], [ %s, %for.body.preheader ]
+  %arrayidx = getelementptr inbounds i32* %a, i32 %i.06
+  %0 = load i32* %arrayidx, align 4, !tbaa !1
+  %cmp1 = icmp eq i32 %0, 0
+  %inc = add nsw i32 %i.06, 1
+  br i1 %cmp1, label %for.end.loopexit, label %for.cond
+
+for.end.loopexit:                                 ; preds = %for.cond, %for.body
+  %i.0.lcssa.ph = phi i32 [ 0, %for.cond ], [ %i.06, %for.body ]
+  br label %for.end
+
+for.end:                                          ; preds = %for.end.loopexit, %entry
+  %i.0.lcssa = phi i32 [ 0, %entry ], [ %i.0.lcssa.ph, %for.end.loopexit ]
+  ret i32 %i.0.lcssa
+}
+
+!1 = metadata !{metadata !2, metadata !2, i64 0}
+!2 = metadata !{metadata !"int", metadata !3, i64 0}
+!3 = metadata !{metadata !"omnipotent char", metadata !4, i64 0}
+!4 = metadata !{metadata !"Simple C/C++ TBAA"}