[Thumb2] RFE, SRS and "SUBS pc, lr" are undefined on v7M

[olista01]

Summary

These instructions are related to the v7[AR] exception model, and are not defined on v7M.

[olista01]

Committed as r220204.

For the record, this was approved by James Molloy, the email reached the mailing list but not phabricator.

lib/Target/ARM/ARMInstrThumb2.td

 }
 
 def t2DCPS1 : T2DCPS<0b01, "dcps1">;
 def t2DCPS2 : T2DCPS<0b10, "dcps2">;
 def t2DCPS3 : T2DCPS<0b11, "dcps3">;
 
 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
             string opc, string asm, list<dag> pattern>
-  : T2I<oops, iops, itin, opc, asm, pattern> {
+  : T2I<oops, iops, itin, opc, asm, pattern>,
+    Requires<[IsThumb2,IsNotMClass]> {
   bits<5> mode;
   let Inst{31-25} = 0b1110100;
   let Inst{24-23} = Op;
   let Inst{22} = 0;
   let Inst{21} = W;
   let Inst{20-16} = 0b01101;
   let Inst{15-5} = 0b11000000000;
   let Inst{4-0} = mode{4-0};

 def : t2InstAlias<"srsdb${p} $mode!", (t2SRSDB_UPD imm0_31:$mode, pred:$p)>;
 
 def : t2InstAlias<"srsia${p} $mode", (t2SRSIA imm0_31:$mode, pred:$p)>;
 def : t2InstAlias<"srsia${p} $mode!", (t2SRSIA_UPD imm0_31:$mode, pred:$p)>;
 
 // Return From Exception is a system instruction.
 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
           string opc, string asm, list<dag> pattern>
-  : T2I<oops, iops, itin, opc, asm, pattern> {
+  : T2I<oops, iops, itin, opc, asm, pattern>,
+    Requires<[IsThumb2,IsNotMClass]> {
   let Inst{31-20} = op31_20{11-0};
 
   bits<4> Rn;
   let Inst{19-16} = Rn;
   let Inst{15-0} = 0xc000;
 }
 
 def t2RFEDBW : T2RFE<0b111010000011,
def t2RFEIA  : T2RFE<0b111010011001,
                    [/* For disassembly only; pattern left blank */]>;
 
 // B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.
 // Exception return instruction is "subs pc, lr, #imm".
 let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
 def t2SUBS_PC_LR : T2I <(outs), (ins imm0_255:$imm), NoItinerary,
                         "subs", "\tpc, lr, $imm",
                         [(ARMintretflag imm0_255:$imm)]>,
-                   Requires<[IsThumb2]> {
+                   Requires<[IsThumb2,IsNotMClass]> {
   let Inst{31-8} = 0b111100111101111010001111;
 
   bits<8> imm;
   let Inst{7-0} = imm;
 }
 
 //===----------------------------------------------------------------------===//
 // Non-Instruction Patterns

test/MC/ARM/thumb2-exception-return-mclass.s

+# RUN: not llvm-mc -triple thumbv7m -assemble < %s 2>&1 | FileCheck %s
+
+  .text
+
+# CHECK: instruction requires: !armv*m
+# CHECK-NEXT: srsdb sp, #7
+  srsdb sp, #7
+
+# CHECK: instruction requires: !armv*m
+# CHECK-NEXT: rfeia r6
+  rfeia r6
+
+# CHECK: instruction requires: !armv*m
+# CHECK-NEXT: subs pc, lr, #42
+  subs pc, lr, #42