Fix float division-by-zero in R600 scheduler

[samsonov]

Summary

Fix a float division by zero reported by UBSan. It was reported
in the following test cases:

LLVM :: CodeGen/R600/and.ll
LLVM :: CodeGen/R600/fma.ll
LLVM :: CodeGen/R600/xor.ll

I'm not sure is actually an accepted value for ALUFetchRationEstimate,
or we should add an assert and fix a bug elsewhere. Please take a look.

[samsonov]

Submitted as r217967, thanks!

lib/Target/R600/R600MachineScheduler.cpp

SUnit* R600SchedStrategy::pickNode(bool &IsTopNode) {
   if (CurInstKind == IDAlu && !Available[IDFetch].empty()) {
     // We use the heuristic provided by AMD Accelerated Parallel Processing
     // OpenCL Programming Guide :
     // The approx. number of WF that allows TEX inst to hide ALU inst is :
     // 500 (cycles for TEX) / (AluFetchRatio * 8 (cycles for ALU))
     float ALUFetchRationEstimate =
         (AluInstCount + AvailablesAluCount() + Pending[IDAlu].size()) /
         (FetchInstCount + Available[IDFetch].size());
+    if (ALUFetchRationEstimate == 0) {
+      AllowSwitchFromAlu = true;
+    } else {
       unsigned NeededWF = 62.5f / ALUFetchRationEstimate;
       DEBUG( dbgs() << NeededWF << " approx. Wavefronts Required\n" );
       // We assume the local GPR requirements to be "dominated" by the requirement
       // of the TEX clause (which consumes 128 bits regs) ; ALU inst before and
       // after TEX are indeed likely to consume or generate values from/for the
       // TEX clause.
       // Available[IDFetch].size() * 2 : GPRs required in the Fetch clause
       // We assume that fetch instructions are either TnXYZW = TEX TnXYZW (need
       // one GPR) or TmXYZW = TnXYZW (need 2 GPR).
       // (TODO : use RegisterPressure)
       // If we are going too use too many GPR, we flush Fetch instruction to lower
       // register pressure on 128 bits regs.
       unsigned NearRegisterRequirement = 2 * Available[IDFetch].size();
       if (NeededWF > getWFCountLimitedByGPR(NearRegisterRequirement))
         AllowSwitchFromAlu = true;
     }
+  }
 
   if (!SU && ((AllowSwitchToAlu && CurInstKind != IDAlu) ||
       (!AllowSwitchFromAlu && CurInstKind == IDAlu))) {
     // try to pick ALU
     SU = pickAlu();
     if (!SU && !PhysicalRegCopy.empty()) {
       SU = PhysicalRegCopy.front();
       PhysicalRegCopy.erase(PhysicalRegCopy.begin());