Fix typos in comments and doc

[jfb]

Committed as https://llvm.org/svn/llvm-project/llvm/trunk@214934

docs/TableGen/index.rst

 
 TableGen Deficiencies
 =====================
 
 Despite being very generic, TableGen has some deficiencies that have been
 pointed out numerous times. The common theme is that, while TableGen allows
 you to build Domain-Specific-Languages, the final languages that you create
 lack the power of other DSLs, which in turn increase considerably the size
-and complecity of TableGen files.
+and complexity of TableGen files.
 
 At the same time, TableGen allows you to create virtually any meaning of
 the basic concepts via custom-made back-ends, which can pervert the original
 design and make it very hard for newcomers to understand the evil TableGen
 file.
 
 There are some in favour of extending the semantics even more, but making sure
 back-ends adhere to strict rules. Others are suggesting we should move to less,
 more powerful DSLs designed with specific purposes, or even re-using existing
 DSLs.
 
 Either way, this is a discussion that will likely span across several years,
 if not decades. You can read more in the `TableGen Deficiencies <Deficiencies.html>`_
 document.

lib/Target/X86/X86ISelLowering.cpp

void X86TargetLowering::ReplaceNodeResults(SDNode *N,
   case ISD::ATOMIC_LOAD_OR:
   case ISD::ATOMIC_LOAD_XOR:
   case ISD::ATOMIC_LOAD_NAND:
   case ISD::ATOMIC_LOAD_MIN:
   case ISD::ATOMIC_LOAD_MAX:
   case ISD::ATOMIC_LOAD_UMIN:
   case ISD::ATOMIC_LOAD_UMAX:
     // Delegate to generic TypeLegalization. Situations we can really handle
-    // should have already been dealt with by X86AtomicExpand.cpp.
+    // should have already been dealt with by X86AtomicExpandPass.cpp.
     break;
   case ISD::ATOMIC_LOAD: {
     ReplaceATOMIC_LOAD(N, Results, DAG);
     return;
   }
   case ISD::BITCAST: {
     assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
     EVT DstVT = N->getValueType(0);

lib/Target/X86/X86InstrInfo.cpp

void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   if (Opc) {
     BuildMI(MBB, MI, DL, get(Opc), DestReg)
       .addReg(SrcReg, getKillRegState(KillSrc));
     return;
   }
 
   // Moving EFLAGS to / from another register requires a push and a pop.
   // Notice that we have to adjust the stack if we don't want to clobber the
-  // first frame index. See X86FrameLowering.cpp - colobbersTheStack.
+  // first frame index. See X86FrameLowering.cpp - clobbersTheStack.
   if (SrcReg == X86::EFLAGS) {
     if (X86::GR64RegClass.contains(DestReg)) {
       BuildMI(MBB, MI, DL, get(X86::PUSHF64));
       BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
       return;
     }
     if (X86::GR32RegClass.contains(DestReg)) {
       BuildMI(MBB, MI, DL, get(X86::PUSHF32));

lib/Transforms/Scalar/GVN.cpp

bool GVN::processFoldableCondBr(BranchInst *BI) {
 
   if (!DeadRoot->getSinglePredecessor())
     DeadRoot = splitCriticalEdges(BI->getParent(), DeadRoot);
 
   addDeadBlock(DeadRoot);
   return true;
 }
 
-// performPRE() will trigger assert if it come across an instruciton without
+// performPRE() will trigger assert if it comes across an instruction without
 // associated val-num. As it normally has far more live instructions than dead
 // instructions, it makes more sense just to "fabricate" a val-number for the
 // dead code than checking if instruction involved is dead or not.
 void GVN::assignValNumForDeadCode() {
   for (SetVector<BasicBlock *>::iterator I = DeadBlocks.begin(),
         E = DeadBlocks.end(); I != E; I++) {
     BasicBlock *BB = *I;
     for (BasicBlock::iterator II = BB->begin(), EE = BB->end();
           II != EE; II++) {
       Instruction *Inst = &*II;
       unsigned ValNum = VN.lookup_or_add(Inst);
       addToLeaderTable(ValNum, Inst, BB);
     }
   }
 }

lib/Transforms/Scalar/LoopRotation.cpp

for (Value::use_iterator UI = OrigHeaderVal->use_begin(),
       }
 
       // Anything else can be handled by SSAUpdater.
       SSA.RewriteUse(U);
     }
   }
 }
 
-/// Determine whether the instructions in this range my be safely and cheaply
+/// Determine whether the instructions in this range may be safely and cheaply
 /// speculated. This is not an important enough situation to develop complex
 /// heuristics. We handle a single arithmetic instruction along with any type
 /// conversions.
 static bool shouldSpeculateInstrs(BasicBlock::iterator Begin,
                                   BasicBlock::iterator End) {
   bool seenIncrement = false;
   for (BasicBlock::iterator I = Begin; I != End; ++I) {
 
for (BasicBlock::iterator I = Begin; I != End; ++I) {
     }
   }
   return true;
 }
 
 /// Fold the loop tail into the loop exit by speculating the loop tail
 /// instructions. Typically, this is a single post-increment. In the case of a
 /// simple 2-block loop, hoisting the increment can be much better than
-/// duplicating the entire loop header. In the cast of loops with early exits,
+/// duplicating the entire loop header. In the case of loops with early exits,
 /// rotation will not work anyway, but simplifyLoopLatch will put the loop in
 /// canonical form so downstream passes can handle it.
 ///
 /// I don't believe this invalidates SCEV.
 bool LoopRotate::simplifyLoopLatch(Loop *L) {
   BasicBlock *Latch = L->getLoopLatch();
   if (!Latch || Latch->hasAddressTaken())
     return false;