Fix ll and sc instructions

[jyyou.tw]

Summary

The ll and sc instructions for r6 and non-r6 are misplaced. This patch fixes that.

[dsanders]

LGTM, Thanks.

[jyyou.tw]

Could someone merge this change? The problem still exists.

[dsanders]

Hi,

I'll commit this today. The reason it hasn't been committed yet is that the patch author is normally expected to commit their patches themselves unless they mention that they don't have commit access.

[jyyou.tw]

Got it. Thank you very much.

[dsanders]

Committed in r213847.

lib/Target/Mips/MipsISelLowering.cpp

MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
   DebugLoc DL = MI->getDebugLoc();
   unsigned LL, SC, AND, NOR, ZERO, BEQ;
 
   if (Size == 4) {
     if (isMicroMips) {
       LL = Mips::LL_MM;
       SC = Mips::SC_MM;
     } else {
-      LL = Subtarget->hasMips32r6() ? Mips::LL : Mips::LL_R6;
-      SC = Subtarget->hasMips32r6() ? Mips::SC : Mips::SC_R6;
+      LL = Subtarget->hasMips32r6() ? Mips::LL_R6 : Mips::LL;
+      SC = Subtarget->hasMips32r6() ? Mips::SC_R6 : Mips::SC;
     }
     AND = Mips::AND;
     NOR = Mips::NOR;
     ZERO = Mips::ZERO;
     BEQ = Mips::BEQ;
   } else {
-    LL = Subtarget->hasMips64r6() ? Mips::LLD : Mips::LLD_R6;
-    SC = Subtarget->hasMips64r6() ? Mips::SCD : Mips::SCD_R6;
+    LL = Subtarget->hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
+    SC = Subtarget->hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
     AND = Mips::AND64;
     NOR = Mips::NOR64;
     ZERO = Mips::ZERO_64;
     BEQ = Mips::BEQ64;
   }
 
   unsigned OldVal = MI->getOperand(0).getReg();
   unsigned Ptr = MI->getOperand(1).getReg();