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[mips] .reginfo is 8 byte aligned on N32.
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Authored by dsanders on Jul 16 2014, 7:43 AM.

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Reviewers

sstankovic
dsanders
vmedic

Commits

rG701e961650c5: [mips] .reginfo is 8 byte aligned on N32.
rL213246: [mips] .reginfo is 8 byte aligned on N32.

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Repository: rL LLVM

Event Timeline

dsanders updated this revision to Diff 11515.Jul 16 2014, 7:43 AM

dsanders retitled this revision from to [mips] .reginfo is 8 byte aligned on N32..

dsanders updated this object.

dsanders edited the test plan for this revision. (Show Details)

dsanders added reviewers: sstankovic, vmedic.

LGTM

dsanders accepted this revision.Jul 17 2014, 3:11 AM

dsanders added a reviewer: dsanders.

This revision is now accepted and ready to land.Jul 17 2014, 3:11 AM

dsanders closed this revision.Jul 17 2014, 3:18 AM

Closed by commit rL213246 (authored by @dsanders).

Revision Contents

Path

Size

llvm/

trunk/

lib/

Target/

Mips/

MCTargetDesc/

MipsTargetStreamer.cpp

3 lines

test/

MC/

Mips/

elf_reginfo.s

2 lines

Diff 11563

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp

Show First 20 Lines • Show All 360 Lines • ▼ Show 20 Lines	if (T.isArch64Bit() && (Features & Mips::FeatureN64)) {
OS.EmitIntValue(0, 4); // ri_cpr[1]mask		OS.EmitIntValue(0, 4); // ri_cpr[1]mask
OS.EmitIntValue(0, 4); // ri_cpr[2]mask		OS.EmitIntValue(0, 4); // ri_cpr[2]mask
OS.EmitIntValue(0, 4); // ri_cpr[3]mask		OS.EmitIntValue(0, 4); // ri_cpr[3]mask
OS.EmitIntValue(0, 8); // ri_gp_value		OS.EmitIntValue(0, 8); // ri_gp_value
} else {		} else {
const MCSectionELF *Sec =		const MCSectionELF *Sec =
Context.getELFSection(".reginfo", ELF::SHT_MIPS_REGINFO, ELF::SHF_ALLOC,		Context.getELFSection(".reginfo", ELF::SHT_MIPS_REGINFO, ELF::SHF_ALLOC,
SectionKind::getMetadata(), 24, "");		SectionKind::getMetadata(), 24, "");
MCA.getOrCreateSectionData(*Sec).setAlignment(4);		MCA.getOrCreateSectionData(*Sec)
		.setAlignment(Features & Mips::FeatureN32 ? 8 : 4);
OS.SwitchSection(Sec);		OS.SwitchSection(Sec);

OS.EmitIntValue(0, 4); // ri_gprmask		OS.EmitIntValue(0, 4); // ri_gprmask
OS.EmitIntValue(0, 4); // ri_cpr[0]mask		OS.EmitIntValue(0, 4); // ri_cpr[0]mask
OS.EmitIntValue(0, 4); // ri_cpr[1]mask		OS.EmitIntValue(0, 4); // ri_cpr[1]mask
OS.EmitIntValue(0, 4); // ri_cpr[2]mask		OS.EmitIntValue(0, 4); // ri_cpr[2]mask
OS.EmitIntValue(0, 4); // ri_cpr[3]mask		OS.EmitIntValue(0, 4); // ri_cpr[3]mask
OS.EmitIntValue(0, 4); // ri_gp_value		OS.EmitIntValue(0, 4); // ri_gp_value
▲ Show 20 Lines • Show All 297 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/elf_reginfo.s

	Show All 21 Lines
	# CHECK_64-LABEL: }			# CHECK_64-LABEL: }

	# check for .reginfo			# check for .reginfo
	# CHECK_32: Sections [			# CHECK_32: Sections [
	# CHECK_32: Section {			# CHECK_32: Section {
	# CHECK_32-LABEL: Name: .reginfo			# CHECK_32-LABEL: Name: .reginfo
	# CHECK_32-NEXT: Type: SHT_MIPS_REGINFO			# CHECK_32-NEXT: Type: SHT_MIPS_REGINFO
	# CHECK_32-NEXT: Flags [ (0x2)			# CHECK_32-NEXT: Flags [ (0x2)
	# CHECK_32: AddressAlignment: 4			# CHECK_32: AddressAlignment: 8
	# CHECK_32: EntrySize: 24			# CHECK_32: EntrySize: 24
	# CHECK_32-LABEL: }			# CHECK_32-LABEL: }