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Differential D44845

[PostRAMachineSink] preserve CFG
ClosedPublic

Authored by junbuml on Mar 23 2018, 1:39 PM.

Details

Reviewers
sebpop
mzolotukhin
mcrosier
Commits
rGf90fe701efbb: [PostRAMachineSink] preserve CFG
rL328727: [PostRAMachineSink] preserve CFG
Summary

Mark CFG is preserved since this pass do not make any change in CFG.

Diff Detail

Repository
rL LLVM

Event Timeline

junbuml created this revision.Mar 23 2018, 1:39 PM
mzolotukhin accepted this revision.Mar 23 2018, 1:54 PM

LGTM!

This revision is now accepted and ready to land.Mar 23 2018, 1:54 PM
Closed by commit rL328727: [PostRAMachineSink] preserve CFG (authored by junbuml). · Explain WhyMar 28 2018, 12:59 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
CodeGen/
5 lines
test/
CodeGen/
X86/
2 lines

Diff 140126

llvm/trunk/lib/CodeGen/MachineSink.cpp

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class PostRAMachineSinking : public MachineFunctionPass { class PostRAMachineSinking : public MachineFunctionPass {
public: public:
bool runOnMachineFunction(MachineFunction &MF) override; bool runOnMachineFunction(MachineFunction &MF) override;
static char ID; static char ID;
PostRAMachineSinking() : MachineFunctionPass(ID) {} PostRAMachineSinking() : MachineFunctionPass(ID) {}
StringRef getPassName() const override { return "PostRA Machine Sink"; } StringRef getPassName() const override { return "PostRA Machine Sink"; }
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG();
MachineFunctionPass::getAnalysisUsage(AU);
}
private: private:
/// Track which registers have been modified and used. /// Track which registers have been modified and used.
BitVector ModifiedRegs, UsedRegs; BitVector ModifiedRegs, UsedRegs;
/// Sink Copy instructions unused in the same block close to their uses in /// Sink Copy instructions unused in the same block close to their uses in
/// successors. /// successors.
bool tryToSinkCopy(MachineBasicBlock &BB, MachineFunction &MF, bool tryToSinkCopy(MachineBasicBlock &BB, MachineFunction &MF,
const TargetRegisterInfo *TRI, const TargetInstrInfo *TII); const TargetRegisterInfo *TRI, const TargetInstrInfo *TII);
▲ Show 20 Lines • Show All 134 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/O3-pipeline.ll

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; CHECK-NEXT: Greedy Register Allocator ; CHECK-NEXT: Greedy Register Allocator
; CHECK-NEXT: Virtual Register Rewriter ; CHECK-NEXT: Virtual Register Rewriter
; CHECK-NEXT: Stack Slot Coloring ; CHECK-NEXT: Stack Slot Coloring
; CHECK-NEXT: Machine Copy Propagation Pass ; CHECK-NEXT: Machine Copy Propagation Pass
; CHECK-NEXT: Machine Loop Invariant Code Motion ; CHECK-NEXT: Machine Loop Invariant Code Motion
; CHECK-NEXT: Bundle Machine CFG Edges ; CHECK-NEXT: Bundle Machine CFG Edges
; CHECK-NEXT: X86 FP Stackifier ; CHECK-NEXT: X86 FP Stackifier
; CHECK-NEXT: PostRA Machine Sink ; CHECK-NEXT: PostRA Machine Sink
; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: Machine Natural Loop Construction
; CHECK-NEXT: Machine Block Frequency Analysis ; CHECK-NEXT: Machine Block Frequency Analysis
; CHECK-NEXT: MachinePostDominator Tree Construction ; CHECK-NEXT: MachinePostDominator Tree Construction
; CHECK-NEXT: Shrink Wrapping analysis ; CHECK-NEXT: Shrink Wrapping analysis
; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter ; CHECK-NEXT: Machine Optimization Remark Emitter
; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization ; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization
; CHECK-NEXT: Control Flow Optimizer ; CHECK-NEXT: Control Flow Optimizer
; CHECK-NEXT: Tail Duplication ; CHECK-NEXT: Tail Duplication
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