[mips][mips64r6] Correct select patterns that have the condition or true/false values backwards

[dsanders]

Summary

This bug caused SingleSource/Regression/C/uint64_to_float and SingleSource/UnitTests/2002-05-02-CastTest3 to fail (among others).

[zoran.jovanovic]

LGTM

lib/Target/Mips/Mips32r6InstrInfo.td

 def : MipsPat<(setne f64:$lhs, f64:$rhs),
               (NOR (CMP_EQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
 
 // i32 selects
 def : MipsPat<(select i32:$cond, i32:$t, i32:$f),
               (OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>,
               ISA_MIPS32R6;
 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i32:$t, i32:$f),
-              (OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>,
+              (OR (SELEQZ i32:$t, i32:$cond), (SELNEZ i32:$f, i32:$cond))>,
               ISA_MIPS32R6;
 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i32:$t, i32:$f),
-              (OR (SELNEZ i32:$f, i32:$cond), (SELEQZ i32:$t, i32:$cond))>,
+              (OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>,
               ISA_MIPS32R6;
 def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
-              (OR (SELNEZ i32:$t, (XORi i32:$cond, immZExt16:$imm)),
-                  (SELEQZ i32:$f, (XORi i32:$cond, immZExt16:$imm)))>,
+              (OR (SELEQZ i32:$t, (XORi i32:$cond, immZExt16:$imm)),
+                  (SELNEZ i32:$f, (XORi i32:$cond, immZExt16:$imm)))>,
               ISA_MIPS32R6;
 def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
               (OR (SELNEZ i32:$f, (XORi i32:$cond, immZExt16:$imm)),
                   (SELEQZ i32:$t, (XORi i32:$cond, immZExt16:$imm)))>,
               ISA_MIPS32R6;
 def : MipsPat<(select (i32 (setgt i32:$cond, immSExt16Plus1:$imm)), i32:$t,
                       i32:$f),
-              (OR (SELNEZ i32:$t, (SLTi i32:$cond, (Plus1 imm:$imm))),
-                  (SELEQZ i32:$f, (SLTi i32:$cond, (Plus1 imm:$imm))))>,
+              (OR (SELEQZ i32:$t, (SLTi i32:$cond, (Plus1 imm:$imm))),
+                  (SELNEZ i32:$f, (SLTi i32:$cond, (Plus1 imm:$imm))))>,
               ISA_MIPS32R6;
 def : MipsPat<(select (i32 (setugt i32:$cond, immSExt16Plus1:$imm)),
                       i32:$t, i32:$f),
-              (OR (SELNEZ i32:$t, (SLTiu i32:$cond, (Plus1 imm:$imm))),
-                  (SELEQZ i32:$f, (SLTiu i32:$cond, (Plus1 imm:$imm))))>,
+              (OR (SELEQZ i32:$t, (SLTiu i32:$cond, (Plus1 imm:$imm))),
+                  (SELNEZ i32:$f, (SLTiu i32:$cond, (Plus1 imm:$imm))))>,
               ISA_MIPS32R6;
 
 def : MipsPat<(select i32:$cond, i32:$t, immz),
               (SELNEZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i32:$t, immz),
               (SELNEZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i32:$t, immz),
               (SELEQZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
 def : MipsPat<(select i32:$cond, immz, i32:$f),
               (SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6;
 def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i32:$f),
               (SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6;
 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i32:$f),
               (SELNEZ i32:$f, i32:$cond)>, ISA_MIPS32R6;

lib/Target/Mips/Mips64r6InstrInfo.td

 //===----------------------------------------------------------------------===//
 
 // i64 selects
 def : MipsPat<(select i64:$cond, i64:$t, i64:$f),
               (OR64 (SELNEZ64 i64:$t, i64:$cond),
                     (SELEQZ64 i64:$f, i64:$cond))>,
               ISA_MIPS64R6;
 def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, i64:$f),
-              (OR64 (SELNEZ64 i64:$t, i64:$cond),
-                    (SELEQZ64 i64:$f, i64:$cond))>,
+              (OR64 (SELEQZ64 i64:$t, i64:$cond),
+                    (SELNEZ64 i64:$f, i64:$cond))>,
               ISA_MIPS64R6;
 def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, i64:$f),
-              (OR64 (SELNEZ64 i64:$f, i64:$cond),
-                    (SELEQZ64 i64:$t, i64:$cond))>,
+              (OR64 (SELNEZ64 i64:$t, i64:$cond),
+                    (SELEQZ64 i64:$f, i64:$cond))>,
               ISA_MIPS64R6;
 def : MipsPat<(select (i32 (seteq i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
-              (OR64 (SELNEZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
-                    (SELEQZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
+              (OR64 (SELEQZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
+                    (SELNEZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
               ISA_MIPS64R6;
 def : MipsPat<(select (i32 (setne i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
-              (OR64 (SELNEZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)),
-                    (SELEQZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
+              (OR64 (SELNEZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
+                    (SELEQZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
               ISA_MIPS64R6;
 def : MipsPat<
   (select (i32 (setgt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
-  (OR64 (SELNEZ64 i64:$t,
+  (OR64 (SELEQZ64 i64:$t,
                   (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
                                  sub_32)),
-        (SELEQZ64 i64:$f,
+        (SELNEZ64 i64:$f,
                   (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
                                  sub_32)))>,
   ISA_MIPS64R6;
 def : MipsPat<
   (select (i32 (setugt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
-  (OR64 (SELNEZ64 i64:$t,
+  (OR64 (SELEQZ64 i64:$t,
                   (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
                                  sub_32)),
-        (SELEQZ64 i64:$f,
+        (SELNEZ64 i64:$f,
                   (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
                                  sub_32)))>,
   ISA_MIPS64R6;
 
 def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, immz),
               (SELNEZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
 def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, immz),
               (SELEQZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
 def : MipsPat<(select (i32 (setne i64:$cond, immz)), immz, i64:$f),
               (SELEQZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
 def : MipsPat<(select (i32 (seteq i64:$cond, immz)), immz, i64:$f),
               (SELNEZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
 
 // i64 selects from an i32 comparison
 // One complicating factor here is that bits 32-63 of an i32 are undefined.
 // FIXME: Ideally, setcc would always produce an i64 on MIPS64 targets.
 //        This would allow us to remove the sign-extensions here.
 def : MipsPat<(select i32:$cond, i64:$t, i64:$f),
               (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
                     (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
               ISA_MIPS64R6;
 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, i64:$f),
-              (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
-                    (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
+              (OR64 (SELEQZ64 i64:$t, (SLL64_32 i32:$cond)),
+                    (SELNEZ64 i64:$f, (SLL64_32 i32:$cond)))>,
               ISA_MIPS64R6;
 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, i64:$f),
-              (OR64 (SELNEZ64 i64:$f, (SLL64_32 i32:$cond)),
-                    (SELEQZ64 i64:$t, (SLL64_32 i32:$cond)))>,
+              (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
+                    (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
               ISA_MIPS64R6;
 def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
-              (OR64 (SELNEZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
+              (OR64 (SELEQZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
                                                       immZExt16:$imm))),
-                    (SELEQZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
+                    (SELNEZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
                                                       immZExt16:$imm))))>,
               ISA_MIPS64R6;
 def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
               (OR64 (SELNEZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
                                                       immZExt16:$imm))),
                     (SELEQZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
                                                       immZExt16:$imm))))>,
               ISA_MIPS64R6;

test/CodeGen/Mips/cmov.ll

 
 ; 32-CMOV-DAG:  lw $[[R0:[0-9]+]], %got(i3)
 ; 32-CMOV-DAG:  addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(i1)
 ; 32-CMOV-DAG:  movn $[[R0]], $[[R1]], $4
 ; 32-CMOV-DAG:  lw $2, 0($[[R0]])
 
 ; 32-CMP-DAG:   lw $[[R0:[0-9]+]], %got(i3)
 ; 32-CMP-DAG:   addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(i1)
-; 32-CMP-DAG:   seleqz $[[T0:[0-9]+]], $[[R1]], $4
-; 32-CMP-DAG:   selnez $[[T1:[0-9]+]], $[[R0]], $4
-; 32-CMP-DAG:   or $[[T2:[0-9]+]], $[[T1]], $[[T0]]
+; 32-CMP-DAG:   selnez $[[T0:[0-9]+]], $[[R1]], $4
+; 32-CMP-DAG:   seleqz $[[T1:[0-9]+]], $[[R0]], $4
+; 32-CMP-DAG:   or $[[T2:[0-9]+]], $[[T0]], $[[T1]]
 ; 32-CMP-DAG:   lw $2, 0($[[T2]])
 
 ; 64-CMOV-DAG:  ldr $[[R0:[0-9]+]]
 ; 64-CMOV-DAG:  ld $[[R1:[0-9]+]], %got_disp(i1)
 ; 64-CMOV-DAG:  movn $[[R0]], $[[R1]], $4
 
 ; 64-CMP-DAG:   ld $[[R0:[0-9]+]], %got_disp(i3)(
 ; 64-CMP-DAG:   daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(i1)
 ; FIXME: This sll works around an implementation detail in the code generator
 ;        (setcc's result is i32 so bits 32-63 are undefined). It's not really
 ;        needed.
 ; 64-CMP-DAG:   sll $[[CC:[0-9]+]], $4, 0
-; 64-CMP-DAG:   seleqz $[[T0:[0-9]+]], $[[R1]], $[[CC]]
-; 64-CMP-DAG:   selnez $[[T1:[0-9]+]], $[[R0]], $[[CC]]
-; 64-CMP-DAG:   or $[[T2:[0-9]+]], $[[T1]], $[[T0]]
+; 64-CMP-DAG:   selnez $[[T0:[0-9]+]], $[[R1]], $[[CC]]
+; 64-CMP-DAG:   seleqz $[[T1:[0-9]+]], $[[R0]], $[[CC]]
+; 64-CMP-DAG:   or $[[T2:[0-9]+]], $[[T0]], $[[T1]]
 ; 64-CMP-DAG:   ld $2, 0($[[T2]])
 
 define i32* @cmov1(i32 %s) nounwind readonly {
 entry:
   %tobool = icmp ne i32 %s, 0
   %tmp1 = load i32** @i3, align 4
   %cond = select i1 %tobool, i32* getelementptr inbounds ([3 x i32]* @i1, i32 0, i32 0), i32* %tmp1
   ret i32* %cond
 }
 
 @c = global i32 1, align 4
 @d = global i32 0, align 4
 
 ; ALL-LABEL: cmov2:
 
 ; 32-CMOV-DAG:  addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(d)
 ; 32-CMOV-DAG:  addiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got(c)
 ; 32-CMOV-DAG:  movn  $[[R1]], $[[R0]], $4
 ; 32-CMOV-DAG:  lw $2, 0($[[R0]])
 
 ; 32-CMP-DAG:   addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(d)
 ; 32-CMP-DAG:   addiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got(c)
-; 32-CMP-DAG:   seleqz $[[T0:[0-9]+]], $[[R0]], $4
-; 32-CMP-DAG:   selnez $[[T1:[0-9]+]], $[[R1]], $4
-; 32-CMP-DAG:   or $[[T2:[0-9]+]], $[[T1]], $[[T0]]
+; 32-CMP-DAG:   selnez $[[T0:[0-9]+]], $[[R0]], $4
+; 32-CMP-DAG:   seleqz $[[T1:[0-9]+]], $[[R1]], $4
+; 32-CMP-DAG:   or $[[T2:[0-9]+]], $[[T0]], $[[T1]]
 ; 32-CMP-DAG:   lw $2, 0($[[T2]])
 
 ; 64-CMOV:      daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(d)
 ; 64-CMOV:      daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got_disp(c)
 ; 64-CMOV:      movn  $[[R1]], $[[R0]], $4
 
 ; 64-CMP-DAG:   daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(d)
 ; 64-CMP-DAG:   daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got_disp(c)
 ; FIXME: This sll works around an implementation detail in the code generator
 ;        (setcc's result is i32 so bits 32-63 are undefined). It's not really
 ;        needed.
 ; 64-CMP-DAG:   sll $[[CC:[0-9]+]], $4, 0
-; 64-CMP-DAG:   seleqz $[[T0:[0-9]+]], $[[R0]], $[[CC]]
-; 64-CMP-DAG:   selnez $[[T1:[0-9]+]], $[[R1]], $[[CC]]
-; 64-CMP-DAG:   or $[[T2:[0-9]+]], $[[T1]], $[[T0]]
+; 64-CMP-DAG:   selnez $[[T0:[0-9]+]], $[[R0]], $[[CC]]
+; 64-CMP-DAG:   seleqz $[[T1:[0-9]+]], $[[R1]], $[[CC]]
+; 64-CMP-DAG:   or $[[T2:[0-9]+]], $[[T0]], $[[T1]]
 ; 64-CMP-DAG:   lw $2, 0($[[T2]])
 
 define i32 @cmov2(i32 %s) nounwind readonly {
 entry:
   %tobool = icmp ne i32 %s, 0
   %tmp1 = load i32* @c, align 4
   %tmp2 = load i32* @d, align 4
   %cond = select i1 %tobool, i32 %tmp1, i32 %tmp2
   ret i32 %cond
 }
 
 ; ALL-LABEL: cmov3:
 
 ; We won't check the result register since we can't know if the move is first
 ; or last. We do know it will be either one of two registers so we can at least
 ; check that.
 
 ; 32-CMOV:      xori $[[R0:[0-9]+]], $4, 234
 ; 32-CMOV:      movz ${{[26]}}, $5, $[[R0]]
 
 ; 32-CMP-DAG:   xori $[[CC:[0-9]+]], $4, 234
-; 32-CMP-DAG:   selnez $[[T0:[0-9]+]], $5, $[[CC]]
-; 32-CMP-DAG:   seleqz $[[T1:[0-9]+]], $6, $[[CC]]
+; 32-CMP-DAG:   seleqz $[[T0:[0-9]+]], $5, $[[CC]]
+; 32-CMP-DAG:   selnez $[[T1:[0-9]+]], $6, $[[CC]]
 ; 32-CMP-DAG:   or $2, $[[T0]], $[[T1]]
 
 ; 64-CMOV:      xori $[[R0:[0-9]+]], $4, 234
 ; 64-CMOV:      movz ${{[26]}}, $5, $[[R0]]
 
 ; 64-CMP-DAG:   xori $[[CC:[0-9]+]], $4, 234
-; 64-CMP-DAG:   selnez $[[T0:[0-9]+]], $5, $[[CC]]
-; 64-CMP-DAG:   seleqz $[[T1:[0-9]+]], $6, $[[CC]]
+; 64-CMP-DAG:   seleqz $[[T0:[0-9]+]], $5, $[[CC]]
+; 64-CMP-DAG:   selnez $[[T1:[0-9]+]], $6, $[[CC]]
 ; 64-CMP-DAG:   or $2, $[[T0]], $[[T1]]
 
 define i32 @cmov3(i32 %a, i32 %b, i32 %c) nounwind readnone {
 entry:
   %cmp = icmp eq i32 %a, 234
   %cond = select i1 %cmp, i32 %b, i32 %c
   ret i32 %cond
 }
 
 ; ALL-LABEL: cmov4:
 
 ; We won't check the result register since we can't know if the move is first
 ; or last. We do know it will be one of two registers so we can at least check
 ; that.
 
 ; 32-CMOV-DAG: xori $[[R0:[0-9]+]], $4, 234
 ; 32-CMOV-DAG: lw $[[R1:2]], 16($sp)
 ; 32-CMOV-DAG: lw $[[R2:3]], 20($sp)
 ; 32-CMOV-DAG: movz $[[R1]], $6, $[[R0]]
 ; 32-CMOV-DAG: movz $[[R2]], $7, $[[R0]]
 
 ; 32-CMP-DAG:  xori $[[R0:[0-9]+]], $4, 234
 ; 32-CMP-DAG:  lw $[[R1:[0-9]+]], 16($sp)
 ; 32-CMP-DAG:  lw $[[R2:[0-9]+]], 20($sp)
-; 32-CMP-DAG:  selnez $[[T0:[0-9]+]], $6, $[[R0]]
-; 32-CMP-DAG:  selnez $[[T1:[0-9]+]], $7, $[[R0]]
-; 32-CMP-DAG:  seleqz $[[T2:[0-9]+]], $[[R1]], $[[R0]]
-; 32-CMP-DAG:  seleqz $[[T3:[0-9]+]], $[[R2]], $[[R0]]
+; 32-CMP-DAG:  seleqz $[[T0:[0-9]+]], $6, $[[R0]]
+; 32-CMP-DAG:  seleqz $[[T1:[0-9]+]], $7, $[[R0]]
+; 32-CMP-DAG:  selnez $[[T2:[0-9]+]], $[[R1]], $[[R0]]
+; 32-CMP-DAG:  selnez $[[T3:[0-9]+]], $[[R2]], $[[R0]]
 ; 32-CMP-DAG:  or $2, $[[T0]], $[[T2]]
 ; 32-CMP-DAG:  or $3, $[[T1]], $[[T3]]
 
 ; 64-CMOV: xori $[[R0:[0-9]+]], $4, 234
 ; 64-CMOV: movz ${{[26]}}, $5, $[[R0]]
 
 ; 64-CMP-DAG:  xori $[[R0:[0-9]+]], $4, 234
-; 64-CMP-DAG:  selnez $[[T0:[0-9]+]], $5, $[[R0]]
-; 64-CMP-DAG:  seleqz $[[T1:[0-9]+]], $6, $[[R0]]
+; 64-CMP-DAG:  seleqz $[[T0:[0-9]+]], $5, $[[R0]]
+; 64-CMP-DAG:  selnez $[[T1:[0-9]+]], $6, $[[R0]]
 ; 64-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 define i64 @cmov4(i32 %a, i64 %b, i64 %c) nounwind readnone {
 entry:
   %cmp = icmp eq i32 %a, 234
   %cond = select i1 %cmp, i64 %b, i64 %c
   ret i64 %cond
 }

 ; 32-CMOV-DAG: addiu $[[I5:2]], $zero, 5
 ; 32-CMOV-DAG: slti $[[R0:[0-9]+]], $4, 32767
 ; 32-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]]
 
 ; 32-CMP-DAG:  addiu $[[I3:[0-9]+]], $zero, 3
 ; 32-CMP-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
 ; 32-CMP-DAG:  slti $[[R0:[0-9]+]], $4, 32767
 ; FIXME: We can do better than this by using selccz to choose between +0 and +2
-; 32-CMP-DAG:  selnez $[[T0:[0-9]+]], $[[I3]], $[[R0]]
-; 32-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]]
+; 32-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]
+; 32-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]
 ; 32-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 ; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3
 ; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5
 ; 64-CMOV-DAG: slti $[[R0:[0-9]+]], $4, 32767
 ; 64-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]]
 
 ; 64-CMP-DAG:  addiu $[[I3:[0-9]+]], $zero, 3
 ; 64-CMP-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
 ; 64-CMP-DAG:  slti $[[R0:[0-9]+]], $4, 32767
 ; FIXME: We can do better than this by using selccz to choose between +0 and +2
-; 64-CMP-DAG:  selnez $[[T0:[0-9]+]], $[[I3]], $[[R0]]
-; 64-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]]
+; 64-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]
+; 64-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]
 ; 64-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 define i32 @slti0(i32 %a) {
 entry:
   %cmp = icmp sgt i32 %a, 32766
   %cond = select i1 %cmp, i32 3, i32 5
   ret i32 %cond
 }

 ; 32-CMOV-DAG: addiu $[[I5:2]], $zero, 5
 ; 32-CMOV-DAG: slti $[[R0:[0-9]+]], $4, -32768
 ; 32-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]]
 
 ; 32-CMP-DAG:  addiu $[[I3:[0-9]+]], $zero, 3
 ; 32-CMP-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
 ; 32-CMP-DAG:  slti $[[R0:[0-9]+]], $4, -32768
 ; FIXME: We can do better than this by using selccz to choose between +0 and +2
-; 32-CMP-DAG:  selnez $[[T0:[0-9]+]], $[[I3]], $[[R0]]
-; 32-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]]
+; 32-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]
+; 32-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]
 ; 32-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 ; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3
 ; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5
 ; 64-CMOV-DAG: slti $[[R0:[0-9]+]], $4, -32768
 ; 64-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]]
 
 ; 64-CMP-DAG:  addiu $[[I3:[0-9]+]], $zero, 3
 ; 64-CMP-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
 ; 64-CMP-DAG:  slti $[[R0:[0-9]+]], $4, -32768
 ; FIXME: We can do better than this by using selccz to choose between +0 and +2
-; 64-CMP-DAG:  selnez $[[T0:[0-9]+]], $[[I3]], $[[R0]]
-; 64-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]]
+; 64-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]
+; 64-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]
 ; 64-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 define i32 @slti2(i32 %a) {
 entry:
   %cmp = icmp sgt i32 %a, -32769
   %cond = select i1 %cmp, i32 3, i32 5
   ret i32 %cond
 }

 ; 32-CMOV-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
 ; 32-CMOV-DAG:  addiu $[[I4:3]], $zero, 4
 ; 32-CMOV-DAG:  movn $[[I4]], $[[I5]], $[[CC]]
 ; 32-CMOV-DAG:  addiu $2, $zero, 0
 
 ; 32-CMP-DAG:   slt $[[CC0:[0-9]+]], $zero, $4
 ; 32-CMP-DAG:   addiu $[[I32766:[0-9]+]], $zero, 32766
 ; 32-CMP-DAG:   sltu $[[CC1:[0-9]+]], $[[I32766]], $5
-; 32-CMP-DAG:   seleqz $[[CC2:[0-9]+]], $[[CC0]], $4
-; 32-CMP-DAG:   selnez $[[CC3:[0-9]+]], $[[CC1]], $4
+; 32-CMP-DAG:   selnez $[[CC2:[0-9]+]], $[[CC0]], $4
+; 32-CMP-DAG:   seleqz $[[CC3:[0-9]+]], $[[CC1]], $4
 ; 32-CMP:       or $[[CC:[0-9]+]], $[[CC3]], $[[CC2]]
 ; 32-CMP-DAG:   addiu $[[I5:[0-9]+]], $zero, 5
 ; 32-CMP-DAG:   addiu $[[I4:[0-9]+]], $zero, 4
 ; 32-CMP-DAG:   seleqz $[[T0:[0-9]+]], $[[I4]], $[[CC]]
 ; 32-CMP-DAG:   selnez $[[T1:[0-9]+]], $[[I5]], $[[CC]]
 ; 32-CMP-DAG:   or $3, $[[T1]], $[[T0]]
 ; 32-CMP-DAG:   addiu $2, $zero, 0
 
 ; 64-CMOV-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
 ; 64-CMOV-DAG:  addiu $[[I4:2]], $zero, 4
 ; 64-CMOV-DAG:  slti $[[R0:[0-9]+]], $4, 32767
 ; 64-CMOV-DAG:  movz $[[I4]], $[[I5]], $[[R0]]
 
 ; 64-CMP-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
 ; 64-CMP-DAG:  addiu $[[I4:[0-9]+]], $zero, 4
 ; 64-CMP-DAG:  slti $[[R0:[0-9]+]], $4, 32767
 ; FIXME: We can do better than this by adding/subtracting the result of slti
 ;        to/from one of the constants.
-; 64-CMP-DAG:  selnez $[[T0:[0-9]+]], $[[I5]], $[[R0]]
-; 64-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I4]], $[[R0]]
+; 64-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I5]], $[[R0]]
+; 64-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I4]], $[[R0]]
 ; 64-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 define i64 @slti64_0(i64 %a) {
 entry:
   %cmp = icmp sgt i64 %a, 32766
   %conv = select i1 %cmp, i64 5, i64 4
   ret i64 %conv
 }
 
 ; ALL-LABEL: slti64_1:
 
 ; 32-CMOV-DAG:  slt $[[CC:[0-9]+]], $zero, $4
 ; 32-CMOV-DAG:  addiu $[[I32766:[0-9]+]], $zero, 32767
 ; 32-CMOV-DAG:  sltu $[[R1:[0-9]+]], $[[I32766]], $5
 ; 32-CMOV-DAG:  movz $[[CC:[0-9]+]], $[[R1]], $4
 ; 32-CMOV-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
 ; 32-CMOV-DAG:  addiu $[[I4:3]], $zero, 4
 ; 32-CMOV-DAG:  movn $[[I4]], $[[I5]], $[[CC]]
 ; 32-CMOV-DAG:  addiu $2, $zero, 0
 
 ; 32-CMP-DAG:   slt $[[CC0:[0-9]+]], $zero, $4
 ; 32-CMP-DAG:   addiu $[[I32766:[0-9]+]], $zero, 32767
 ; 32-CMP-DAG:   sltu $[[CC1:[0-9]+]], $[[I32766]], $5
-; 32-CMP-DAG:   seleqz $[[CC2:[0-9]+]], $[[CC0]], $4
-; 32-CMP-DAG:   selnez $[[CC3:[0-9]+]], $[[CC1]], $4
+; 32-CMP-DAG:   selnez $[[CC2:[0-9]+]], $[[CC0]], $4
+; 32-CMP-DAG:   seleqz $[[CC3:[0-9]+]], $[[CC1]], $4
 ; 32-CMP:       or $[[CC:[0-9]+]], $[[CC3]], $[[CC2]]
 ; 32-CMP-DAG:   addiu $[[I5:[0-9]+]], $zero, 5
 ; 32-CMP-DAG:   addiu $[[I4:[0-9]+]], $zero, 4
 ; 32-CMP-DAG:   seleqz $[[T0:[0-9]+]], $[[I4]], $[[CC]]
 ; 32-CMP-DAG:   selnez $[[T1:[0-9]+]], $[[I5]], $[[CC]]
 ; 32-CMP-DAG:   or $3, $[[T1]], $[[T0]]
 ; 32-CMP-DAG:   addiu $2, $zero, 0
 

 ; 64-CMOV-DAG:  slti $[[R0:[0-9]+]], $4, -32768
 ; 64-CMOV-DAG:  movz $[[I4]], $[[I3]], $[[R0]]
 
 ; 64-CMP-DAG:  addiu $[[I3:[0-9]+]], $zero, 3
 ; 64-CMP-DAG:  addiu $[[I4:[0-9]+]], $zero, 4
 ; 64-CMP-DAG:  slti $[[R0:[0-9]+]], $4, -32768
 ; FIXME: We can do better than this by adding/subtracting the result of slti
 ;        to/from one of the constants.
-; 64-CMP-DAG:  selnez $[[T0:[0-9]+]], $[[I3]], $[[R0]]
-; 64-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I4]], $[[R0]]
+; 64-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]
+; 64-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I4]], $[[R0]]
 ; 64-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 define i64 @slti64_2(i64 %a) {
 entry:
   %cmp = icmp sgt i64 %a, -32769
   %conv = select i1 %cmp, i64 3, i64 4
   ret i64 %conv
 }

 ; 32-CMOV-DAG: addiu $[[I5:2]], $zero, 5
 ; 32-CMOV-DAG: sltiu $[[R0:[0-9]+]], $4, 32767
 ; 32-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]]
 
 ; 32-CMP-DAG:  addiu $[[I3:[0-9]+]], $zero, 3
 ; 32-CMP-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
 ; 32-CMP-DAG:  sltiu $[[R0:[0-9]+]], $4, 32767
 ; FIXME: We can do better than this by using selccz to choose between +0 and +2
-; 32-CMP-DAG:  selnez $[[T0:[0-9]+]], $[[I3]], $[[R0]]
-; 32-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]]
+; 32-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]
+; 32-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]
 ; 32-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 ; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3
 ; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5
 ; 64-CMOV-DAG: sltiu $[[R0:[0-9]+]], $4, 32767
 ; 64-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]]
 
 ; 64-CMP-DAG:  addiu $[[I3:[0-9]+]], $zero, 3
 ; 64-CMP-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
 ; 64-CMP-DAG:  sltiu $[[R0:[0-9]+]], $4, 32767
 ; FIXME: We can do better than this by using selccz to choose between +0 and +2
-; 64-CMP-DAG:  selnez $[[T0:[0-9]+]], $[[I3]], $[[R0]]
-; 64-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]]
+; 64-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]
+; 64-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]
 ; 64-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 define i32 @sltiu0(i32 %a) {
 entry:
   %cmp = icmp ugt i32 %a, 32766
   %cond = select i1 %cmp, i32 3, i32 5
   ret i32 %cond
 }

 ; 32-CMOV-DAG: addiu $[[I5:2]], $zero, 5
 ; 32-CMOV-DAG: sltiu $[[R0:[0-9]+]], $4, -32768
 ; 32-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]]
 
 ; 32-CMP-DAG:  addiu $[[I3:[0-9]+]], $zero, 3
 ; 32-CMP-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
 ; 32-CMP-DAG:  sltiu $[[R0:[0-9]+]], $4, -32768
 ; FIXME: We can do better than this by using selccz to choose between +0 and +2
-; 32-CMP-DAG:  selnez $[[T0:[0-9]+]], $[[I3]], $[[R0]]
-; 32-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]]
+; 32-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]
+; 32-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]
 ; 32-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 ; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3
 ; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5
 ; 64-CMOV-DAG: sltiu $[[R0:[0-9]+]], $4, -32768
 ; 64-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]]
 
 ; 64-CMP-DAG:  addiu $[[I3:[0-9]+]], $zero, 3
 ; 64-CMP-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
 ; 64-CMP-DAG:  sltiu $[[R0:[0-9]+]], $4, -32768
 ; FIXME: We can do better than this by using selccz to choose between +0 and +2
-; 64-CMP-DAG:  selnez $[[T0:[0-9]+]], $[[I3]], $[[R0]]
-; 64-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]]
+; 64-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]
+; 64-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]
 ; 64-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 define i32 @sltiu2(i32 %a) {
 entry:
   %cmp = icmp ugt i32 %a, -32769
   %cond = select i1 %cmp, i32 3, i32 5
   ret i32 %cond
 }

test/CodeGen/Mips/countleading.ll

 ; ALL-LABEL: ctlz_i64:
 
 ; MIPS4-NOT:     dclz
 
 ; MIPS32-GT-R1-DAG: clz $[[R0:[0-9]+]], $4
 ; MIPS32-GT-R1-DAG: clz $[[R1:[0-9]+]], $5
 ; MIPS32-GT-R1-DAG: addiu $[[R2:2+]], $[[R0]], 32
 ; MIPS32-R1-R2-DAG: movn $[[R2]], $[[R1]], $5
-; MIPS32-R6-DAG:    selnez $[[R5:[0-9]+]], $[[R2]], $5
-; MIPS32-R6-DAG:    seleqz $[[R6:[0-9]+]], $[[R1]], $5
-; MIPS32-R6-DAG:    or $2, $[[R5]], $[[R6]]
+; MIPS32-R6-DAG:    seleqz $[[R5:[0-9]+]], $[[R2]], $5
+; MIPS32-R6-DAG:    selnez $[[R6:[0-9]+]], $[[R1]], $5
+; MIPS32-R6-DAG:    or $2, $[[R6]], $[[R5]]
 ; MIPS32-GT-R1-DAG: addiu $3, $zero, 0
 
 ; MIPS64-GT-R1:  dclz $2, $4
 
   %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
   ret i64 %tmp1
 }
 

test/CodeGen/Mips/mips64-f128.ll

 ; C_CC_FMT:      movn $9, $7, $4
 ; C_CC_FMT:      move $2, $8
 ; C_CC_FMT:      move $4, $9
 
 ; FIXME: This sll works around an implementation detail in the code generator
 ;        (setcc's result is i32 so bits 32-63 are undefined). It's not really
 ;        needed.
 ; CMP_CC_FMT-DAG: sll $[[CC:[0-9]+]], $4, 0
-; CMP_CC_FMT-DAG: selnez $[[EQ1:[0-9]+]], $8, $[[CC]]
-; CMP_CC_FMT-DAG: seleqz $[[NE1:[0-9]+]], $6, $[[CC]]
-; CMP_CC_FMT-DAG: or $2, $[[EQ1]], $[[NE1]]
-; CMP_CC_FMT-DAG: selnez $[[EQ2:[0-9]+]], $9, $[[CC]]
-; CMP_CC_FMT-DAG: seleqz $[[NE2:[0-9]+]], $7, $[[CC]]
-; CMP_CC_FMT-DAG: or $4, $[[EQ2]], $[[NE2]]
+; CMP_CC_FMT-DAG: seleqz $[[EQ1:[0-9]+]], $8, $[[CC]]
+; CMP_CC_FMT-DAG: selnez $[[NE1:[0-9]+]], $6, $[[CC]]
+; CMP_CC_FMT-DAG: or $2, $[[NE1]], $[[EQ1]]
+; CMP_CC_FMT-DAG: seleqz $[[EQ2:[0-9]+]], $9, $[[CC]]
+; CMP_CC_FMT-DAG: selnez $[[NE2:[0-9]+]], $7, $[[CC]]
+; CMP_CC_FMT-DAG: or $4, $[[NE2]], $[[EQ2]]
 
 define fp128 @select_LD(i32 %a, i64, fp128 %b, fp128 %c) {
 entry:
   %tobool = icmp ne i32 %a, 0
   %cond = select i1 %tobool, fp128 %b, fp128 %c
   ret fp128 %cond
 }
 

test/CodeGen/Mips/select.ll

 ; ALL-LABEL: i32_icmp_ne_i32_val:
 
 ; 32:            movn $5, $6, $4
 ; 32:            move $2, $5
 
 ; 32R2:          movn $5, $6, $4
 ; 32R2:          move $2, $5
 
-; 32R6-DAG:      selnez $[[T0:[0-9]+]], $5, $4
-; 32R6-DAG:      seleqz $[[T1:[0-9]+]], $6, $4
-; 32R6:          or $2, $[[T0]], $[[T1]]
+; 32R6-DAG:      seleqz $[[T0:[0-9]+]], $5, $4
+; 32R6-DAG:      selnez $[[T1:[0-9]+]], $6, $4
+; 32R6:          or $2, $[[T1]], $[[T0]]
 
 ; 64:            movn $5, $6, $4
 ; 64:            move $2, $5
 
 ; 64R2:          movn $5, $6, $4
 ; 64R2:          move $2, $5
 
-; 64R6-DAG:      selnez $[[T0:[0-9]+]], $5, $4
-; 64R6-DAG:      seleqz $[[T1:[0-9]+]], $6, $4
-; 64R6:          or $2, $[[T0]], $[[T1]]
+; 64R6-DAG:      seleqz $[[T0:[0-9]+]], $5, $4
+; 64R6-DAG:      selnez $[[T1:[0-9]+]], $6, $4
+; 64R6:          or $2, $[[T1]], $[[T0]]
 
   %tobool = icmp ne i32 %s, 0
   %cond = select i1 %tobool, i32 %f1, i32 %f0
   ret i32 %cond
 }
 
 define i64 @i32_icmp_ne_i64_val(i32 %s, i64 %f0, i64 %f1) nounwind readnone {
 entry:

 ; 32R2-DAG:      lw $[[F1:[0-9]+]], 16($sp)
 ; 32R2-DAG:      movn $6, $[[F1]], $4
 ; 32R2-DAG:      lw $[[F1H:[0-9]+]], 20($sp)
 ; 32R2:          movn $7, $[[F1H]], $4
 ; 32R2:          move $2, $6
 ; 32R2:          move $3, $7
 
 ; 32R6-DAG:      lw $[[F1:[0-9]+]], 16($sp)
-; 32R6-DAG:      selnez $[[T0:[0-9]+]], $6, $4
-; 32R6-DAG:      seleqz $[[T1:[0-9]+]], $[[F1]], $4
-; 32R6:          or $2, $[[T0]], $[[T1]]
+; 32R6-DAG:      seleqz $[[T0:[0-9]+]], $6, $4
+; 32R6-DAG:      selnez $[[T1:[0-9]+]], $[[F1]], $4
+; 32R6:          or $2, $[[T1]], $[[T0]]
 ; 32R6-DAG:      lw $[[F1H:[0-9]+]], 20($sp)
-; 32R6-DAG:      selnez $[[T0:[0-9]+]], $7, $4
-; 32R6-DAG:      seleqz $[[T1:[0-9]+]], $[[F1H]], $4
-; 32R6:          or $3, $[[T0]], $[[T1]]
+; 32R6-DAG:      seleqz $[[T0:[0-9]+]], $7, $4
+; 32R6-DAG:      selnez $[[T1:[0-9]+]], $[[F1H]], $4
+; 32R6:          or $3, $[[T1]], $[[T0]]
 
 ; 64:            movn $5, $6, $4
 ; 64:            move $2, $5
 
 ; 64R2:          movn $5, $6, $4
 ; 64R2:          move $2, $5
 
 ; FIXME: This sll works around an implementation detail in the code generator
 ;        (setcc's result is i32 so bits 32-63 are undefined). It's not really
 ;        needed.
 ; 64R6-DAG:      sll $[[CC:[0-9]+]], $4, 0
-; 64R6-DAG:      selnez $[[T0:[0-9]+]], $5, $[[CC]]
-; 64R6-DAG:      seleqz $[[T1:[0-9]+]], $6, $[[CC]]
-; 64R6:          or $2, $[[T0]], $[[T1]]
+; 64R6-DAG:      seleqz $[[T0:[0-9]+]], $5, $[[CC]]
+; 64R6-DAG:      selnez $[[T1:[0-9]+]], $6, $[[CC]]
+; 64R6:          or $2, $[[T1]], $[[T0]]
 
   %tobool = icmp ne i32 %s, 0
   %cond = select i1 %tobool, i64 %f1, i64 %f0
   ret i64 %cond
 }
 
 define i64 @i64_icmp_ne_i64_val(i64 %s, i64 %f0, i64 %f1) nounwind readnone {
 entry:

 ; 32R2-DAG:      movn $6, $[[F1]], $[[CC]]
 ; 32R2-DAG:      lw $[[F1H:[0-9]+]], 20($sp)
 ; 32R2:          movn $7, $[[F1H]], $[[CC]]
 ; 32R2:          move $2, $6
 ; 32R2:          move $3, $7
 
 ; 32R6-DAG:      lw $[[F1:[0-9]+]], 16($sp)
 ; 32R6-DAG:      or $[[T2:[0-9]+]], $4, $5
-; 32R6-DAG:      selnez $[[T0:[0-9]+]], $6, $[[T2]]
-; 32R6-DAG:      seleqz $[[T1:[0-9]+]], $[[F1]], $[[T2]]
-; 32R6:          or $2, $[[T0]], $[[T1]]
+; 32R6-DAG:      seleqz $[[T0:[0-9]+]], $6, $[[T2]]
+; 32R6-DAG:      selnez $[[T1:[0-9]+]], $[[F1]], $[[T2]]
+; 32R6:          or $2, $[[T1]], $[[T0]]
 ; 32R6-DAG:      lw $[[F1H:[0-9]+]], 20($sp)
-; 32R6-DAG:      selnez $[[T0:[0-9]+]], $7, $[[T2]]
-; 32R6-DAG:      seleqz $[[T1:[0-9]+]], $[[F1H]], $[[T2]]
-; 32R6:          or $3, $[[T0]], $[[T1]]
+; 32R6-DAG:      seleqz $[[T0:[0-9]+]], $7, $[[T2]]
+; 32R6-DAG:      selnez $[[T1:[0-9]+]], $[[F1H]], $[[T2]]
+; 32R6:          or $3, $[[T1]], $[[T0]]
 
 ; 64:            movn $5, $6, $4
 ; 64:            move $2, $5
 
 ; 64R2:          movn $5, $6, $4
 ; 64R2:          move $2, $5
 
-; 64R6-DAG:      selnez $[[T0:[0-9]+]], $5, $4
-; 64R6-DAG:      seleqz $[[T1:[0-9]+]], $6, $4
-; 64R6:          or $2, $[[T0]], $[[T1]]
+; 64R6-DAG:      seleqz $[[T0:[0-9]+]], $5, $4
+; 64R6-DAG:      selnez $[[T1:[0-9]+]], $6, $4
+; 64R6:          or $2, $[[T1]], $[[T0]]
 
   %tobool = icmp ne i64 %s, 0
   %cond = select i1 %tobool, i64 %f1, i64 %f0
   ret i64 %cond
 }
 
 define float @i32_icmp_ne_f32_val(i32 %s, float %f0, float %f1) nounwind readnone {
 entry: