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Differential D4265

[mips] Added support for assembling sdbbp.
ClosedPublic

Authored by dsanders on Jun 24 2014, 2:43 AM.

Details

Reviewers
jkolek
vmedic
zoran.jovanovic
Commits
rGe6198bf886cf: [mips] Added support for assembling sdbbp.
rL211590: [mips] Added support for assembling sdbbp.
Summary

This instruction is re-encoded in MIPS32r6/MIPS64r6 without changing the
restrictions. We hadn't implemented it for earlier ISA's so it has been added to those too.

Diff Detail

Event Timeline

dsanders updated this revision to Diff 10775.Jun 24 2014, 2:43 AM
dsanders retitled this revision from to [mips] Added support for assembling sdbbp..
dsanders updated this object.
dsanders edited the test plan for this revision. (Show Details)
dsanders added reviewers: jkolek, vmedic, zoran.jovanovic.
dsanders updated this object.Jun 24 2014, 2:45 AM
vmedic accepted this revision.Jun 24 2014, 3:30 AM
vmedic edited edge metadata.

LGTM

This revision is now accepted and ready to land.Jun 24 2014, 3:30 AM
dsanders closed this revision.Jun 24 2014, 6:08 AM

Revision Contents

PathSize
lib/
Target/
Mips/
11 lines
31 lines
10 lines
2 lines
test/
MC/
Mips/
mips32/
2 lines
mips32r2/
2 lines
mips32r6/
2 lines
mips64/
2 lines
mips64r2/
2 lines
mips64r6/
2 lines

Diff 10775

lib/Target/Mips/Mips32r6InstrFormats.td

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def OPCODE6_SC : OPCODE6<0b100110>; def OPCODE6_SC : OPCODE6<0b100110>;
def OPCODE6_SCD : OPCODE6<0b100111>; def OPCODE6_SCD : OPCODE6<0b100111>;
def OPCODE6_CLO : OPCODE6<0b010001>; def OPCODE6_CLO : OPCODE6<0b010001>;
def OPCODE6_CLZ : OPCODE6<0b010000>; def OPCODE6_CLZ : OPCODE6<0b010000>;
def OPCODE6_DCLO : OPCODE6<0b010011>; def OPCODE6_DCLO : OPCODE6<0b010011>;
def OPCODE6_DCLZ : OPCODE6<0b010010>; def OPCODE6_DCLZ : OPCODE6<0b010010>;
def OPCODE6_LSA : OPCODE6<0b000101>; def OPCODE6_LSA : OPCODE6<0b000101>;
def OPCODE6_DLSA : OPCODE6<0b010101>; def OPCODE6_DLSA : OPCODE6<0b010101>;
def OPCODE6_SDBBP : OPCODE6<0b001110>;
class FIELD_FMT<bits<5> Val> { class FIELD_FMT<bits<5> Val> {
bits<5> Value = Val; bits<5> Value = Val;
} }
def FIELD_FMT_S : FIELD_FMT<0b10000>; def FIELD_FMT_S : FIELD_FMT<0b10000>;
def FIELD_FMT_D : FIELD_FMT<0b10001>; def FIELD_FMT_D : FIELD_FMT<0b10001>;
class FIELD_CMP_COND<bits<5> Val> { class FIELD_CMP_COND<bits<5> Val> {
▲ Show 20 Lines • Show All 215 Lines • ▼ Show 20 Linesclass SPECIAL_3R_FM<bits<5> mulop, bits<6> funct> : MipsR6Inst {
let Inst{31-26} = OPGROUP_SPECIAL.Value; let Inst{31-26} = OPGROUP_SPECIAL.Value;
let Inst{25-21} = rs; let Inst{25-21} = rs;
let Inst{20-16} = rt; let Inst{20-16} = rt;
let Inst{15-11} = rd; let Inst{15-11} = rd;
let Inst{10-6} = mulop; let Inst{10-6} = mulop;
let Inst{5-0} = funct; let Inst{5-0} = funct;
} }
class SPECIAL_SDBBP_FM : MipsR6Inst {
bits<20> code_;
bits<32> Inst;
let Inst{31-26} = OPGROUP_SPECIAL.Value;
let Inst{25-6} = code_;
let Inst{5-0} = OPCODE6_SDBBP.Value;
}
// This class is ambiguous with other branches: // This class is ambiguous with other branches:
// BEQC/BNEC require that rs > rt // BEQC/BNEC require that rs > rt
class CMP_BRANCH_2R_OFF16_FM<OPGROUP funct> : MipsR6Inst { class CMP_BRANCH_2R_OFF16_FM<OPGROUP funct> : MipsR6Inst {
bits<5> rs; bits<5> rs;
bits<5> rt; bits<5> rt;
bits<16> offset; bits<16> offset;
bits<32> Inst; bits<32> Inst;
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lib/Target/Mips/Mips32r6InstrInfo.td

Show All 10 Lines
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
include "Mips32r6InstrFormats.td" include "Mips32r6InstrFormats.td"
// Notes about removals/changes from MIPS32r6: // Notes about removals/changes from MIPS32r6:
// Reencoded: jr -> jalr // Reencoded: jr -> jalr
// Reencoded: jr.hb -> jalr.hb // Reencoded: jr.hb -> jalr.hb
// Reencoded: sdbbp
def brtarget21 : Operand<OtherVT> { def brtarget21 : Operand<OtherVT> {
let EncoderMethod = "getBranchTarget21OpValue"; let EncoderMethod = "getBranchTarget21OpValue";
let OperandType = "OPERAND_PCREL"; let OperandType = "OPERAND_PCREL";
let DecoderMethod = "DecodeBranchTarget21"; let DecoderMethod = "DecodeBranchTarget21";
let ParserMatchClass = MipsJumpTargetAsmOperand; let ParserMatchClass = MipsJumpTargetAsmOperand;
} }
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class LSA_R6_ENC : SPECIAL_LSA_FM<OPCODE6_LSA>; class LSA_R6_ENC : SPECIAL_LSA_FM<OPCODE6_LSA>;
class LL_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LL>; class LL_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LL>;
class SC_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SC>; class SC_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SC>;
class CLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLO>; class CLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLO>;
class CLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLZ>; class CLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLZ>;
class SDBBP_R6_ENC : SPECIAL_SDBBP_FM;
//===----------------------------------------------------------------------===//
//
// Instruction Multiclasses
//
//===----------------------------------------------------------------------===//
class CMP_CONDN_DESC_BASE<string CondStr, string Typestr, class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,
RegisterOperand FGROpnd, RegisterOperand FGROpnd,
SDPatternOperator Op = null_frag> { SDPatternOperator Op = null_frag> {
dag OutOperandList = (outs FGRCCOpnd:$fd); dag OutOperandList = (outs FGRCCOpnd:$fd);
dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft); dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft"); string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))]; list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))];
} }
//===----------------------------------------------------------------------===//
//
// Instruction Multiclasses
//
//===----------------------------------------------------------------------===//
multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr, multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
RegisterOperand FGROpnd>{ RegisterOperand FGROpnd>{
def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_F>, def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_F>,
CMP_CONDN_DESC_BASE<"f", Typestr, FGROpnd>, CMP_CONDN_DESC_BASE<"f", Typestr, FGROpnd>,
ISA_MIPS32R6; ISA_MIPS32R6;
def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>, def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>, CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>,
ISA_MIPS32R6; ISA_MIPS32R6;
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class CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> : class CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> :
CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd> { CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd> {
list<dag> Pattern = [(set GPROpnd:$rd, (ctlz GPROpnd:$rs))]; list<dag> Pattern = [(set GPROpnd:$rd, (ctlz GPROpnd:$rs))];
} }
class CLO_R6_DESC : CLO_R6_DESC_BASE<"clo", GPR32Opnd>; class CLO_R6_DESC : CLO_R6_DESC_BASE<"clo", GPR32Opnd>;
class CLZ_R6_DESC : CLZ_R6_DESC_BASE<"clz", GPR32Opnd>; class CLZ_R6_DESC : CLZ_R6_DESC_BASE<"clz", GPR32Opnd>;
class SDBBP_R6_DESC {
dag OutOperandList = (outs);
dag InOperandList = (ins uimm20:$code_);
string AsmString = "sdbbp\t$code_";
list<dag> Pattern = [];
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Instruction Definitions // Instruction Definitions
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6; def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6; def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
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def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6; def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6; def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6; def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
def NAL; // BAL with rd=0 def NAL; // BAL with rd=0
def PREF_R6 : PREF_ENC, PREF_DESC, ISA_MIPS32R6; def PREF_R6 : PREF_ENC, PREF_DESC, ISA_MIPS32R6;
def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6; def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6;
def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6; def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6;
def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6; def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6;
def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6;
def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6; def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
def SELEQZ : SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32; def SELEQZ : SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6; def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6; def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
def SELNEZ : SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32; def SELNEZ : SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6; def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6; def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6; def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6; def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;
def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6; def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Instruction Aliases
//
//===----------------------------------------------------------------------===//
def : MipsInstAlias<"sdbbp", (SDBBP_R6 0)>, ISA_MIPS32R6;
//===----------------------------------------------------------------------===//
//
// Patterns and Pseudo Instructions // Patterns and Pseudo Instructions
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// f32 comparisons supported via another comparison // f32 comparisons supported via another comparison
def : MipsPat<(setone f32:$lhs, f32:$rhs), def : MipsPat<(setone f32:$lhs, f32:$rhs),
(NOR (CMP_UEQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6; (NOR (CMP_UEQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
def : MipsPat<(seto f32:$lhs, f32:$rhs), def : MipsPat<(seto f32:$lhs, f32:$rhs),
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lib/Target/Mips/MipsInstrFormats.td

Show First 20 Lines • Show All 838 Lines • ▼ Show 20 Linesclass BARRIER_FM<bits<5> op> : StdArch {
let Inst{31-26} = 0; // SPECIAL let Inst{31-26} = 0; // SPECIAL
let Inst{25-21} = 0; let Inst{25-21} = 0;
let Inst{20-16} = 0; // rt = 0 let Inst{20-16} = 0; // rt = 0
let Inst{15-11} = 0; // rd = 0 let Inst{15-11} = 0; // rd = 0
let Inst{10-6} = op; // Operation let Inst{10-6} = op; // Operation
let Inst{5-0} = 0; // SLL let Inst{5-0} = 0; // SLL
} }
class SDBBP_FM : StdArch {
bits<20> code_;
bits<32> Inst;
let Inst{31-26} = 0b011100; // SPECIAL2
let Inst{25-6} = code_;
let Inst{5-0} = 0b111111; // SDBBP
}
class JR_HB_FM<bits<6> op> : StdArch{ class JR_HB_FM<bits<6> op> : StdArch{
bits<5> rs; bits<5> rs;
bits<32> Inst; bits<32> Inst;
let Inst{31-26} = 0; // SPECIAL let Inst{31-26} = 0; // SPECIAL
let Inst{25-21} = rs; let Inst{25-21} = rs;
let Inst{20-11} = 0; let Inst{20-11} = 0;
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lib/Target/Mips/MipsInstrInfo.td

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def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>, def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
ISA_MIPS2_NOT_32R6_64R6; ISA_MIPS2_NOT_32R6_64R6;
def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>, def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
ISA_MIPS2_NOT_32R6_64R6; ISA_MIPS2_NOT_32R6_64R6;
def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>; def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>; def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
def TRAP : TrapBase<BREAK>; def TRAP : TrapBase<BREAK>;
def SDBBP : SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32; def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32; def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2; def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2; def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
▲ Show 20 Lines • Show All 292 Lines • ▼ Show 20 Linesdef : MipsInstAlias<"subu, $rd, $rs, $imm",
(ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
InvertedImOperand:$imm), 0>; InvertedImOperand:$imm), 0>;
def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
InvertedImOperand:$imm), 0>; InvertedImOperand:$imm), 0>;
def : MipsInstAlias<"sra $rd, $rt, $rs", def : MipsInstAlias<"sra $rd, $rt, $rs",
(SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<"srl $rd, $rt, $rs", def : MipsInstAlias<"srl $rd, $rt, $rs",
(SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
def : MipsInstAlias<"sync", def : MipsInstAlias<"sync",
(SYNC 0), 1>, ISA_MIPS2; (SYNC 0), 1>, ISA_MIPS2;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Assembler Pseudo Instructions // Assembler Pseudo Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> : class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
▲ Show 20 Lines • Show All 244 Lines • Show Last 20 Lines

test/MC/Mips/mips32/valid.s

Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | FileCheck %s
nor $a3,$zero,$a3 nor $a3,$zero,$a3
or $12,$s0,$sp or $12,$s0,$sp
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
round.w.d $f6,$f4 round.w.d $f6,$f4
round.w.s $f27,$f28 round.w.s $f27,$f28
sb $s6,-19857($14) sb $s6,-19857($14)
sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8] sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8]
sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f]
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
sdc1 $f31,30574($13) sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sh $14,-6704($15) sh $14,-6704($15)
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
Show All 39 Lines

test/MC/Mips/mips32r2/valid.s

Show First 20 Lines • Show All 134 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
rdhwr $sp,$11 rdhwr $sp,$11
rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2]
rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2] rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2]
rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46] rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
round.w.d $f6,$f4 round.w.d $f6,$f4
round.w.s $f27,$f28 round.w.s $f27,$f28
sb $s6,-19857($14) sb $s6,-19857($14)
sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8] sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8]
sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f]
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
sdc1 $f31,30574($13) sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdxc1 $f11,$10($14) sdxc1 $f11,$10($14)
seb $25,$15 seb $25,$15
seh $v1,$12 seh $v1,$12
sh $14,-6704($15) sh $14,-6704($15)
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
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test/MC/Mips/mips32r6/valid.s

Show First 20 Lines • Show All 142 Lines • ▼ Show 20 Lines# RUN: FileCheck %s -check-prefix=WARNING < %t0
sdc2 $20,629($s2) # CHECK: sdc2 $20, 629($18) # encoding: [0x49,0xf4,0x92,0x75] sdc2 $20,629($s2) # CHECK: sdc2 $20, 629($18) # encoding: [0x49,0xf4,0x92,0x75]
swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30] swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30]
ll $v0,-153($s2) # CHECK: ll $2, -153($18) # encoding: [0x7e,0x42,0xb3,0xb6] ll $v0,-153($s2) # CHECK: ll $2, -153($18) # encoding: [0x7e,0x42,0xb3,0xb6]
sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26] sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26]
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x00,0xa0,0x58,0x51] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x00,0xa0,0x58,0x51]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50]
ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS32r6 and is equivalent to a nop instruction ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS32r6 and is equivalent to a nop instruction
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sdbbp # CHECK: sdbbp # encoding: [0x00,0x00,0x00,0x0e]
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x00,0x08,0x8e]
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]

test/MC/Mips/mips64/valid.s

Show First 20 Lines • Show All 170 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | FileCheck %s
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
round.l.d $f12,$f1 round.l.d $f12,$f1
round.l.s $f25,$f5 round.l.s $f25,$f5
round.w.d $f6,$f4 round.w.d $f6,$f4
round.w.s $f27,$f28 round.w.s $f27,$f28
sb $s6,-19857($14) sb $s6,-19857($14)
sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8] sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8]
scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd] scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd]
sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f]
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
sd $12,5835($10) sd $12,5835($10)
sdc1 $f31,30574($13) sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdl $a3,-20961($s8) sdl $a3,-20961($s8)
sdr $11,-20423($12) sdr $11,-20423($12)
sdxc1 $f11,$10($14) sdxc1 $f11,$10($14)
sh $14,-6704($15) sh $14,-6704($15)
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
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test/MC/Mips/mips64r2/valid.s

Show First 20 Lines • Show All 195 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s
rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46] rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
round.l.d $f12,$f1 round.l.d $f12,$f1
round.l.s $f25,$f5 round.l.s $f25,$f5
round.w.d $f6,$f4 round.w.d $f6,$f4
round.w.s $f27,$f28 round.w.s $f27,$f28
sb $s6,-19857($14) sb $s6,-19857($14)
sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8] sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8]
scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd] scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd]
sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f]
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
sd $12,5835($10) sd $12,5835($10)
sdc1 $f31,30574($13) sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdl $a3,-20961($s8) sdl $a3,-20961($s8)
sdr $11,-20423($12) sdr $11,-20423($12)
sdxc1 $f11,$10($14) sdxc1 $f11,$10($14)
seb $25,$15 seb $25,$15
seh $v1,$12 seh $v1,$12
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test/MC/Mips/mips64r6/valid.s

Show First 20 Lines • Show All 161 Lines • ▼ Show 20 Lines# RUN: FileCheck %s -check-prefix=WARNING < %t0
sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26] sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26]
scd $15,-51($sp) # CHECK: scd $15, -51($sp) # encoding: [0x7f,0xaf,0xe6,0xa7] scd $15,-51($sp) # CHECK: scd $15, -51($sp) # encoding: [0x7f,0xaf,0xe6,0xa7]
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x00,0xa0,0x58,0x51] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x00,0xa0,0x58,0x51]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50]
dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x00,0xc0,0x90,0x53] dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x00,0xc0,0x90,0x53]
dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x03,0x20,0x80,0x52] dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x03,0x20,0x80,0x52]
ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS64r6 and is equivalent to a nop instruction ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS64r6 and is equivalent to a nop instruction
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sdbbp # CHECK: sdbbp # encoding: [0x00,0x00,0x00,0x0e]
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x00,0x08,0x8e]
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]