Do materialize for floating point

[rkotler]

Summary

Implement materialization of floating point constants in Mips fast-isel.

[dsanders]

Can you edit the summary to describe what the patch is for? It appears to be a list of commits at the moment.

lib/Target/Mips/MipsFastISel.cpp

232–249

I'd put the cast in the caller. The caller would then use something like:

if (ConstantFP *Tmp = dyn_cast<ConstantFP>(C))
  return MaterializeFP(Tmp, ...);
else if (ConstantInt *Tmp = dyn_cast<ConstantInt>(C))
  return MaterializeInt(Tmp, ...);
...

267–304

This was already in the previous patch

test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll

32–33

It isn't necessary for this patch, but just to let you know. I believe we need to make emit mthc1 to copy the upper 32-bits for the FRmodeless work

test/CodeGen/Mips/Fast-ISel/simplestorei.ll

1–63 ↗

(On Diff #9189)

This was in the previous patch

[rkotler]

• Merge branch '1758_6' into 1758_7
• in progress fp merge

[rkotler]

• simplify a test
• simplify call

[rkotler]

Need to run clang-format before putback.

test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll

32–33

I'm going to change this anyway to do loads from the constant pool rather than synthesizing the literal. For sure there will be some changes to handle modeless and also when we do mips64.

test/CodeGen/Mips/Fast-ISel/simplestorei.ll

1–63 ↗

(On Diff #9189)

I was not sure how to just make the delta. I surely won't commit the file again.

[dsanders]

LGTM with the change about putting the cast() in the caller as a dyn_cast() instead of using isa() and cast()

test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll

32–33

I assume that some constants will still synthesize the literal. At minimum, 0.0 shouldn't use the constant pool.

test/CodeGen/Mips/Fast-ISel/simplestorei.ll

1–63 ↗

(On Diff #9189)

'arc diff $git_revision' will make the delta from the specified revision instead of the default origin/master.

[rkotler]

I did not understand the comment about using dyn_cast instead of isa.

I will commit as is and make the update after. You can explain what you meant to me.

[dsanders]

I did not understand the comment about using dyn_cast instead of isa.

As discussed on the r210414 post-commit review thread, it seems you already made this change in r207790. The original diff for this revision passed a Constant* into MaterializeFP and used isa() in the caller, and cast() in the callee. The request was to move the cast() to the caller, combine it with the isa() to make a dyn_cast(), and change MaterializeFP to take a ConstantFP* instead of Constant*.

The patch here is rather noisy but rL210414 as committed looks good to me (apart from the commit message which should be corrected before you re-commit).

[rkotler]

Fixed summary and test case description.

lib/Target/Mips/MipsFastISel.cpp

 //===-- MipsastISel.cpp - Mips FastISel implementation
 //---------------------===//
 
 #include "llvm/CodeGen/FunctionLoweringInfo.h"
 #include "llvm/CodeGen/FastISel.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/IR/GlobalAlias.h"
 #include "llvm/IR/GlobalVariable.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetLibraryInfo.h"
 #include "MipsRegisterInfo.h"
 #include "MipsISelLowering.h"
 #include "MipsMachineFunction.h"
 #include "MipsSubtarget.h"
+#include "MipsTargetMachine.h"
 
 using namespace llvm;
 
 namespace {
 
 // All possible address modes.
 typedef struct Address {
   enum { RegBase, FrameIndexBase } BaseType;
 
   union {
     unsigned Reg;
     int FI;
   } Base;
 
   int64_t Offset;
 
   // Innocuous defaults for our address.
   Address() : BaseType(RegBase), Offset(0) { Base.Reg = 0; }
 } Address;
 
 class MipsFastISel final : public FastISel {
 
   /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
   /// make the right decision when generating code for different targets.
-  const MipsSubtarget *Subtarget;
   Module &M;
   const TargetMachine &TM;
   const TargetInstrInfo &TII;
   const TargetLowering &TLI;
+  const MipsSubtarget &Subtarget;
   MipsFunctionInfo *MFI;
 
   // Convenience variables to avoid some queries.
   LLVMContext *Context;
 
   bool TargetSupported;
 
 public:
   explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
                         const TargetLibraryInfo *libInfo)
       : FastISel(funcInfo, libInfo),
         M(const_cast<Module &>(*funcInfo.Fn->getParent())),
         TM(funcInfo.MF->getTarget()), TII(*TM.getInstrInfo()),
-        TLI(*TM.getTargetLowering()) {
-    Subtarget = &TM.getSubtarget<MipsSubtarget>();
+        TLI(*TM.getTargetLowering()),
+        Subtarget(TM.getSubtarget<MipsSubtarget>()) {
     MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
     Context = &funcInfo.Fn->getContext();
-    TargetSupported = ((Subtarget->getRelocationModel() == Reloc::PIC_) &&
-                       (Subtarget->hasMips32r2() && (Subtarget->isABI_O32())));
+    TargetSupported = ((Subtarget.getRelocationModel() == Reloc::PIC_) &&
+                       (Subtarget.hasMips32r2() && (Subtarget.isABI_O32())));
   }
 
   bool TargetSelectInstruction(const Instruction *I) override;
   unsigned TargetMaterializeConstant(const Constant *C) override;
 
   bool ComputeAddress(const Value *Obj, Address &Addr);
 
 private:
   bool EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
                  unsigned Alignment = 0);
   bool SelectRet(const Instruction *I);
   bool SelectStore(const Instruction *I);
 
   bool isTypeLegal(Type *Ty, MVT &VT);
   bool isLoadTypeLegal(Type *Ty, MVT &VT);
 
   unsigned MaterializeFP(const ConstantFP *CFP, MVT VT);
   unsigned MaterializeGV(const GlobalValue *GV, MVT VT);
   unsigned MaterializeInt(const Constant *C, MVT VT);
   unsigned Materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
+
+  unsigned FastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
+                             unsigned Op0, bool Op0IsKill, uint64_t imm1,
+                             uint64_t imm2, unsigned Op3, bool Op3IsKill) {
+    return 0;
+  }
+
+  MachineInstrBuilder EmitInst(unsigned Opc) {
+    return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
+  }
+
+  MachineInstrBuilder EmitInst(unsigned Opc, unsigned DstReg) {
+    return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DstReg);
+  }
+
+  MachineInstrBuilder EmitInstStore(unsigned Opc, unsigned SrcReg, unsigned MemReg , int64_t MemOffset) {
+    return EmitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
+  }
+
+#include "MipsGenFastISel.inc"
 };
 
 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
   EVT evt = TLI.getValueType(Ty, true);
   // Only handle simple types.
   if (evt == MVT::Other || !evt.isSimple())
     return false;
   VT = evt.getSimpleVT();
unsigned MipsFastISel::TargetMaterializeConstant(const Constant *C) {
   return 0;
 }
 
 bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
                              unsigned Alignment) {
   //
   // more cases will be handled here in following patches.
   //
-  if (VT != MVT::i32)
+  if (VT == MVT::i32)
+    EmitInstStore(Mips::SW, SrcReg, Addr.Base.Reg, Addr.Offset);
+  else if (VT == MVT::f32)
+    EmitInstStore(Mips::SWC1, SrcReg, Addr.Base.Reg, Addr.Offset);
+  else if (VT == MVT::f64)
+    EmitInstStore(Mips::SDC1, SrcReg, Addr.Base.Reg, Addr.Offset);
+  else
     return false;
-  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::SW))
-      .addReg(SrcReg)
-      .addReg(Addr.Base.Reg)
-      .addImm(Addr.Offset);
   return true;
 }
 
 bool MipsFastISel::SelectStore(const Instruction *I) {
   Value *Op0 = I->getOperand(0);
   unsigned SrcReg = 0;
 
   // Atomic stores need special handling.

 bool MipsFastISel::SelectRet(const Instruction *I) {
   const ReturnInst *Ret = cast<ReturnInst>(I);
 
   if (!FuncInfo.CanLowerReturn)
     return false;
   if (Ret->getNumOperands() > 0) {
     return false;
   }
-  unsigned RetOpc = Mips::RetRA;
-  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(RetOpc));
+  EmitInst(Mips::RetRA);
   return true;
 }
 
 bool MipsFastISel::TargetSelectInstruction(const Instruction *I) {
   if (!TargetSupported)
     return false;
   switch (I->getOpcode()) {
   default:
     break;
   case Instruction::Store:
     return SelectStore(I);
   case Instruction::Ret:
     return SelectRet(I);
   }
   return false;
 }
 }
 
 unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) {
+  int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
+  if (VT == MVT::f32) {
+    const TargetRegisterClass *RC = &Mips::FGR32RegClass;
+    unsigned DestReg = createResultReg(RC);
+    unsigned TempReg = Materialize32BitInt(Imm, &Mips::GPR32RegClass);
+    EmitInst(Mips::MTC1, DestReg).addReg(TempReg);
+    return DestReg;
+  } else if (VT == MVT::f64) {
+    const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
+    unsigned DestReg = createResultReg(RC);
+    unsigned TempReg1 = Materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
+    unsigned TempReg2 =
+        Materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
+    EmitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
+    return DestReg;
+  }
   return 0;
 }
 
 unsigned MipsFastISel::MaterializeGV(const GlobalValue *GV, MVT VT) {
   // For now 32-bit only.
   if (VT != MVT::i32)
     return 0;
   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
   unsigned DestReg = createResultReg(RC);
   const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
   bool IsThreadLocal = GVar && GVar->isThreadLocal();
   // TLS not supported at this time.
   if (IsThreadLocal)
     return 0;
-  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LW), DestReg)
-      .addReg(MFI->getGlobalBaseReg())
+  EmitInst(Mips::LW, DestReg).addReg(MFI->getGlobalBaseReg())
       .addGlobalAddress(GV, 0, MipsII::MO_GOT);
   return DestReg;
 }
 unsigned MipsFastISel::MaterializeInt(const Constant *C, MVT VT) {
   if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
     return 0;
   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
   const ConstantInt *CI = cast<ConstantInt>(C);
   int64_t Imm;
   if (CI->isNegative())
     Imm = CI->getSExtValue();
   else
     Imm = CI->getZExtValue();
   return Materialize32BitInt(Imm, RC);
 }
 
 unsigned MipsFastISel::Materialize32BitInt(int64_t Imm,
                                            const TargetRegisterClass *RC) {
   unsigned ResultReg = createResultReg(RC);
 
   if (isInt<16>(Imm)) {
     unsigned Opc = Mips::ADDiu;
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
-        .addReg(Mips::ZERO)
-        .addImm(Imm);
+    EmitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
     return ResultReg;
   } else if (isUInt<16>(Imm)) {
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::ORi),
-            ResultReg)
-        .addReg(Mips::ZERO)
-        .addImm(Imm);
+    EmitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
     return ResultReg;
   }
   unsigned Lo = Imm & 0xFFFF;
   unsigned Hi = (Imm >> 16) & 0xFFFF;
   if (Lo) {
     // Both Lo and Hi have nonzero bits.
     unsigned TmpReg = createResultReg(RC);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LUi),
-            TmpReg).addImm(Hi);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::ORi),
-            ResultReg)
-        .addReg(TmpReg)
-        .addImm(Lo);
+    EmitInst(Mips::LUi, TmpReg).addImm(Hi);
+    EmitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
 
   } else {
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LUi),
-            ResultReg).addImm(Hi);
+    EmitInst(Mips::LUi, ResultReg).addImm(Hi);
   }
   return ResultReg;
 }
 
 namespace llvm {
 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
                                const TargetLibraryInfo *libInfo) {
   return new MipsFastISel(funcInfo, libInfo);
 }
 }

test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll

+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN:     < %s | FileCheck %s
+
+@f = common global float 0.000000e+00, align 4
+@de = common global double 0.000000e+00, align 8
+
+; Function Attrs: nounwind
+define void @f1() #0 {
+entry:
+  store float 0x3FFA76C8C0000000, float* @f, align 4
+  ret void
+; CHECK:  .ent  f1
+; CHECK:  lui $[[REG1:[0-9]+]], 16339
+; CHECK:  ori $[[REG2:[0-9]+]], $[[REG1]], 46662
+; CHECK:  mtc1  $[[REG2]], $f[[REG3:[0-9]+]]
+; CHECK:  lw  $[[REG4:[0-9]+]], %got(f)(${{[0-9]+}})
+; CHECK:  swc1  $f[[REG3]], 0($[[REG4]])
+; CHECK:  .end  f1
+
+}
+
+; Function Attrs: nounwind
+define void @d1() #0 {
+entry:
+  store double 1.234567e+00, double* @de, align 8
+; CHECK:  .ent  d1
+; CHECK:  lui $[[REG1a:[0-9]+]], 16371
+; CHECK:  ori $[[REG2a:[0-9]+]], $[[REG1a]], 49353
+; CHECK:  lui $[[REG1b:[0-9]+]], 21403
+; CHECK:  ori $[[REG2b:[0-9]+]], $[[REG1b]], 34951
+; CHECK:  mtc1  $[[REG2b]], $f[[REG3b:[0-9]+]]
+; CHECK:  mtc1  $[[REG2a]], $f[[REG3a:[0-9]+]]
+; CHECK:  sdc1  $f[[REG3b]], 0(${{[0-9]+}})
+; CHECK:  .end  d1
+  ret void
+}
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+