[mips] Emit all three relocation operations for each relocation entry on Mips64 big-endian systems.

[matheusalmeida]

Summary

The N64 ABI allows up to three operations to be specified per relocation record
independently of the endianness.

[matheusalmeida]

Daniel,

If you think it's best to CC the mailing list just say so.

Matheus

[dsanders]

When we were discussing this triple reloc mechanism you mentioned that the Type was subject to endianness (and was a strange mixed endian) but I don't see any endian conversions in the patch. Is that handled by the code in ELFRelBase<...>::getRInfo()? If so, then it LGTM.

If you think it's best to CC the mailing list just say so.

You're only touching existing MIPS specific code so I think it's unnecessary in this case.

include/llvm/Object/ELF.h

549–554

Thanks for adding the explanation. One small correction: only MIPS ELF64's can be assumed to be N64. You currently say all ELF64's.

[matheusalmeida]

Is that handled by the code in ELFRelBase<...>::getRInfo()

That's correct.

include/llvm/Object/ELF.h

549–554

Yeah... I wanted to write"all Mips ELF::ELFCLASS64 ELFs are N64."...

[matheusalmeida]

Fix comment.

include/llvm/Object/ELF.h

public:
 
   /// \brief Get the symbol table section and symbol for a given relocation.
   template <class RelT>
   std::pair<const Elf_Shdr *, const Elf_Sym *>
   getRelocationSymbol(const Elf_Shdr *RelSec, const RelT *Rel) const;
 
   ELFFile(MemoryBuffer *Object, error_code &ec);
 
+  bool isMipsELF64() const {
+    return Header->e_machine == ELF::EM_MIPS &&
+      Header->getFileClass() == ELF::ELFCLASS64;
+  }
+
   bool isMips64EL() const {
     return Header->e_machine == ELF::EM_MIPS &&
       Header->getFileClass() == ELF::ELFCLASS64 &&
       Header->getDataEncoding() == ELF::ELFDATA2LSB;
   }
 
   Elf_Shdr_Iter begin_sections() const;
   Elf_Shdr_Iter end_sections() const;

 template <class ELFT>
 StringRef ELFFile<ELFT>::getRelocationTypeName(uint32_t Type) const {
   return getELFRelocationTypeName(Header->e_machine, Type);
 }
 
 template <class ELFT>
 void ELFFile<ELFT>::getRelocationTypeName(uint32_t Type,
                                           SmallVectorImpl<char> &Result) const {
-  if (!isMips64EL()) {
+  if (!isMipsELF64()) {
     StringRef Name = getRelocationTypeName(Type);
     Result.append(Name.begin(), Name.end());
   } else {
+    // The Mips N64 ABI allows up to three operations to be specified per
+    // relocation record. Unfortunately there's no easy way to test for the
+    // presence of N64 ELFs as they have no special flag that identifies them
+    // as being N64. We can safely assume at the moment that all Mips
+    // ELFCLASS64 ELFs are N64. New Mips64 ABIs should provide enough
+    // information to disambiguate between old vs new ABIs.
     uint8_t Type1 = (Type >> 0) & 0xFF;
     uint8_t Type2 = (Type >> 8) & 0xFF;
     uint8_t Type3 = (Type >> 16) & 0xFF;
 
     // Concat all three relocation type names.
     StringRef Name = getRelocationTypeName(Type1);
     Result.append(Name.begin(), Name.end());
 

test/MC/Mips/elf-N64.s

 // RUN: llvm-mc -filetype=obj -triple=mips64el-pc-linux -mcpu=mips64  %s -o - | llvm-readobj -r | FileCheck %s
+// RUN: llvm-mc -filetype=obj -triple=mips64-pc-linux -mcpu=mips64  %s -o - | llvm-readobj -r | FileCheck %s
 
 // Check for N64 relocation production.
 // Check that the appropriate relocations were created.
 
 // CHECK: Relocations [
 // CHECK:   0x{{[0-9,A-F]+}} R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16
 // CHECK:   0x{{[0-9,A-F]+}} R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16
 // CHECK:   0x{{[0-9,A-F]+}} R_MIPS_GOT_PAGE/R_MIPS_NONE/R_MIPS_NONE

test/MC/Mips/elf-gprel-32-64.s

 // RUN: llvm-mc -filetype=obj -triple=mips64el-pc-linux -mcpu=mips64 %s -o - \
 // RUN: | llvm-readobj -r \
 // RUN: | FileCheck %s
+// RUN: llvm-mc -filetype=obj -triple=mips64-pc-linux -mcpu=mips64 %s -o - \
+// RUN: | llvm-readobj -r \
+// RUN: | FileCheck %s
 
 // Check that the appropriate relocations were created.
 
 // R_MIPS_GPREL32/R_MIPS_64/R_MIPS_NONE
 // CHECK:      Relocations [
 // CHECK:        Section ({{[a-z0-9]+}}) .rela.rodata {
 // CHECK-NEXT:     0x{{[0-9,A-F]+}} R_MIPS_GPREL32/R_MIPS_64/R_MIPS_NONE
 // CHECK-NEXT:     0x{{[0-9,A-F]+}} R_MIPS_GPREL32/R_MIPS_64/R_MIPS_NONE