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Differential D3497

Make sure that DSUB does not duplicate the pattern of DSUBU
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Authored by rkotler on Apr 24 2014, 5:15 PM.

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dsanders
Commits
rGc04166992713: Make sure that DSUB does not duplicate the pattern of DSUBU
rL207247: Make sure that DSUB does not duplicate the pattern of DSUBU

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Event Timeline

rkotler updated this revision to Diff 8823.Apr 24 2014, 5:15 PM
rkotler retitled this revision from to Make sure that DSUB does not duplicate the pattern of DSUBU.
rkotler updated this object.
rkotler edited the test plan for this revision. (Show Details)
rkotler added a reviewer: dsanders.
dsanders accepted this revision.Apr 25 2014, 1:49 AM
dsanders edited edge metadata.

LGTM.

The testcase is that D3498 successfully generates the MipsGenFastISel.inc

This revision is now accepted and ready to land.Apr 25 2014, 1:49 AM
rkotler closed this revision.Apr 25 2014, 11:11 AM

Revision Contents

PathSize
lib/
Target/
Mips/
2 lines

Diff 8823

lib/Target/Mips/Mips64InstrInfo.td

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} }
/// Arithmetic Instructions (3-Operand, R-Type) /// Arithmetic Instructions (3-Operand, R-Type)
def DADD : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>; def DADD : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>;
def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>, def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>,
ADD_FM<0, 0x2d>; ADD_FM<0, 0x2d>;
def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>,
ADD_FM<0, 0x2f>; ADD_FM<0, 0x2f>;
def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB, sub>, ADD_FM<0, 0x2e>; def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>;
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>; def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>; def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>;
def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>; def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>;
def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>; def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>;
def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>; def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>;
def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>; def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>;
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