ARM64: start porting regression tests from AArch64

[t.p.northover]

Summary

Hi all,

This is the start of my work to make sure all AArch64 regression tests pass on the ARM64 backend as well.

In the end, I decided that it would be best to modify the existing AArch64 tests rather than create duplicates in the ARM64 directory.

This has the advantage that they're guaranteed to stay in sync: if someone adds a new feature to AArch64 that isn't in ARM64, the test will start failing and some action must be taken. I suggest adding the feature if possible, or creating bugzilla report if necessary and putting a hack in the test.

The disadvantage is that anyone building Clang with *just* AArch64 enabled (not ARM64) will get less test coverage (none of lib/CodeGen/AArch64 will run for that compiler). This is a fairly large disadvantage in those situations, so I'd understand if this is unacceptable to some users.

What's the feeling on this approach?

Cheers.

Tim.

[Jiangning]

Hi Tim,

I'm OK with this basic method.

Shouldn't changing 'or' to 'and' in lit config just work? I think you just
want to say we need to run the test under AArch64 for both AArch64 and
ARM64, right?

Thanks,
-Jiangning

test/CodeGen/AArch64/128bit_load_store.ll

-; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=neon | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=neon| FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=neon | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64
 
 define void @test_store_f128(fp128* %ptr, fp128 %val) #0 {
-; CHECK: test_store_f128
+; CHECK-LABEL: test_store_f128
 ; CHECK: str   {{q[0-9]+}}, [{{x[0-9]+}}]
 entry:
   store fp128 %val, fp128* %ptr, align 16
   ret void
 }
 
 define fp128 @test_load_f128(fp128* readonly %ptr) #2 {
-; CHECK: test_load_f128
+; CHECK-LABEL: test_load_f128
 ; CHECK: ldr   {{q[0-9]+}}, [{{x[0-9]+}}]
 entry:
   %0 = load fp128* %ptr, align 16
   ret fp128 %0
 }
 
 define void @test_vstrq_p128(i128* %ptr, i128 %val) #0 {
-; CHECK: test_vstrq_p128
-; CHECK: str  {{x[0-9]+}}, [{{x[0-9]+}}, #8]
-; CHECK-NEXT: str  {{x[0-9]+}}, [{{x[0-9]+}}]
+; CHECK-ARM64-LABEL: test_vstrq_p128
+; CHECK-ARM64: stp {{x[0-9]+}}, {{x[0-9]+}}, [{{x[0-9]+}}]
+
+; CHECK-AARCH64-LABEL: test_vstrq_p128
+; CHECK-AARCH64: str {{x[0-9]+}}, [{{x[0-9]+}}, #8]
+; CHECK-AARCH64: str {{x[0-9]+}}, [{{x[0-9]+}}]
 entry:
   %0 = bitcast i128* %ptr to fp128*
   %1 = bitcast i128 %val to fp128
   store fp128 %1, fp128* %0, align 16
   ret void
 }
 
 define i128 @test_vldrq_p128(i128* readonly %ptr) #2 {
-; CHECK: test_vldrq_p128
-; CHECK: ldr  {{x[0-9]+}}, [{{x[0-9]+}}]
-; CHECK-NEXT: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #8]
+; CHECK-ARM64-LABEL: test_vldrq_p128
+; CHECK-ARM64: ldp {{x[0-9]+}}, {{x[0-9]+}}, [{{x[0-9]+}}]
+
+; CHECK-AARCH64-LABEL: test_vldrq_p128
+; CHECK-AARCH64: ldr {{x[0-9]+}}, [{{x[0-9]+}}]
+; CHECK-AARCH64: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #8]
 entry:
   %0 = bitcast i128* %ptr to fp128*
   %1 = load fp128* %0, align 16
   %2 = bitcast fp128 %1 to i128
   ret i128 %2
 }
 
 define void @test_ld_st_p128(i128* nocapture %ptr) #0 {
-; CHECK: test_ld_st_p128
+; CHECK-LABEL: test_ld_st_p128
 ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}]
 ; CHECK-NEXT: str {{q[0-9]+}}, [{{x[0-9]+}}, #16]
 entry:
   %0 = bitcast i128* %ptr to fp128*
   %1 = load fp128* %0, align 16
   %add.ptr = getelementptr inbounds i128* %ptr, i64 1
   %2 = bitcast i128* %add.ptr to fp128*
   store fp128 %1, fp128* %2, align 16
   ret void
 }
 

test/CodeGen/AArch64/adc.ll

 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck --check-prefix=CHECK --check-prefix=CHECK-LE %s
 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64_be-none-linux-gnu | FileCheck --check-prefix=CHECK --check-prefix=CHECK-BE %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=arm64 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-LE %s
 
 define i128 @test_simple(i128 %a, i128 %b, i128 %c) {
 ; CHECK-LABEL: test_simple:
 
   %valadd = add i128 %a, %b
 ; CHECK-LE: adds [[ADDLO:x[0-9]+]], x0, x2
 ; CHECK-LE-NEXT: adcs [[ADDHI:x[0-9]+]], x1, x3
 ; CHECK-BE: adds [[ADDLO:x[0-9]+]], x1, x3

test/CodeGen/AArch64/addsub.ll

-; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-linux-gnu | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -march=arm64 | FileCheck %s
 
 ; Note that this should be refactored (for efficiency if nothing else)
 ; when the PCS is implemented so we don't have to worry about the
 ; loads and stores.
 
 @var_i32 = global i32 42
 @var_i64 = global i64 0
 
; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #52
 
   ret void
 }
 
 ; Add 12-bit immediates, shifted left by 12 bits
 define void @add_med() {
 ; CHECK-LABEL: add_med:
 
-; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #3567, lsl #12
+; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{#3567, lsl #12|#14610432}}
   %val32 = load i32* @var_i32
   %newval32 = add i32 %val32, 14610432 ; =0xdef000
   store i32 %newval32, i32* @var_i32
 
-; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #4095, lsl #12
+; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{#4095, lsl #12|#16773120}}
   %val64 = load i64* @var_i64
   %newval64 = add i64 %val64, 16773120 ; =0xfff000
   store i64 %newval64, i64* @var_i64
 
   ret void
 }
 
 ; Subtract 12-bit immediates
; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, #52
 
   ret void
 }
 
 ; Subtract 12-bit immediates, shifted left by 12 bits
 define void @sub_med() {
 ; CHECK-LABEL: sub_med:
 
-; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #3567, lsl #12
+; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{#3567, lsl #12|#14610432}}
   %val32 = load i32* @var_i32
   %newval32 = sub i32 %val32, 14610432 ; =0xdef000
   store i32 %newval32, i32* @var_i32
 
-; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, #4095, lsl #12
+; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{#4095, lsl #12|#16773120}}
   %val64 = load i64* @var_i64
   %newval64 = sub i64 %val64, 16773120 ; =0xfff000
   store i64 %newval64, i64* @var_i64
 
   ret void
 }
 
 define void @testing() {
 ; CHECK-LABEL: testing:
   %val = load i32* @var_i32
 
 ; CHECK: cmp {{w[0-9]+}}, #4095
 ; CHECK: b.ne .LBB4_6
   %cmp_pos_small = icmp ne i32 %val, 4095
   br i1 %cmp_pos_small, label %ret, label %test2
 
 test2:
-; CHECK: cmp {{w[0-9]+}}, #3567, lsl #12
-; CHECK: b.lo .LBB4_6
+; CHECK: cmp {{w[0-9]+}}, {{#3567, lsl #12|#14610432}}
+; CHECK: b.{{cc|lo}} .LBB4_6
   %newval2 = add i32 %val, 1
   store i32 %newval2, i32* @var_i32
   %cmp_pos_big = icmp ult i32 %val, 14610432
   br i1 %cmp_pos_big, label %ret, label %test3
 
 test3:
 ; CHECK: cmp {{w[0-9]+}}, #123
 ; CHECK: b.lt .LBB4_6

test/CodeGen/AArch64/lit.local.cfg

 targets = set(config.root.targets_to_build.split())
-if not 'AArch64' in targets:
+if 'AArch64' not in targets or 'ARM64' not in targets:
     config.unsupported = True