[SystemZ] Add floating-point test data class instructions.

[• koriakin]

Summary

These are not used by CodeGen yet - ISD combiners creating the new node
will come in subsequent patches.

[uweigand]

See inline comment. Also, it might be good to add some tests to insns-bad.s as well.

Otherwise LGTM.

lib/Target/SystemZ/SystemZInstrFormats.td

1963

Please add a comment about the new "Test" category above where the other categories (like Unary etc.) are documented.

[uweigand]

LGTM, thanks!

lib/Target/SystemZ/SystemZISelLowering.h

enum NodeType : unsigned {
 
   // Byte swapping store.
   //
   // Operand 0: the value to store
   // Operand 1: the address to store to
   // Operand 2: the type of store (i16, i32, i64)
   STRV,
 
+  // Test Data Class.
+  //
+  // Operand 0: the value to test
+  // Operand 1: the bit mask
+  TDC,
+
   // Prefetch from the second operand using the 4-bit control code in
   // the first operand.  The code is 1 for a load prefetch and 2 for
   // a store prefetch.
   PREFETCH
 };
 
 // Return true if OPCODE is some kind of PC-relative address.
 inline bool isPCREL(unsigned Opcode) {

lib/Target/SystemZ/SystemZISelLowering.cpp

switch ((SystemZISD::NodeType)Opcode) {
     OPCODE(ATOMIC_LOADW_NAND);
     OPCODE(ATOMIC_LOADW_MIN);
     OPCODE(ATOMIC_LOADW_MAX);
     OPCODE(ATOMIC_LOADW_UMIN);
     OPCODE(ATOMIC_LOADW_UMAX);
     OPCODE(ATOMIC_CMP_SWAPW);
     OPCODE(LRV);
     OPCODE(STRV);
+    OPCODE(TDC);
     OPCODE(PREFETCH);
   }
   return nullptr;
 #undef OPCODE
 }
 
 // Return true if VT is a vector whose elements are a whole number of bytes
 // in width.

lib/Target/SystemZ/SystemZInstrFP.td

let Defs = [CC], CCValues = 0xF in {
   def CEBR : CompareRRE<"ceb", 0xB309, z_fcmp, FP32,  FP32>;
   def CDBR : CompareRRE<"cdb", 0xB319, z_fcmp, FP64,  FP64>;
   def CXBR : CompareRRE<"cxb", 0xB349, z_fcmp, FP128, FP128>;
 
   def CEB : CompareRXE<"ceb", 0xED09, z_fcmp, FP32, load, 4>;
   def CDB : CompareRXE<"cdb", 0xED19, z_fcmp, FP64, load, 8>;
 }
 
+// Test Data Class.
+let Defs = [CC], CCValues = 0xC in {
+  def TCEB : TestRXE<"tceb", 0xED10, z_tdc, FP32>;
+  def TCDB : TestRXE<"tcdb", 0xED11, z_tdc, FP64>;
+  def TCXB : TestRXE<"tcxb", 0xED12, z_tdc, FP128>;
+}
+
 //===----------------------------------------------------------------------===//
 // Peepholes
 //===----------------------------------------------------------------------===//
 
 def : Pat<(f32  fpimmneg0), (LCDFR_32 (LZER))>;
 def : Pat<(f64  fpimmneg0), (LCDFR (LZDR))>;
 def : Pat<(f128 fpimmneg0), (LCXBR (LZXR))>;

lib/Target/SystemZ/SystemZInstrFormats.td

 //
 //   StoreBinary:
 //     One address operand and two other input operands.  The instruction
 //     stores to the address.
 //
 //   Compare:
 //     Two input operands and an implicit CC output operand.
 //
+//   Test:
+//     Two input operands and an implicit CC output operand.  The second
+//     input operand is an "address" operand used as a test class mask.
+//
 //   Ternary:
 //     One register output operand and three input operands.
 //
 //   Quaternary:
 //     One register output operand and four input operands.
 //
 //   LoadAndOp:
 //     One output operand and two input operands, one of which is an address.
: InstVRRa<opcode, (outs), (ins tr.op:$V1, tr.op:$V2),
              mnemonic#"\t$V1, $V2",
              [(operator (tr.vt tr.op:$V1), (tr.vt tr.op:$V2))]> {
   let isCompare = 1;
   let M3 = type;
   let M4 = 0;
   let M5 = 0;
 }
 
+class TestRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
+              RegisterOperand cls>
+  : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
+            mnemonic#"\t$R1, $XBD2",
+            [(operator cls:$R1, bdxaddr12only:$XBD2)]> {
+  let M3 = 0;
+}
+
 class TernaryRRD<string mnemonic, bits<16> opcode,
                  SDPatternOperator operator, RegisterOperand cls>
   : InstRRD<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, cls:$R2),
             mnemonic#"r\t$R1, $R3, $R2",
             [(set cls:$R1, (operator cls:$R1src, cls:$R3, cls:$R2))]> {
   let OpKey = mnemonic ## cls;
   let OpType = "reg";
   let Constraints = "$R1 = $R1src";

lib/Target/SystemZ/SystemZOperators.td

def SDT_ZVecTernaryInt      : SDTypeProfile<1, 3,
                                              SDTCisSameAs<0, 2>,
                                              SDTCisVT<3, i32>]>;
 def SDT_ZVecQuaternaryInt   : SDTypeProfile<1, 4,
                                             [SDTCisVec<0>,
                                              SDTCisSameAs<0, 1>,
                                              SDTCisSameAs<0, 2>,
                                              SDTCisSameAs<0, 3>,
                                              SDTCisVT<4, i32>]>;
+def SDT_ZTest               : SDTypeProfile<0, 2, [SDTCisVT<1, i64>]>;
 
 //===----------------------------------------------------------------------===//
 // Node definitions
 //===----------------------------------------------------------------------===//
 
 // These are target-independent nodes, but have target-specific formats.
 def callseq_start       : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart,
                                  [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;

 def z_membarrier        : SDNode<"SystemZISD::MEMBARRIER", SDTNone,
                                  [SDNPHasChain, SDNPSideEffect]>;
 
 def z_loadbswap        : SDNode<"SystemZISD::LRV", SDT_ZLoadBSwap,
                                  [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def z_storebswap       : SDNode<"SystemZISD::STRV", SDT_ZStoreBSwap,
                                  [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 
+def z_tdc               : SDNode<"SystemZISD::TDC", SDT_ZTest, [SDNPOutGlue]>;
+
 // Defined because the index is an i32 rather than a pointer.
 def z_vector_insert     : SDNode<"ISD::INSERT_VECTOR_ELT",
                                  SDT_ZInsertVectorElt>;
 def z_vector_extract    : SDNode<"ISD::EXTRACT_VECTOR_ELT",
                                  SDT_ZExtractVectorElt>;
 def z_byte_mask         : SDNode<"SystemZISD::BYTE_MASK", SDT_ZReplicate>;
 def z_rotate_mask       : SDNode<"SystemZISD::ROTATE_MASK", SDT_ZRotateMask>;
 def z_replicate         : SDNode<"SystemZISD::REPLICATE", SDT_ZReplicate>;

test/MC/Disassembler/SystemZ/insns.txt

 0xe5 0x61 0xf0 0x00 0x00 0x2a
 
 # CHECK: tbeginc 4095(%r1), 42
 0xe5 0x61 0x1f 0xff 0x00 0x2a
 
 # CHECK: tbeginc 4095(%r15), 42
 0xe5 0x61 0xff 0xff 0x00 0x2a
 
+# CHECK: tcdb %f0, 0
+0xed 0x00 0x00 0x00 0x00 0x11
+
+# CHECK: tcdb %f0, 4095
+0xed 0x00 0x0f 0xff 0x00 0x11
+
+# CHECK: tcdb %f0, 0(%r1)
+0xed 0x00 0x10 0x00 0x00 0x11
+
+# CHECK: tcdb %f0, 0(%r15)
+0xed 0x00 0xf0 0x00 0x00 0x11
+
+# CHECK: tcdb %f0, 4095(%r1,%r15)
+0xed 0x01 0xff 0xff 0x00 0x11
+
+# CHECK: tcdb %f0, 4095(%r15,%r1)
+0xed 0x0f 0x1f 0xff 0x00 0x11
+
+# CHECK: tcdb %f15, 0
+0xed 0xf0 0x00 0x00 0x00 0x11
+
+# CHECK: tceb %f0, 0
+0xed 0x00 0x00 0x00 0x00 0x10
+
+# CHECK: tceb %f0, 4095
+0xed 0x00 0x0f 0xff 0x00 0x10
+
+# CHECK: tceb %f0, 0(%r1)
+0xed 0x00 0x10 0x00 0x00 0x10
+
+# CHECK: tceb %f0, 0(%r15)
+0xed 0x00 0xf0 0x00 0x00 0x10
+
+# CHECK: tceb %f0, 4095(%r1,%r15)
+0xed 0x01 0xff 0xff 0x00 0x10
+
+# CHECK: tceb %f0, 4095(%r15,%r1)
+0xed 0x0f 0x1f 0xff 0x00 0x10
+
+# CHECK: tceb %f15, 0
+0xed 0xf0 0x00 0x00 0x00 0x10
+
+# CHECK: tcxb %f0, 0
+0xed 0x00 0x00 0x00 0x00 0x12
+
+# CHECK: tcxb %f0, 4095
+0xed 0x00 0x0f 0xff 0x00 0x12
+
+# CHECK: tcxb %f0, 0(%r1)
+0xed 0x00 0x10 0x00 0x00 0x12
+
+# CHECK: tcxb %f0, 0(%r15)
+0xed 0x00 0xf0 0x00 0x00 0x12
+
+# CHECK: tcxb %f0, 4095(%r1,%r15)
+0xed 0x01 0xff 0xff 0x00 0x12
+
+# CHECK: tcxb %f0, 4095(%r15,%r1)
+0xed 0x0f 0x1f 0xff 0x00 0x12
+
+# CHECK: tcxb %f13, 0
+0xed 0xd0 0x00 0x00 0x00 0x12
+
 # CHECK: tend
 0xb2 0xf8 0x00 0x00
 
 # CHECK: tm 0, 0
 0x91 0x00 0x00 0x00
 
 # CHECK: tm 4095, 0
 0x91 0x00 0x0f 0xff

test/MC/SystemZ/insn-bad.s

 #CHECK: sy  %r0, -524289
 #CHECK: error: invalid operand
 #CHECK: sy  %r0, 524288
 
   sy  %r0, -524289
   sy  %r0, 524288
 
 #CHECK: error: invalid operand
+#CHECK: tcdb  %f0, -1
+#CHECK: error: invalid operand
+#CHECK: tcdb  %f0, 4096
+
+  tcdb  %f0, -1
+  tcdb  %f0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: tceb  %f0, -1
+#CHECK: error: invalid operand
+#CHECK: tceb  %f0, 4096
+
+  tceb  %f0, -1
+  tceb  %f0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: tcxb  %f0, -1
+#CHECK: error: invalid operand
+#CHECK: tcxb  %f0, 4096
+
+  tcxb  %f0, -1
+  tcxb  %f0, 4096
+
+#CHECK: error: invalid operand
 #CHECK: tm  -1, 0
 #CHECK: error: invalid operand
 #CHECK: tm  4096, 0
 #CHECK: error: invalid use of indexed addressing
 #CHECK: tm  0(%r1,%r2), 0
 #CHECK: error: invalid operand
 #CHECK: tm  0, -1
 #CHECK: error: invalid operand

test/MC/SystemZ/insn-good.s

#CHECK: sy  %r15, 0                 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x5b]
   sy  %r0, 1
   sy  %r0, 524287
   sy  %r0, 0(%r1)
   sy  %r0, 0(%r15)
   sy  %r0, 524287(%r1,%r15)
   sy  %r0, 524287(%r15,%r1)
   sy  %r15, 0
 
+#CHECK: tcdb  %f0, 0                  # encoding: [0xed,0x00,0x00,0x00,0x00,0x11]
+#CHECK: tcdb  %f0, 4095               # encoding: [0xed,0x00,0x0f,0xff,0x00,0x11]
+#CHECK: tcdb  %f0, 0(%r1)             # encoding: [0xed,0x00,0x10,0x00,0x00,0x11]
+#CHECK: tcdb  %f0, 0(%r15)            # encoding: [0xed,0x00,0xf0,0x00,0x00,0x11]
+#CHECK: tcdb  %f0, 4095(%r1,%r15)     # encoding: [0xed,0x01,0xff,0xff,0x00,0x11]
+#CHECK: tcdb  %f0, 4095(%r15,%r1)     # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x11]
+#CHECK: tcdb  %f15, 0                 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x11]
+
+  tcdb  %f0, 0
+  tcdb  %f0, 4095
+  tcdb  %f0, 0(%r1)
+  tcdb  %f0, 0(%r15)
+  tcdb  %f0, 4095(%r1,%r15)
+  tcdb  %f0, 4095(%r15,%r1)
+  tcdb  %f15, 0
+
+#CHECK: tceb  %f0, 0                  # encoding: [0xed,0x00,0x00,0x00,0x00,0x10]
+#CHECK: tceb  %f0, 4095               # encoding: [0xed,0x00,0x0f,0xff,0x00,0x10]
+#CHECK: tceb  %f0, 0(%r1)             # encoding: [0xed,0x00,0x10,0x00,0x00,0x10]
+#CHECK: tceb  %f0, 0(%r15)            # encoding: [0xed,0x00,0xf0,0x00,0x00,0x10]
+#CHECK: tceb  %f0, 4095(%r1,%r15)     # encoding: [0xed,0x01,0xff,0xff,0x00,0x10]
+#CHECK: tceb  %f0, 4095(%r15,%r1)     # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x10]
+#CHECK: tceb  %f15, 0                 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x10]
+
+  tceb  %f0, 0
+  tceb  %f0, 4095
+  tceb  %f0, 0(%r1)
+  tceb  %f0, 0(%r15)
+  tceb  %f0, 4095(%r1,%r15)
+  tceb  %f0, 4095(%r15,%r1)
+  tceb  %f15, 0
+
+#CHECK: tcxb  %f0, 0                  # encoding: [0xed,0x00,0x00,0x00,0x00,0x12]
+#CHECK: tcxb  %f0, 4095               # encoding: [0xed,0x00,0x0f,0xff,0x00,0x12]
+#CHECK: tcxb  %f0, 0(%r1)             # encoding: [0xed,0x00,0x10,0x00,0x00,0x12]
+#CHECK: tcxb  %f0, 0(%r15)            # encoding: [0xed,0x00,0xf0,0x00,0x00,0x12]
+#CHECK: tcxb  %f0, 4095(%r1,%r15)     # encoding: [0xed,0x01,0xff,0xff,0x00,0x12]
+#CHECK: tcxb  %f0, 4095(%r15,%r1)     # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x12]
+#CHECK: tcxb  %f13, 0                 # encoding: [0xed,0xd0,0x00,0x00,0x00,0x12]
+
+  tcxb  %f0, 0
+  tcxb  %f0, 4095
+  tcxb  %f0, 0(%r1)
+  tcxb  %f0, 0(%r15)
+  tcxb  %f0, 4095(%r1,%r15)
+  tcxb  %f0, 4095(%r15,%r1)
+  tcxb  %f13, 0
+
 #CHECK: tm  0, 0                    # encoding: [0x91,0x00,0x00,0x00]
 #CHECK: tm  4095, 0                 # encoding: [0x91,0x00,0x0f,0xff]
 #CHECK: tm  0, 255                  # encoding: [0x91,0xff,0x00,0x00]
 #CHECK: tm  0(%r1), 42              # encoding: [0x91,0x2a,0x10,0x00]
 #CHECK: tm  0(%r15), 42             # encoding: [0x91,0x2a,0xf0,0x00]
 #CHECK: tm  4095(%r1), 42           # encoding: [0x91,0x2a,0x1f,0xff]
 #CHECK: tm  4095(%r15), 42          # encoding: [0x91,0x2a,0xff,0xff]