[SystemZ] Avoid generating 2 XOR instructions for (and (xor x, -1), y)

[assem]

Summary

Created a pattern to match 64-bit mode (and (xor x, -1), y) to a shorter sequence of instructions.

Before the change, the canonical form is translated to:

xihf    %r3, 4294967295
xilf    %r3, 4294967295
ngr     %r2, %r3

After the change, the canonical form is translated to:

ngr     %r3, %r2
xgr     %r2, %r3

[uweigand]

LGTM, thanks!

llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td

def : Pat<(sra (shl (i32 (z_select_ccmask 1, 0, imm32zx4:$valid, imm32zx4:$cc)),
                     (i32 31)),
           (Select32 (LHI -1), (LHI 0), imm32zx4:$valid, imm32zx4:$cc)>;
 def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, imm32zx4:$valid,
                                                        imm32zx4:$cc)))),
                     (i32 63)),
                (i32 63)),
           (Select64 (LGHI -1), (LGHI 0), imm32zx4:$valid, imm32zx4:$cc)>;
 
+// Avoid generating 2 XOR instructions. (xor (and x, y), y) is
+// equivalent to (and (xor x, -1), y)
+def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y),
+                          (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>;
+
 // Peepholes for turning scalar operations into block operations.
 defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence,
                       XCSequence, 1>;
 defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence,
                       XCSequence, 2>;
 defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence,
                       XCSequence, 4>;
 defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence,
                       OCSequence, XCSequence, 1>;
 defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence,
                       XCSequence, 2>;
 defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence,
                       XCSequence, 4>;
 defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence,
                       XCSequence, 8>;

llvm/trunk/test/CodeGen/SystemZ/and-xor-01.ll

+; Testing peephole for generating shorter code for (and (xor b, -1), a)
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+define i64 @f1(i64 %a, i64 %b) {
+; CHECK-LABEL: f1:
+; CHECK: ngr %r3, %r2
+; CHECK: xgr %r2, %r3
+; CHECK: br %r14
+  %neg = xor i64 %b, -1
+  %and = and i64 %neg, %a
+  ret i64 %and
+}
+