Enable index register memory constraints for inline ASM operands on SystemZ

[colpell]

Summary

This enables use of the 'R' and 'T' memory constraints for inline ASM operands on SystemZ, which allow an index register as well as an immediate displacement. This patch includes corresponding documentation and test case updates.

As with the last patch of this kind, I moved the 'm' constraint to the most general case, which is now 'T' (base + 20-bit signed displacement + index register).

[uweigand]

There's a typo in the documentation change, see inline annotations. Otherwise, LGTM.

docs/LangRef.rst

3598 ↗

(On Diff #60390)

The 20-bit immediates are *signed*, not unsigned like the 12-bit ones.

3600 ↗

(On Diff #60390)

Likewise.

[colpell]

Fix documentation typo (unsigned -> signed).

llvm/trunk/docs/LangRef.rst

 
 SystemZ:
 
 - ``I``: An immediate unsigned 8-bit integer.
 - ``J``: An immediate unsigned 12-bit integer.
 - ``K``: An immediate signed 16-bit integer.
 - ``L``: An immediate signed 20-bit integer.
 - ``M``: An immediate integer 0x7fffffff.
-- ``Q``, ``R``: A memory address operand with a base address and a 12-bit
-  immediate unsigned displacement.
-- ``S``, ``T``: A memory address operand with a base address and a 20-bit
-  immediate signed displacement.
+- ``Q``: A memory address operand with a base address and a 12-bit immediate
+  unsigned displacement.
+- ``R``: A memory address operand with a base address, a 12-bit immediate
+  unsigned displacement, and an index register.
+- ``S``: A memory address operand with a base address and a 20-bit immediate
+  signed displacement.
+- ``T``: A memory address operand with a base address, a 20-bit immediate
+  signed displacement, and an index register.
 - ``r`` or ``d``: A 32, 64, or 128-bit integer register.
 - ``a``: A 32, 64, or 128-bit integer address register (excludes R0, which in an
   address context evaluates as zero).
 - ``h``: A 32-bit value in the high part of a 64bit data register
   (LLVM-specific)
 - ``f``: A 32, 64, or 128-bit floating point register.
 
 X86:

llvm/trunk/lib/Target/SystemZ/README.txt

 //===---------------------------------------------------------------------===//
 // Random notes about and ideas for the SystemZ backend.
 //===---------------------------------------------------------------------===//
 
 The initial backend is deliberately restricted to z10.  We should add support
 for later architectures at some point.
 
 --
 
-SystemZDAGToDAGISel::SelectInlineAsmMemoryOperand() treats the Q and R
-constraints the same, and the S and T constraints the same, because the optional
-index is not used.
-
---
-
 If an inline asm ties an i32 "r" result to an i64 input, the input
 will be treated as an i32, leaving the upper bits uninitialised.
 For example:
 
 define void @f4(i32 *%dst) {
   %val = call i32 asm "blah $0", "=r,0" (i64 103)
   store i32 %val, i32 *%dst
   ret void

llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp

void SystemZDAGToDAGISel::Select(SDNode *Node) {
 
   SelectCode(Node);
 }
 
 bool SystemZDAGToDAGISel::
 SelectInlineAsmMemoryOperand(const SDValue &Op,
                              unsigned ConstraintID,
                              std::vector<SDValue> &OutOps) {
+  SystemZAddressingMode::AddrForm Form;
+  SystemZAddressingMode::DispRange DispRange;
   SDValue Base, Disp, Index;
 
   switch(ConstraintID) {
   default:
     llvm_unreachable("Unexpected asm memory constraint");
   case InlineAsm::Constraint_i:
   case InlineAsm::Constraint_Q:
+    // Accept an address with a short displacement, but no index.
+    Form = SystemZAddressingMode::FormBD;
+    DispRange = SystemZAddressingMode::Disp12Only;
+    break;
   case InlineAsm::Constraint_R:
-    // Accept addresses with short displacements, which are compatible
-    // with Q and R. But keep the index operand for future expansion (e.g. the
-    // index for R).
-    if (selectBDXAddr(SystemZAddressingMode::FormBD,
-                      SystemZAddressingMode::Disp12Only,
-                      Op, Base, Disp, Index)) {
-      OutOps.push_back(Base);
-      OutOps.push_back(Disp);
-      OutOps.push_back(Index);
-      return false;
-    }
+    // Accept an address with a short displacement and an index.
+    Form = SystemZAddressingMode::FormBDXNormal;
+    DispRange = SystemZAddressingMode::Disp12Only;
     break;
   case InlineAsm::Constraint_S:
+    // Accept an address with a long displacement, but no index.
+    Form = SystemZAddressingMode::FormBD;
+    DispRange = SystemZAddressingMode::Disp20Only;
+    break;
   case InlineAsm::Constraint_T:
   case InlineAsm::Constraint_m:
-    // Accept addresses with long displacements. As above, keep the index for
-    // future implementation of index for the T constraint.
-    if (selectBDXAddr(SystemZAddressingMode::FormBD,
-                      SystemZAddressingMode::Disp20Only,
-                      Op, Base, Disp, Index)) {
-      OutOps.push_back(Base);
-      OutOps.push_back(Disp);
-      OutOps.push_back(Index);
-      return false;
-    }
-    break;
-  }
+    // Accept an address with a long displacement and an index.
+    // m works the same as T, as this is the most general case.
+    Form = SystemZAddressingMode::FormBDXNormal;
+    DispRange = SystemZAddressingMode::Disp20Only;
+    break;
+  }
+
+  if (selectBDXAddr(Form, DispRange, Op, Base, Disp, Index)) {
+
   return true;
 }

llvm/trunk/test/CodeGen/SystemZ/asm-02.ll

 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
   %add = add i64 %base, 4096
   %addr = inttoptr i64 %add to i64 *
   call void asm "blah $0", "=*R" (i64 *%addr)
   ret void
 }
 
-; FIXME: at the moment the precise constraint is not passed down to
-; target code, so we must conservatively treat "R" as "Q".
+; Check that indices are allowed
+define void @f5(i64 %base, i64 %index) {
+; CHECK-LABEL: f5:
+; CHECK: blah 0(%r3,%r2)
+; CHECK: br %r14
+  %add = add i64 %base, %index
+  %addr = inttoptr i64 %add to i64 *
+  call void asm "blah $0", "=*R" (i64 *%addr)
+  ret void
+}
+
+; Check that indices and displacements are allowed simultaneously
+define void @f6(i64 %base, i64 %index) {
+; CHECK-LABEL: f6:
+; CHECK: blah 4095(%r3,%r2)
+; CHECK: br %r14
+  %add = add i64 %base, 4095
+  %addi = add i64 %add, %index
+  %addr = inttoptr i64 %addi to i64 *
+  call void asm "blah $0", "=*R" (i64 *%addr)
+  ret void
+}
+
+; Check that LAY is used if there is an index but the displacement is too large
+define void @f7(i64 %base, i64 %index) {
+; CHECK-LABEL: f7:
+; CHECK: lay %r0, 4096(%r3,%r2)
+; CHECK: blah 0(%r0)
+; CHECK: br %r14
+  %add = add i64 %base, 4096
+  %addi = add i64 %add, %index
+  %addr = inttoptr i64 %addi to i64 *
+  call void asm "blah $0", "=*R" (i64 *%addr)
+  ret void
+}

llvm/trunk/test/CodeGen/SystemZ/asm-04.ll

 ; Test the "T" asm constraint, which accepts addresses that have a base,
 ; an index and a 20-bit displacement.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as | FileCheck %s
 
+; Check the lowest range.
 define void @f1(i64 %base) {
 ; CHECK-LABEL: f1:
+; CHECK: blah -524288(%r2)
+; CHECK: br %r14
+  %add = add i64 %base, -524288
+  %addr = inttoptr i64 %add to i64 *
+  call void asm "blah $0", "=*T" (i64 *%addr)
+  ret void
+}
+
+; Check the next lowest byte.
+define void @f2(i64 %base) {
+; CHECK-LABEL: f2:
+; CHECK: agfi %r2, -524289
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
-  %addr = inttoptr i64 %base to i64 *
+  %add = add i64 %base, -524289
+  %addr = inttoptr i64 %add to i64 *
   call void asm "blah $0", "=*T" (i64 *%addr)
   ret void
 }
 
-; FIXME: at the moment the precise constraint is not passed down to
-; target code, so we must conservatively treat "T" as "S".
+; Check the highest range.
+define void @f3(i64 %base) {
+; CHECK-LABEL: f3:
+; CHECK: blah 524287(%r2)
+; CHECK: br %r14
+  %add = add i64 %base, 524287
+  %addr = inttoptr i64 %add to i64 *
+  call void asm "blah $0", "=*T" (i64 *%addr)
+  ret void
+}
+
+; Check the next highest byte.
+define void @f4(i64 %base) {
+; CHECK-LABEL: f4:
+; CHECK: agfi %r2, 524288
+; CHECK: blah 0(%r2)
+; CHECK: br %r14
+  %add = add i64 %base, 524288
+  %addr = inttoptr i64 %add to i64 *
+  call void asm "blah $0", "=*T" (i64 *%addr)
+  ret void
+}
+
+; Check that indices are allowed
+define void @f5(i64 %base, i64 %index) {
+; CHECK-LABEL: f5:
+; CHECK: blah 0(%r3,%r2)
+; CHECK: br %r14
+  %add = add i64 %base, %index
+  %addr = inttoptr i64 %add to i64 *
+  call void asm "blah $0", "=*T" (i64 *%addr)
+  ret void
+}
+
+; Check that indices and displacements are allowed simultaneously
+define void @f6(i64 %base, i64 %index) {
+; CHECK-LABEL: f6:
+; CHECK: blah 524287(%r3,%r2)
+; CHECK: br %r14
+  %add = add i64 %base, 524287
+  %addi = add i64 %add, %index
+  %addr = inttoptr i64 %addi to i64 *
+  call void asm "blah $0", "=*T" (i64 *%addr)
+  ret void
+}

llvm/trunk/test/CodeGen/SystemZ/asm-05.ll

 ; Test the "m" asm constraint, which is equivalent to "T".
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as | FileCheck %s
 
 define void @f1(i64 %base) {
 ; CHECK-LABEL: f1:
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
   %addr = inttoptr i64 %base to i64 *
   call void asm "blah $0", "=*m" (i64 *%addr)
   ret void
 }
-
-; FIXME: at the moment the precise constraint is not passed down to
-; target code, so we must conservatively treat "m" as "S".