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Differential D20620

[Clang][AVX512][Builtin] Fix palignr intrinsics header
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Authored by m_zuckerman on May 25 2016, 6:50 AM.

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Details

Reviewers

AsafBadouh
delena
igorb

Commits

rGefbf3f108ed6: [Clang][AVX512][Builtin] Fix palignr intrinsics header
rC270707: [Clang][AVX512][Builtin] Fix palignr intrinsics header
rL270707: [Clang][AVX512][Builtin] Fix palignr intrinsics header

Summary

We don't need to multiply by eight the IMM. The instruction is doing that.

Diff Detail

Repository: rL LLVM

Event Timeline

m_zuckerman updated this revision to Diff 58406.May 25 2016, 6:50 AM

m_zuckerman retitled this revision from to [Clang][AVX512][Builtin] Fix palignr intrinsics header .

m_zuckerman updated this object.

m_zuckerman added reviewers: AsafBadouh, igorb, delena.

m_zuckerman added a subscriber: cfe-commits.

LGTM

This revision is now accepted and ready to land.May 25 2016, 6:52 AM

Closed by commit rL270707: [Clang][AVX512][Builtin] Fix palignr intrinsics header (authored by mzuckerm). · Explain WhyMay 25 2016, 8:11 AM

This revision was automatically updated to reflect the committed changes.

Revision Contents

Path

Size

cfe/

trunk/

lib/

Headers/

avx512bwintrin.h

6 lines

Diff 58425

cfe/trunk/lib/Headers/avx512bwintrin.h

Show First 20 Lines • Show All 2,139 Lines • ▼ Show 20 Lines	_mm512_mask_permutexvar_epi16 (__m512i __W, __mmask32 __M, __m512i __A,
return (__m512i) __builtin_ia32_permvarhi512_mask ((__v32hi) __B,		return (__m512i) __builtin_ia32_permvarhi512_mask ((__v32hi) __B,
(__v32hi) __A,		(__v32hi) __A,
(__v32hi) __W,		(__v32hi) __W,
(__mmask32) __M);		(__mmask32) __M);
}		}

#define _mm512_alignr_epi8(A, B, N) __extension__ ({\		#define _mm512_alignr_epi8(A, B, N) __extension__ ({\
(__m512i)__builtin_ia32_palignr512_mask((__v64qi)(__m512i)(A), \		(__m512i)__builtin_ia32_palignr512_mask((__v64qi)(__m512i)(A), \
(__v64qi)(__m512i)(B), (int)(N) * 8, \		(__v64qi)(__m512i)(B), (int)(N), \
(__v64qi)_mm512_undefined_pd(), \		(__v64qi)_mm512_undefined_pd(), \
(__mmask64)-1); })		(__mmask64)-1); })

#define _mm512_mask_alignr_epi8(W, U, A, B, N) __extension__({\		#define _mm512_mask_alignr_epi8(W, U, A, B, N) __extension__({\
(__m512i)__builtin_ia32_palignr512_mask((__v64qi)(__m512i)(A), \		(__m512i)__builtin_ia32_palignr512_mask((__v64qi)(__m512i)(A), \
(__v64qi)(__m512i)(B), (int)(N) * 8, \		(__v64qi)(__m512i)(B), (int)(N), \
(__v64qi)(__m512i)(W), \		(__v64qi)(__m512i)(W), \
(__mmask64)(U)); })		(__mmask64)(U)); })

#define _mm512_maskz_alignr_epi8(U, A, B, N) __extension__({\		#define _mm512_maskz_alignr_epi8(U, A, B, N) __extension__({\
(__m512i)__builtin_ia32_palignr512_mask((__v64qi)(__m512i)(A), \		(__m512i)__builtin_ia32_palignr512_mask((__v64qi)(__m512i)(A), \
(__v64qi)(__m512i)(B), (int)(N) * 8, \		(__v64qi)(__m512i)(B), (int)(N), \
(__v64qi)_mm512_setzero_si512(), \		(__v64qi)_mm512_setzero_si512(), \
(__mmask64)(U)); })		(__mmask64)(U)); })

#define _mm512_dbsad_epu8(A, B, imm) __extension__ ({\		#define _mm512_dbsad_epu8(A, B, imm) __extension__ ({\
(__m512i)__builtin_ia32_dbpsadbw512_mask((__v64qi)(__m512i)(A), \		(__m512i)__builtin_ia32_dbpsadbw512_mask((__v64qi)(__m512i)(A), \
(__v64qi)(__m512i)(B), (int)(imm), \		(__v64qi)(__m512i)(B), (int)(imm), \
(__v32hi)_mm512_undefined_epi32(), \		(__v32hi)_mm512_undefined_epi32(), \
(__mmask32)-1); })		(__mmask32)-1); })
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