This is an archive of the discontinued LLVM Phabricator instance.

Differential D20520

[mips] Fix disassembler offset for compact branches
AbandonedPublic

Authored by sdardis on May 23 2016, 5:31 AM.

Details

Reviewers
dsanders
vkalintiris
Summary

As the MIPSR6 specification says, a 18/23-bit signed offset (the 16/21-bit
offset field shifted left 2 bits) is added to the address of the instruction
following the (compact) branch (not the branch itself), to form a PC-relative
effective target address.

Similarly for branches which take a 26bit offset

The immediate for those branches is only shifted when it should be shifted
and added.

Diff Detail

Event Timeline

sdardis updated this revision to Diff 58085.May 23 2016, 5:31 AM
sdardis retitled this revision from to [mips] Fix disassembler offset for compact branches.
sdardis updated this object.
sdardis added reviewers: dsanders, vkalintiris.
sdardis set the repository for this revision to rL LLVM.
sdardis added a subscriber: llvm-commits.
Herald added subscribers: sdardis, dsanders. · View Herald TranscriptMay 23 2016, 5:31 AM
sdardis abandoned this revision.May 24 2016, 4:42 AM

Patch already submitted for this issue.

Revision Contents

PathSize
lib/
Target/
Mips/
Disassembler/
16 lines
test/
ExecutionEngine/
RuntimeDyld/
Mips/
4 lines
4 lines
MC/
Disassembler/
Mips/
mips32r6/
52 lines
52 lines
mips64r6/
52 lines
52 lines

Diff 58085

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

Show First 20 Lines • Show All 574 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
// We have: // We have:
// 0b001000 sssss ttttt iiiiiiiiiiiiiiii // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
// BOVC if rs >= rt // BOVC if rs >= rt
// BEQZALC if rs == 0 && rt != 0 // BEQZALC if rs == 0 && rt != 0
// BEQC if rs < rt && rs != 0 // BEQC if rs < rt && rs != 0
InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rs = fieldFromInstruction(insn, 21, 5);
InsnType Rt = fieldFromInstruction(insn, 16, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5);
InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; InsnType Imm = (SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4) + 4;
bool HasRs = false; bool HasRs = false;
if (Rs >= Rt) { if (Rs >= Rt) {
MI.setOpcode(Mips::BOVC); MI.setOpcode(Mips::BOVC);
HasRs = true; HasRs = true;
} else if (Rs != 0 && Rs < Rt) { } else if (Rs != 0 && Rs < Rt) {
MI.setOpcode(Mips::BEQC); MI.setOpcode(Mips::BEQC);
HasRs = true; HasRs = true;
Show All 22 Linesstatic DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
// We have: // We have:
// 0b011000 sssss ttttt iiiiiiiiiiiiiiii // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
// BNVC if rs >= rt // BNVC if rs >= rt
// BNEZALC if rs == 0 && rt != 0 // BNEZALC if rs == 0 && rt != 0
// BNEC if rs < rt && rs != 0 // BNEC if rs < rt && rs != 0
InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rs = fieldFromInstruction(insn, 21, 5);
InsnType Rt = fieldFromInstruction(insn, 16, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5);
InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; InsnType Imm = (SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4) + 4;
bool HasRs = false; bool HasRs = false;
if (Rs >= Rt) { if (Rs >= Rt) {
MI.setOpcode(Mips::BNVC); MI.setOpcode(Mips::BNVC);
HasRs = true; HasRs = true;
} else if (Rs != 0 && Rs < Rt) { } else if (Rs != 0 && Rs < Rt) {
MI.setOpcode(Mips::BNEC); MI.setOpcode(Mips::BNEC);
HasRs = true; HasRs = true;
Show All 23 Linesstatic DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
// 0b010110 sssss ttttt iiiiiiiiiiiiiiii // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
// Invalid if rs == 0 // Invalid if rs == 0
// BLEZC if rs == 0 && rt != 0 // BLEZC if rs == 0 && rt != 0
// BGEZC if rs == rt && rt != 0 // BGEZC if rs == rt && rt != 0
// BGEC if rs != rt && rs != 0 && rt != 0 // BGEC if rs != rt && rs != 0 && rt != 0
InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rs = fieldFromInstruction(insn, 21, 5);
InsnType Rt = fieldFromInstruction(insn, 16, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5);
InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; InsnType Imm = (SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4) + 4;
bool HasRs = false; bool HasRs = false;
if (Rt == 0) if (Rt == 0)
return MCDisassembler::Fail; return MCDisassembler::Fail;
else if (Rs == 0) else if (Rs == 0)
MI.setOpcode(Mips::BLEZC); MI.setOpcode(Mips::BLEZC);
else if (Rs == Rt) else if (Rs == Rt)
MI.setOpcode(Mips::BGEZC); MI.setOpcode(Mips::BGEZC);
Show All 28 Linesstatic DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
// BGTZC if rs == 0 && rt != 0 // BGTZC if rs == 0 && rt != 0
// BLTZC if rs == rt && rt != 0 // BLTZC if rs == rt && rt != 0
// BLTC if rs != rt && rs != 0 && rt != 0 // BLTC if rs != rt && rs != 0 && rt != 0
bool HasRs = false; bool HasRs = false;
InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rs = fieldFromInstruction(insn, 21, 5);
InsnType Rt = fieldFromInstruction(insn, 16, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5);
InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; InsnType Imm = (SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4) + 4;
if (Rt == 0) if (Rt == 0)
return MCDisassembler::Fail; return MCDisassembler::Fail;
else if (Rs == 0) else if (Rs == 0)
MI.setOpcode(Mips::BGTZC); MI.setOpcode(Mips::BGTZC);
else if (Rs == Rt) else if (Rs == Rt)
MI.setOpcode(Mips::BLTZC); MI.setOpcode(Mips::BLTZC);
else { else {
Show All 25 Linesstatic DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
// 0b000111 sssss ttttt iiiiiiiiiiiiiiii // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
// BGTZ if rt == 0 // BGTZ if rt == 0
// BGTZALC if rs == 0 && rt != 0 // BGTZALC if rs == 0 && rt != 0
// BLTZALC if rs != 0 && rs == rt // BLTZALC if rs != 0 && rs == rt
// BLTUC if rs != 0 && rs != rt // BLTUC if rs != 0 && rs != rt
InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rs = fieldFromInstruction(insn, 21, 5);
InsnType Rt = fieldFromInstruction(insn, 16, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5);
InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; InsnType Imm = (SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4) + 4;
bool HasRs = false; bool HasRs = false;
bool HasRt = false; bool HasRt = false;
if (Rt == 0) { if (Rt == 0) {
MI.setOpcode(Mips::BGTZ); MI.setOpcode(Mips::BGTZ);
HasRs = true; HasRs = true;
} else if (Rs == 0) { } else if (Rs == 0) {
MI.setOpcode(Mips::BGTZALC); MI.setOpcode(Mips::BGTZALC);
Show All 32 Linesstatic DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
// 0b000110 sssss ttttt iiiiiiiiiiiiiiii // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
// Invalid if rs == 0 // Invalid if rs == 0
// BLEZALC if rs == 0 && rt != 0 // BLEZALC if rs == 0 && rt != 0
// BGEZALC if rs == rt && rt != 0 // BGEZALC if rs == rt && rt != 0
// BGEUC if rs != rt && rs != 0 && rt != 0 // BGEUC if rs != rt && rs != 0 && rt != 0
InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rs = fieldFromInstruction(insn, 21, 5);
InsnType Rt = fieldFromInstruction(insn, 16, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5);
InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; InsnType Imm = (SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4) + 4;
bool HasRs = false; bool HasRs = false;
if (Rt == 0) if (Rt == 0)
return MCDisassembler::Fail; return MCDisassembler::Fail;
else if (Rs == 0) else if (Rs == 0)
MI.setOpcode(Mips::BLEZALC); MI.setOpcode(Mips::BLEZALC);
else if (Rs == Rt) else if (Rs == Rt)
MI.setOpcode(Mips::BGEZALC); MI.setOpcode(Mips::BGEZALC);
▲ Show 20 Lines • Show All 1,048 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeJumpTarget(MCInst &Inst,
Inst.addOperand(MCOperand::createImm(JumpOffset)); Inst.addOperand(MCOperand::createImm(JumpOffset));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeBranchTarget21(MCInst &Inst, static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
unsigned Offset, unsigned Offset,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
int32_t BranchOffset = SignExtend32<21>(Offset) * 4; int32_t BranchOffset = (SignExtend32<21>(Offset) * 4) + 4;
Inst.addOperand(MCOperand::createImm(BranchOffset)); Inst.addOperand(MCOperand::createImm(BranchOffset));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst,
unsigned Offset, unsigned Offset,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
int32_t BranchOffset = SignExtend32<21>(Offset) << 1; int32_t BranchOffset = SignExtend32<21>(Offset) << 1;
Inst.addOperand(MCOperand::createImm(BranchOffset)); Inst.addOperand(MCOperand::createImm(BranchOffset));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeBranchTarget26(MCInst &Inst, static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
unsigned Offset, unsigned Offset,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
int32_t BranchOffset = SignExtend32<26>(Offset) * 4; int32_t BranchOffset = (SignExtend32<26>(Offset) * 4) + 4;
Inst.addOperand(MCOperand::createImm(BranchOffset)); Inst.addOperand(MCOperand::createImm(BranchOffset));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
unsigned Offset, unsigned Offset,
uint64_t Address, uint64_t Address,
▲ Show 20 Lines • Show All 328 Lines • Show Last 20 Lines

test/ExecutionEngine/RuntimeDyld/Mips/ELF_N64R6_relocations.s

Show All 26 LinesR_MIPS_PC18_S3:
ldpc $6,foo ldpc $6,foo
# Test R_MIPS_PC19_S2 relocation. # Test R_MIPS_PC19_S2 relocation.
# rtdyld-check: decode_operand(R_MIPS_PC19_S2, 1)[20:0] = (foo - R_MIPS_PC19_S2)[20:0] # rtdyld-check: decode_operand(R_MIPS_PC19_S2, 1)[20:0] = (foo - R_MIPS_PC19_S2)[20:0]
R_MIPS_PC19_S2: R_MIPS_PC19_S2:
lwpc $6,foo lwpc $6,foo
# Test R_MIPS_PC21_S2 relocation. # Test R_MIPS_PC21_S2 relocation.
# rtdyld-check: decode_operand(R_MIPS_PC21_S2, 1)[22:0] = (foo - next_pc(R_MIPS_PC21_S2))[22:0] # rtdyld-check: decode_operand(R_MIPS_PC21_S2, 1)[22:0] = (foo - R_MIPS_PC21_S2)[22:0]
R_MIPS_PC21_S2: R_MIPS_PC21_S2:
bnezc $5,foo bnezc $5,foo
# Test R_MIPS_PC26_S2 relocation. # Test R_MIPS_PC26_S2 relocation.
# rtdyld-check: decode_operand(R_MIPS_PC26_S2, 0)[27:0] = (foo - next_pc(R_MIPS_PC26_S2))[27:0] # rtdyld-check: decode_operand(R_MIPS_PC26_S2, 0)[27:0] = (foo - R_MIPS_PC26_S2)[27:0]
R_MIPS_PC26_S2: R_MIPS_PC26_S2:
balc foo balc foo
# Test R_MIPS_PCHI16 relocation. # Test R_MIPS_PCHI16 relocation.
# rtdyld-check: decode_operand(R_MIPS_PCHI16, 1)[15:0] = (foo - R_MIPS_PCHI16 + 0x8000)[31:16] # rtdyld-check: decode_operand(R_MIPS_PCHI16, 1)[15:0] = (foo - R_MIPS_PCHI16 + 0x8000)[31:16]
R_MIPS_PCHI16: R_MIPS_PCHI16:
aluipc $5, %pcrel_hi(foo) aluipc $5, %pcrel_hi(foo)
# Test R_MIPS_PCLO16 relocation. # Test R_MIPS_PCLO16 relocation.
# rtdyld-check: decode_operand(R_MIPS_PCLO16, 2)[15:0] = (foo - R_MIPS_PCLO16)[15:0] # rtdyld-check: decode_operand(R_MIPS_PCLO16, 2)[15:0] = (foo - R_MIPS_PCLO16)[15:0]
R_MIPS_PCLO16: R_MIPS_PCLO16:
addiu $5, $5, %pcrel_lo(foo) addiu $5, $5, %pcrel_lo(foo)
.size bar, .-bar .size bar, .-bar

test/ExecutionEngine/RuntimeDyld/Mips/ELF_O32R6_relocations.s

Show All 21 Lines
bar: bar:
# Test R_MIPS_PC19_S2 relocation. # Test R_MIPS_PC19_S2 relocation.
# rtdyld-check: decode_operand(R_MIPS_PC19_S2, 1)[20:0] = (foo - R_MIPS_PC19_S2)[20:0] # rtdyld-check: decode_operand(R_MIPS_PC19_S2, 1)[20:0] = (foo - R_MIPS_PC19_S2)[20:0]
R_MIPS_PC19_S2: R_MIPS_PC19_S2:
lwpc $6,foo lwpc $6,foo
# Test R_MIPS_PC21_S2 relocation. # Test R_MIPS_PC21_S2 relocation.
# rtdyld-check: decode_operand(R_MIPS_PC21_S2, 1)[22:0] = (foo - next_pc(R_MIPS_PC21_S2))[22:0] # rtdyld-check: decode_operand(R_MIPS_PC21_S2, 1)[22:0] = (foo - R_MIPS_PC21_S2)[22:0]
R_MIPS_PC21_S2: R_MIPS_PC21_S2:
bnezc $5,foo bnezc $5,foo
# Test R_MIPS_PC26_S2 relocation. # Test R_MIPS_PC26_S2 relocation.
# rtdyld-check: decode_operand(R_MIPS_PC26_S2, 0)[27:0] = (foo - next_pc(R_MIPS_PC26_S2))[27:0] # rtdyld-check: decode_operand(R_MIPS_PC26_S2, 0)[27:0] = (foo - R_MIPS_PC26_S2)[27:0]
R_MIPS_PC26_S2: R_MIPS_PC26_S2:
balc foo balc foo
# Test R_MIPS_PCHI16 relocation. # Test R_MIPS_PCHI16 relocation.
# rtdyld-check: decode_operand(R_MIPS_PCHI16, 1)[15:0] = (foo - R_MIPS_PCHI16 + 0x8000)[31:16] # rtdyld-check: decode_operand(R_MIPS_PCHI16, 1)[15:0] = (foo - R_MIPS_PCHI16 + 0x8000)[31:16]
R_MIPS_PCHI16: R_MIPS_PCHI16:
aluipc $5, %pcrel_hi(foo) aluipc $5, %pcrel_hi(foo)
# Test R_MIPS_PCLO16 relocation. # Test R_MIPS_PCLO16 relocation.
# rtdyld-check: decode_operand(R_MIPS_PCLO16, 2)[15:0] = (foo - R_MIPS_PCLO16)[15:0] # rtdyld-check: decode_operand(R_MIPS_PCLO16, 2)[15:0] = (foo - R_MIPS_PCLO16)[15:0]
R_MIPS_PCLO16: R_MIPS_PCLO16:
addiu $5, $5, %pcrel_lo(foo) addiu $5, $5, %pcrel_lo(foo)
.size bar, .-bar .size bar, .-bar

test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt

# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r6 | FileCheck %s # RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r6 | FileCheck %s
0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4 0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4
0x19 0x00 0x80 0xec # CHECK: addiupc $4, 100 0x19 0x00 0x80 0xec # CHECK: addiupc $4, 100
0x0a 0x00 0x29 0x25 # CHECK: addiu $9, $9, 10 0x0a 0x00 0x29 0x25 # CHECK: addiu $9, $9, 10
0xa0 0x22 0x43 0x7c # CHECK: align $4, $2, $3, 2 0xa0 0x22 0x43 0x7c # CHECK: align $4, $2, $3, 2
0x38 0x00 0x7f 0xec # CHECK: aluipc $3, 56 0x38 0x00 0x7f 0xec # CHECK: aluipc $3, 56
0xe9 0xff 0x62 0x3c # CHECK: aui $3, $2, -23 0xe9 0xff 0x62 0x3c # CHECK: aui $3, $2, -23
0xff 0xff 0x7e 0xec # CHECK: auipc $3, -1 0xff 0xff 0x7e 0xec # CHECK: auipc $3, -1
0x9b 0x14 0x11 0x04 # CHECK: bal 21104 0x9b 0x14 0x11 0x04 # CHECK: bal 21104
0xb8 0x96 0x37 0xe8 # CHECK: balc 14572256 0xb8 0x96 0x37 0xe8 # CHECK: balc 14572260
0xb8 0x96 0x37 0xc8 # CHECK: bc 14572256 0xb8 0x96 0x37 0xc8 # CHECK: bc 14572260
0x01 0x00 0x20 0x45 # CHECK: bc1eqz $f0, 8 0x01 0x00 0x20 0x45 # CHECK: bc1eqz $f0, 8
0x01 0x00 0x3f 0x45 # CHECK: bc1eqz $f31, 8 0x01 0x00 0x3f 0x45 # CHECK: bc1eqz $f31, 8
0x01 0x00 0xa0 0x45 # CHECK: bc1nez $f0, 8 0x01 0x00 0xa0 0x45 # CHECK: bc1nez $f0, 8
0x01 0x00 0xbf 0x45 # CHECK: bc1nez $f31, 8 0x01 0x00 0xbf 0x45 # CHECK: bc1nez $f31, 8
0x02 0x00 0x20 0x49 # CHECK: bc2eqz $0, 12 0x02 0x00 0x20 0x49 # CHECK: bc2eqz $0, 12
0x02 0x00 0x3f 0x49 # CHECK: bc2eqz $31, 12 0x02 0x00 0x3f 0x49 # CHECK: bc2eqz $31, 12
0x02 0x00 0xa0 0x49 # CHECK: bc2nez $0, 12 0x02 0x00 0xa0 0x49 # CHECK: bc2nez $0, 12
0x02 0x00 0xbf 0x49 # CHECK: bc2nez $31, 12 0x02 0x00 0xbf 0x49 # CHECK: bc2nez $31, 12
0x40 0x00 0xa6 0x20 # CHECK: beqc $5, $6, 256 0x40 0x00 0xa6 0x20 # CHECK: beqc $5, $6, 260
0x4d 0x01 0x02 0x20 # CHECK: beqzalc $2, 1332 0x4d 0x01 0x02 0x20 # CHECK: beqzalc $2, 1336
0x40 0x00 0xa6 0x60 # CHECK: bnec $5, $6, 256 0x40 0x00 0xa6 0x60 # CHECK: bnec $5, $6, 260
0x4d 0x01 0x02 0x60 # CHECK: bnezalc $2, 1332 0x4d 0x01 0x02 0x60 # CHECK: bnezalc $2, 1336
0x90 0x46 0xa0 0xd8 # CHECK: beqzc $5, 72256 0x90 0x46 0xa0 0xd8 # CHECK: beqzc $5, 72260
0x40 0x00 0x43 0x58 # CHECK: bgec $2, $3, 256 0x40 0x00 0x43 0x58 # CHECK: bgec $2, $3, 260
0x40 0x00 0x43 0x18 # CHECK: bgeuc $2, $3, 256 0x40 0x00 0x43 0x18 # CHECK: bgeuc $2, $3, 260
0x4d 0x01 0x42 0x18 # CHECK: bgezalc $2, 1332 0x4d 0x01 0x42 0x18 # CHECK: bgezalc $2, 1336
0x90 0x46 0xa0 0xf8 # CHECK: bnezc $5, 72256 0x90 0x46 0xa0 0xf8 # CHECK: bnezc $5, 72260
0x40 0x00 0xa5 0x5c # CHECK: bltzc $5, 256 0x40 0x00 0xa5 0x5c # CHECK: bltzc $5, 260
0x40 0x00 0xa5 0x58 # CHECK: bgezc $5, 256 0x40 0x00 0xa5 0x58 # CHECK: bgezc $5, 260
0x4d 0x01 0x02 0x1c # CHECK: bgtzalc $2, 1332 0x4d 0x01 0x02 0x1c # CHECK: bgtzalc $2, 1336
0x40 0x00 0x05 0x58 # CHECK: blezc $5, 256 0x40 0x00 0x05 0x58 # CHECK: blezc $5, 260
0x4d 0x01 0x42 0x1c # CHECK: bltzalc $2, 1332 0x4d 0x01 0x42 0x1c # CHECK: bltzalc $2, 1336
0x40 0x00 0x05 0x5c # CHECK: bgtzc $5, 256 0x40 0x00 0x05 0x5c # CHECK: bgtzc $5, 260
0x20 0x20 0x02 0x7c # CHECK: bitswap $4, $2 0x20 0x20 0x02 0x7c # CHECK: bitswap $4, $2
0x4d 0x01 0x02 0x18 # CHECK: blezalc $2, 1332 0x4d 0x01 0x02 0x18 # CHECK: blezalc $2, 1336
0x40 0x00 0xa6 0x5c # CHECK: bltc $5, $6, 256 0x40 0x00 0xa6 0x5c # CHECK: bltc $5, $6, 260
0x40 0x00 0xa6 0x1c # CHECK: bltuc $5, $6, 256 0x40 0x00 0xa6 0x1c # CHECK: bltuc $5, $6, 260
0x01 0x00 0x00 0x60 # CHECK: bnvc $zero, $zero, 4 0x01 0x00 0x00 0x60 # CHECK: bnvc $zero, $zero, 8
0x01 0x00 0x40 0x60 # CHECK: bnvc $2, $zero, 4 0x01 0x00 0x40 0x60 # CHECK: bnvc $2, $zero, 8
0x01 0x00 0x82 0x60 # CHECK: bnvc $4, $2, 4 0x01 0x00 0x82 0x60 # CHECK: bnvc $4, $2, 8
0x01 0x00 0x00 0x20 # CHECK: bovc $zero, $zero, 4 0x01 0x00 0x00 0x20 # CHECK: bovc $zero, $zero, 8
0x01 0x00 0x40 0x20 # CHECK: bovc $2, $zero, 4 0x01 0x00 0x40 0x20 # CHECK: bovc $2, $zero, 8
0x01 0x00 0x82 0x20 # CHECK: bovc $4, $2, 4 0x01 0x00 0x82 0x20 # CHECK: bovc $4, $2, 8
0x80 0x18 0x84 0x46 # CHECK: cmp.af.s $f2, $f3, $f4 0x80 0x18 0x84 0x46 # CHECK: cmp.af.s $f2, $f3, $f4
0x80 0x18 0xa4 0x46 # CHECK: cmp.af.d $f2, $f3, $f4 0x80 0x18 0xa4 0x46 # CHECK: cmp.af.d $f2, $f3, $f4
0x81 0x18 0x84 0x46 # CHECK: cmp.un.s $f2, $f3, $f4 0x81 0x18 0x84 0x46 # CHECK: cmp.un.s $f2, $f3, $f4
0x81 0x18 0xa4 0x46 # CHECK: cmp.un.d $f2, $f3, $f4 0x81 0x18 0xa4 0x46 # CHECK: cmp.un.d $f2, $f3, $f4
0x82 0x18 0x84 0x46 # CHECK: cmp.eq.s $f2, $f3, $f4 0x82 0x18 0x84 0x46 # CHECK: cmp.eq.s $f2, $f3, $f4
0x82 0x18 0xa4 0x46 # CHECK: cmp.eq.d $f2, $f3, $f4 0x82 0x18 0xa4 0x46 # CHECK: cmp.eq.d $f2, $f3, $f4
0x83 0x18 0x84 0x46 # CHECK: cmp.ueq.s $f2, $f3, $f4 0x83 0x18 0x84 0x46 # CHECK: cmp.ueq.s $f2, $f3, $f4
0x83 0x18 0xa4 0x46 # CHECK: cmp.ueq.d $f2, $f3, $f4 0x83 0x18 0xa4 0x46 # CHECK: cmp.ueq.d $f2, $f3, $f4
▲ Show 20 Lines • Show All 100 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt

Show All 30 Lines
0x01 0x70 0x00 0x33 # CHECK: tltu $11, $16 0x01 0x70 0x00 0x33 # CHECK: tltu $11, $16
0x01 0xed 0x00 0x32 # CHECK: tlt $15, $13 0x01 0xed 0x00 0x32 # CHECK: tlt $15, $13
0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016 0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016
0x02 0x8e 0x5e 0xf1 # CHECK: tgeu $20, $14, 379 0x02 0x8e 0x5e 0xf1 # CHECK: tgeu $20, $14, 379
0x02 0xdc 0x00 0x31 # CHECK: tgeu $22, $gp 0x02 0xdc 0x00 0x31 # CHECK: tgeu $22, $gp
0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp 0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp
0x04 0x11 0x14 0x9b # CHECK: bal 21104 0x04 0x11 0x14 0x9b # CHECK: bal 21104
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1332 0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1336
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1332 0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1336
0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 256 0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 260
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
0x1c 0x02 0x01 0x4d # CHECK: bgtzalc $2, 1332 0x1c 0x02 0x01 0x4d # CHECK: bgtzalc $2, 1336
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
0x1c 0x42 0x01 0x4d # CHECK: bltzalc $2, 1332 0x1c 0x42 0x01 0x4d # CHECK: bltzalc $2, 1336
0x1c 0xa6 0x00 0x40 # CHECK: bltuc $5, $6, 256 0x1c 0xa6 0x00 0x40 # CHECK: bltuc $5, $6, 260
0x20 0x00 0x00 0x01 # CHECK: bovc $zero, $zero, 4 0x20 0x00 0x00 0x01 # CHECK: bovc $zero, $zero, 8
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
0x20 0x02 0x01 0x4d # CHECK: beqzalc $2, 1332 0x20 0x02 0x01 0x4d # CHECK: beqzalc $2, 1336
0x20 0x40 0x00 0x01 # CHECK: bovc $2, $zero, 4 0x20 0x40 0x00 0x01 # CHECK: bovc $2, $zero, 8
0x20 0x82 0x00 0x01 # CHECK: bovc $4, $2, 4 0x20 0x82 0x00 0x01 # CHECK: bovc $4, $2, 8
0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 256 0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 260
0x25 0x29 0x00 0x0a # CHECK: addiu $9, $9, 10 0x25 0x29 0x00 0x0a # CHECK: addiu $9, $9, 10
0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4 0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4
0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4 0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4
0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23 0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23
0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1 0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
0x40 0x08 0x80 0x03 # CHECK: mfc0 $8, $16, 3 0x40 0x08 0x80 0x03 # CHECK: mfc0 $8, $16, 3
0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1 0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
0x41 0x60 0x60 0x00 # CHECK: di 0x41 0x60 0x60 0x00 # CHECK: di
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
# The immediate should be 8 but the disassembler currently emits 12 # The immediate should be 8 but the disassembler currently emits 12
0x49 0xa0 0x00 0x02 # CHECK: bc2nez $0, 12 0x49 0xa0 0x00 0x02 # CHECK: bc2nez $0, 12
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
# The immediate should be 8 but the disassembler currently emits 12 # The immediate should be 8 but the disassembler currently emits 12
0x49 0xbf 0x00 0x02 # CHECK: bc2nez $31, 12 0x49 0xbf 0x00 0x02 # CHECK: bc2nez $31, 12
0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1) 0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1)
0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18) 0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18)
0x58 0x05 0x00 0x40 # CHECK: blezc $5, 256 0x58 0x05 0x00 0x40 # CHECK: blezc $5, 260
0x58 0x43 0x00 0x40 # CHECK: bgec $2, $3, 256 0x58 0x43 0x00 0x40 # CHECK: bgec $2, $3, 260
0x58 0xa5 0x00 0x40 # CHECK: bgezc $5, 256 0x58 0xa5 0x00 0x40 # CHECK: bgezc $5, 260
0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 256 0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 260
0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 256 0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 260
0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 256 0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 260
0x60 0x00 0x00 0x01 # CHECK: bnvc $zero, $zero, 4 0x60 0x00 0x00 0x01 # CHECK: bnvc $zero, $zero, 8
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
0x60 0x02 0x01 0x4d # CHECK: bnezalc $2, 1332 0x60 0x02 0x01 0x4d # CHECK: bnezalc $2, 1336
0x60 0x40 0x00 0x01 # CHECK: bnvc $2, $zero, 4 0x60 0x40 0x00 0x01 # CHECK: bnvc $2, $zero, 8
0x60 0x82 0x00 0x01 # CHECK: bnvc $4, $2, 4 0x60 0x82 0x00 0x01 # CHECK: bnvc $4, $2, 8
0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256 0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 260
0x7c 0x02 0x20 0x20 # CHECK: bitswap $4, $2 0x7c 0x02 0x20 0x20 # CHECK: bitswap $4, $2
0x7c 0x43 0x22 0xa0 # CHECK: align $4, $2, $3, 2 0x7c 0x43 0x22 0xa0 # CHECK: align $4, $2, $3, 2
0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5) 0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5)
0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5) 0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5)
0x7e 0x42 0xb3 0xb6 # CHECK: ll $2, -153($18) 0x7e 0x42 0xb3 0xb6 # CHECK: ll $2, -153($18)
0x7e 0x6f 0xec 0x26 # CHECK: sc $15, -40($19) 0x7e 0x6f 0xec 0x26 # CHECK: sc $15, -40($19)
0xc8 0x37 0x96 0xb8 # CHECK: bc 14572256 0xc8 0x37 0x96 0xb8 # CHECK: bc 14572260
0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256 0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256
0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72256 0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72260
0xe8 0x37 0x96 0xb8 # CHECK: balc 14572256 0xe8 0x37 0x96 0xb8 # CHECK: balc 14572260
0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268 0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268
0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268 0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268
0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1 0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1
0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56 0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56
0xec 0x80 0x00 0x19 # CHECK: addiupc $4, 100 0xec 0x80 0x00 0x19 # CHECK: addiupc $4, 100
0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256 0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256
0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72256 0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72260

test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt

# RUN: llvm-mc %s -disassemble -triple=mipsel-unknown-linux -mcpu=mips64r6 | FileCheck %s # RUN: llvm-mc %s -disassemble -triple=mipsel-unknown-linux -mcpu=mips64r6 | FileCheck %s
0x0a 0x00 0x29 0x25 # CHECK: addiu $9, $9, 10 0x0a 0x00 0x29 0x25 # CHECK: addiu $9, $9, 10
0x19 0x00 0x80 0xec # CHECK: addiupc $4, 100 0x19 0x00 0x80 0xec # CHECK: addiupc $4, 100
0xa0 0x22 0x43 0x7c # CHECK: align $4, $2, $3, 2 0xa0 0x22 0x43 0x7c # CHECK: align $4, $2, $3, 2
0x38 0x00 0x7f 0xec # CHECK: aluipc $3, 56 0x38 0x00 0x7f 0xec # CHECK: aluipc $3, 56
0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4 0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4
0xe9 0xff 0x62 0x3c # CHECK: aui $3, $2, -23 0xe9 0xff 0x62 0x3c # CHECK: aui $3, $2, -23
0xff 0xff 0x7e 0xec # CHECK: auipc $3, -1 0xff 0xff 0x7e 0xec # CHECK: auipc $3, -1
0x9b 0x14 0x11 0x04 # CHECK: bal 21104 0x9b 0x14 0x11 0x04 # CHECK: bal 21104
0xb8 0x96 0x37 0xe8 # CHECK: balc 14572256 0xb8 0x96 0x37 0xe8 # CHECK: balc 14572260
0xb8 0x96 0x37 0xc8 # CHECK: bc 14572256 0xb8 0x96 0x37 0xc8 # CHECK: bc 14572260
0x01 0x00 0x20 0x45 # CHECK: bc1eqz $f0, 8 0x01 0x00 0x20 0x45 # CHECK: bc1eqz $f0, 8
0x01 0x00 0x3f 0x45 # CHECK: bc1eqz $f31, 8 0x01 0x00 0x3f 0x45 # CHECK: bc1eqz $f31, 8
0x01 0x00 0xa0 0x45 # CHECK: bc1nez $f0, 8 0x01 0x00 0xa0 0x45 # CHECK: bc1nez $f0, 8
0x01 0x00 0xbf 0x45 # CHECK: bc1nez $f31, 8 0x01 0x00 0xbf 0x45 # CHECK: bc1nez $f31, 8
0x02 0x00 0x20 0x49 # CHECK: bc2eqz $0, 12 0x02 0x00 0x20 0x49 # CHECK: bc2eqz $0, 12
0x02 0x00 0x3f 0x49 # CHECK: bc2eqz $31, 12 0x02 0x00 0x3f 0x49 # CHECK: bc2eqz $31, 12
0x02 0x00 0xa0 0x49 # CHECK: bc2nez $0, 12 0x02 0x00 0xa0 0x49 # CHECK: bc2nez $0, 12
0x02 0x00 0xbf 0x49 # CHECK: bc2nez $31, 12 0x02 0x00 0xbf 0x49 # CHECK: bc2nez $31, 12
0x40 0x00 0xa6 0x20 # CHECK: beqc $5, $6, 256 0x40 0x00 0xa6 0x20 # CHECK: beqc $5, $6, 260
0x4d 0x01 0x02 0x20 # CHECK: beqzalc $2, 1332 0x4d 0x01 0x02 0x20 # CHECK: beqzalc $2, 1336
0x90 0x46 0xa0 0xd8 # CHECK: beqzc $5, 72256 0x90 0x46 0xa0 0xd8 # CHECK: beqzc $5, 72260
0x40 0x00 0x43 0x58 # CHECK: bgec $2, $3, 256 0x40 0x00 0x43 0x58 # CHECK: bgec $2, $3, 260
0x40 0x00 0x43 0x18 # CHECK: bgeuc $2, $3, 256 0x40 0x00 0x43 0x18 # CHECK: bgeuc $2, $3, 260
0x4d 0x01 0x42 0x18 # CHECK: bgezalc $2, 1332 0x4d 0x01 0x42 0x18 # CHECK: bgezalc $2, 1336
0x40 0x00 0xa5 0x58 # CHECK: bgezc $5, 256 0x40 0x00 0xa5 0x58 # CHECK: bgezc $5, 260
0x4d 0x01 0x02 0x1c # CHECK: bgtzalc $2, 1332 0x4d 0x01 0x02 0x1c # CHECK: bgtzalc $2, 1336
0x40 0x00 0x05 0x5c # CHECK: bgtzc $5, 256 0x40 0x00 0x05 0x5c # CHECK: bgtzc $5, 260
0x20 0x20 0x02 0x7c # CHECK: bitswap $4, $2 0x20 0x20 0x02 0x7c # CHECK: bitswap $4, $2
0x4d 0x01 0x02 0x18 # CHECK: blezalc $2, 1332 0x4d 0x01 0x02 0x18 # CHECK: blezalc $2, 1336
0x40 0x00 0x05 0x58 # CHECK: blezc $5, 256 0x40 0x00 0x05 0x58 # CHECK: blezc $5, 260
0x40 0x00 0xa6 0x5c # CHECK: bltc $5, $6, 256 0x40 0x00 0xa6 0x5c # CHECK: bltc $5, $6, 260
0x40 0x00 0xa6 0x1c # CHECK: bltuc $5, $6, 256 0x40 0x00 0xa6 0x1c # CHECK: bltuc $5, $6, 260
0x4d 0x01 0x42 0x1c # CHECK: bltzalc $2, 1332 0x4d 0x01 0x42 0x1c # CHECK: bltzalc $2, 1336
0x40 0x00 0xa5 0x5c # CHECK: bltzc $5, 256 0x40 0x00 0xa5 0x5c # CHECK: bltzc $5, 260
0x40 0x00 0xa6 0x60 # CHECK: bnec $5, $6, 256 0x40 0x00 0xa6 0x60 # CHECK: bnec $5, $6, 260
0x4d 0x01 0x02 0x60 # CHECK: bnezalc $2, 1332 0x4d 0x01 0x02 0x60 # CHECK: bnezalc $2, 1336
0x90 0x46 0xa0 0xf8 # CHECK: bnezc $5, 72256 0x90 0x46 0xa0 0xf8 # CHECK: bnezc $5, 72260
0x01 0x00 0x40 0x60 # CHECK: bnvc $2, $zero, 4 0x01 0x00 0x40 0x60 # CHECK: bnvc $2, $zero, 8
0x01 0x00 0x82 0x60 # CHECK: bnvc $4, $2, 4 0x01 0x00 0x82 0x60 # CHECK: bnvc $4, $2, 8
0x01 0x00 0x00 0x60 # CHECK: bnvc $zero, $zero, 4 0x01 0x00 0x00 0x60 # CHECK: bnvc $zero, $zero, 8
0x01 0x00 0x40 0x20 # CHECK: bovc $2, $zero, 4 0x01 0x00 0x40 0x20 # CHECK: bovc $2, $zero, 8
0x01 0x00 0x82 0x20 # CHECK: bovc $4, $2, 4 0x01 0x00 0x82 0x20 # CHECK: bovc $4, $2, 8
0x01 0x00 0x00 0x20 # CHECK: bovc $zero, $zero, 4 0x01 0x00 0x00 0x20 # CHECK: bovc $zero, $zero, 8
0x25 0x04 0xa1 0x7c # CHECK: cache 1, 8($5) 0x25 0x04 0xa1 0x7c # CHECK: cache 1, 8($5)
0x9b 0x20 0x20 0x46 # CHECK: class.d $f2, $f4 0x9b 0x20 0x20 0x46 # CHECK: class.d $f2, $f4
0x9b 0x20 0x00 0x46 # CHECK: class.s $f2, $f4 0x9b 0x20 0x00 0x46 # CHECK: class.s $f2, $f4
0x51 0x58 0xa0 0x00 # CHECK: clo $11, $5 0x51 0x58 0xa0 0x00 # CHECK: clo $11, $5
0x50 0xe8 0x80 0x03 # CHECK: clz $sp, $gp 0x50 0xe8 0x80 0x03 # CHECK: clz $sp, $gp
0x80 0x18 0xa4 0x46 # CHECK: cmp.af.d $f2, $f3, $f4 0x80 0x18 0xa4 0x46 # CHECK: cmp.af.d $f2, $f3, $f4
0x80 0x18 0x84 0x46 # CHECK: cmp.af.s $f2, $f3, $f4 0x80 0x18 0x84 0x46 # CHECK: cmp.af.s $f2, $f3, $f4
0x82 0x18 0xa4 0x46 # CHECK: cmp.eq.d $f2, $f3, $f4 0x82 0x18 0xa4 0x46 # CHECK: cmp.eq.d $f2, $f3, $f4
▲ Show 20 Lines • Show All 122 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
0x03 0x20 0x80 0x52 # CHECK: dclz $16, $25 0x03 0x20 0x80 0x52 # CHECK: dclz $16, $25
0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp 0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp
0x03 0xe0 0x78 0x25 # CHECK: move $15, $ra 0x03 0xe0 0x78 0x25 # CHECK: move $15, $ra
0x03 0xe0 0x78 0x2d # CHECK: move $15, $ra 0x03 0xe0 0x78 0x2d # CHECK: move $15, $ra
0x04 0x11 0x14 0x9b # CHECK: bal 21104 0x04 0x11 0x14 0x9b # CHECK: bal 21104
0x04 0x66 0x56 0x78 # CHECK: dahi $3, 22136 0x04 0x66 0x56 0x78 # CHECK: dahi $3, 22136
0x04 0x7e 0xab 0xcd # CHECK: dati $3, -21555 0x04 0x7e 0xab 0xcd # CHECK: dati $3, -21555
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1332 0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1336
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1332 0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1336
0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 256 0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 260
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
0x1c 0x02 0x01 0x4d # CHECK: bgtzalc $2, 1332 0x1c 0x02 0x01 0x4d # CHECK: bgtzalc $2, 1336
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
0x1c 0x42 0x01 0x4d # CHECK: bltzalc $2, 1332 0x1c 0x42 0x01 0x4d # CHECK: bltzalc $2, 1336
0x1c 0xa6 0x00 0x40 # CHECK: bltuc $5, $6, 256 0x1c 0xa6 0x00 0x40 # CHECK: bltuc $5, $6, 260
0x20 0x00 0x00 0x01 # CHECK: bovc $zero, $zero, 4 0x20 0x00 0x00 0x01 # CHECK: bovc $zero, $zero, 8
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
0x20 0x02 0x01 0x4d # CHECK: beqzalc $2, 1332 0x20 0x02 0x01 0x4d # CHECK: beqzalc $2, 1336
0x20 0x40 0x00 0x01 # CHECK: bovc $2, $zero, 4 0x20 0x40 0x00 0x01 # CHECK: bovc $2, $zero, 8
0x20 0x82 0x00 0x01 # CHECK: bovc $4, $2, 4 0x20 0x82 0x00 0x01 # CHECK: bovc $4, $2, 8
0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 256 0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 260
0x25 0x29 0x00 0x0a # CHECK: addiu $9, $9, 10 0x25 0x29 0x00 0x0a # CHECK: addiu $9, $9, 10
0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4 0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4
0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4 0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4
0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23 0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23
0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1 0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
0x40 0x08 0x80 0x03 # CHECK: mfc0 $8, $16, 3 0x40 0x08 0x80 0x03 # CHECK: mfc0 $8, $16, 3
0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0 0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0
0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1 0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
# The immediate should be 8 but the disassembler currently emits 12 # The immediate should be 8 but the disassembler currently emits 12
0x49 0xa0 0x00 0x02 # CHECK: bc2nez $0, 12 0x49 0xa0 0x00 0x02 # CHECK: bc2nez $0, 12
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
# The immediate should be 8 but the disassembler currently emits 12 # The immediate should be 8 but the disassembler currently emits 12
0x49 0xbf 0x00 0x02 # CHECK: bc2nez $31, 12 0x49 0xbf 0x00 0x02 # CHECK: bc2nez $31, 12
0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1) 0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1)
0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18) 0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18)
0x58 0x05 0x00 0x40 # CHECK: blezc $5, 256 0x58 0x05 0x00 0x40 # CHECK: blezc $5, 260
0x58 0x43 0x00 0x40 # CHECK: bgec $2, $3, 256 0x58 0x43 0x00 0x40 # CHECK: bgec $2, $3, 260
0x58 0xa5 0x00 0x40 # CHECK: bgezc $5, 256 0x58 0xa5 0x00 0x40 # CHECK: bgezc $5, 260
0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 256 0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 260
0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 256 0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 260
0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 256 0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 260
0x60 0x00 0x00 0x01 # CHECK: bnvc $zero, $zero, 4 0x60 0x00 0x00 0x01 # CHECK: bnvc $zero, $zero, 8
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
0x60 0x02 0x01 0x4d # CHECK: bnezalc $2, 1332 0x60 0x02 0x01 0x4d # CHECK: bnezalc $2, 1336
0x60 0x40 0x00 0x01 # CHECK: bnvc $2, $zero, 4 0x60 0x40 0x00 0x01 # CHECK: bnvc $2, $zero, 8
0x60 0x82 0x00 0x01 # CHECK: bnvc $4, $2, 4 0x60 0x82 0x00 0x01 # CHECK: bnvc $4, $2, 8
0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256 0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 260
0x74 0x62 0x12 0x34 # CHECK: daui $3, $2, 4660 0x74 0x62 0x12 0x34 # CHECK: daui $3, $2, 4660
0x7c 0x02 0x20 0x20 # CHECK: bitswap $4, $2 0x7c 0x02 0x20 0x20 # CHECK: bitswap $4, $2
0x7c 0x02 0x20 0x24 # CHECK: dbitswap $4, $2 0x7c 0x02 0x20 0x24 # CHECK: dbitswap $4, $2
0x7c 0x43 0x22 0xa0 # CHECK: align $4, $2, $3, 2 0x7c 0x43 0x22 0xa0 # CHECK: align $4, $2, $3, 2
0x7c 0x43 0x23 0x64 # CHECK: dalign $4, $2, $3, 5 0x7c 0x43 0x23 0x64 # CHECK: dalign $4, $2, $3, 5
0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5) 0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5)
0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5) 0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5)
0x7e 0x42 0xb3 0xb6 # CHECK: ll $2, -153($18) 0x7e 0x42 0xb3 0xb6 # CHECK: ll $2, -153($18)
0x7e 0x6f 0xec 0x26 # CHECK: sc $15, -40($19) 0x7e 0x6f 0xec 0x26 # CHECK: sc $15, -40($19)
0x7f 0xaf 0xe6 0xa7 # CHECK: scd $15, -51($sp) 0x7f 0xaf 0xe6 0xa7 # CHECK: scd $15, -51($sp)
0x7f 0xe0 0x38 0x37 # CHECK: lld $zero, 112($ra) 0x7f 0xe0 0x38 0x37 # CHECK: lld $zero, 112($ra)
0xc8 0x37 0x96 0xb8 # CHECK: bc 14572256 0xc8 0x37 0x96 0xb8 # CHECK: bc 14572260
0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256 0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256
0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72256 0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72260
0xe8 0x37 0x96 0xb8 # CHECK: balc 14572256 0xe8 0x37 0x96 0xb8 # CHECK: balc 14572260
0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268 0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268
0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268 0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268
0xec 0x58 0x3c 0x48 # CHECK: ldpc $2, 123456 0xec 0x58 0x3c 0x48 # CHECK: ldpc $2, 123456
0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1 0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1
0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56 0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56
0xec 0x80 0x00 0x19 # CHECK: addiupc $4, 100 0xec 0x80 0x00 0x19 # CHECK: addiupc $4, 100
0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256 0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256
0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72256 0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72260