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Differential D20330

[mips][mips16] Fix ZERO is not a CPU16Regs register error from the machine verifier.
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Authored by dsanders on May 17 2016, 7:20 AM.

Details

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sdardis
Commits
rG2f2ab5102c14: [mips][mips16] Fix ZERO is not a CPU16Regs register error from the machine…
rL270037: [mips][mips16] Fix ZERO is not a CPU16Regs register error from the machine…
Summary

Partially fixes PR27458

Diff Detail

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rL LLVM

Event Timeline

dsanders updated this revision to Diff 57476.May 17 2016, 7:20 AM
dsanders retitled this revision from to [mips][mips16] Fix ZERO is not a CPU16Regs register error from the machine verifier..
dsanders updated this object.
dsanders added a reviewer: sdardis.
dsanders added a subscriber: llvm-commits.
Herald added subscribers: sdardis, dsanders. · View Herald TranscriptMay 17 2016, 7:20 AM
sdardis accepted this revision.May 18 2016, 3:23 AM
sdardis edited edge metadata.

LGTM.

This revision is now accepted and ready to land.May 18 2016, 3:23 AM
Closed by commit rL270037: [mips][mips16] Fix ZERO is not a CPU16Regs register error from the machine… (authored by dsanders). · Explain WhyMay 19 2016, 3:49 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
2 lines
test/
CodeGen/
Mips/
3 lines

Diff 57760

llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td

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// <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), // <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
// (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) // (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
// >; // >;
def: UncondBranch16_pat<br, Bimm16>; def: UncondBranch16_pat<br, Bimm16>;
// Small immediates // Small immediates
def: Mips16Pat<(i32 immSExt16:$in), def: Mips16Pat<(i32 immSExt16:$in),
(AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>; (AddiuRxRxImmX16 (MoveR3216 ZERO), immSExt16:$in)>;
def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>; def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
// //
// MipsDivRem // MipsDivRem
// //
def: Mips16Pat def: Mips16Pat
<(MipsDivRem16 CPU16Regs:$rx, CPU16Regs:$ry), <(MipsDivRem16 CPU16Regs:$rx, CPU16Regs:$ry),
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llvm/trunk/test/CodeGen/Mips/mips16fpe.ll

; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16hf ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 \
; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=16hf
@x = global float 5.000000e+00, align 4 @x = global float 5.000000e+00, align 4
@y = global float 1.500000e+01, align 4 @y = global float 1.500000e+01, align 4
@xd = global double 6.000000e+00, align 8 @xd = global double 6.000000e+00, align 8
@yd = global double 1.800000e+01, align 8 @yd = global double 1.800000e+01, align 8
@two = global i32 2, align 4 @two = global i32 2, align 4
@addsf3_result = common global float 0.000000e+00, align 4 @addsf3_result = common global float 0.000000e+00, align 4
@adddf3_result = common global double 0.000000e+00, align 8 @adddf3_result = common global double 0.000000e+00, align 8
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