[mips] Compact branch policy control for MIPSR6

[sdardis]

Summary

This patch adds the commandline option -mips-compact-branches={never,optimal,always),
which controls how LLVM generates compact branches for MIPS targets. By
default, the compact branch policy is 'optimal' where LLVM will (hopefully)
pick the optimal branch for any situation. The 'never' policy will disable
the generation of compact branches and 'always' will generate compact branches
wherever possible.

[dsanders]

LGTM with a couple nits

lib/Target/Mips/MipsDelaySlotFiller.cpp

66–68

We should mention that never/always aren't absolute in a doxygen comment.

Also an optional nit: We don't have any rules about it but most enumerators seem to separate the prefix from the name using an underscore (e.g. 'CB_Never')

test/CodeGen/Mips/compactbranches/compact-branch-policy.ll

13

Could you add a comment indicating why the ALWAYS case has one?

[sdardis]

Thanks, committed as rL269753.

lib/Target/Mips/MipsDelaySlotFiller.cpp

static cl::opt<bool> DisableSuccBBSearch(
   cl::Hidden);
 
 static cl::opt<bool> DisableBackwardSearch(
   "disable-mips-df-backward-search",
   cl::init(false),
   cl::desc("Disallow MIPS delay filler to search backward."),
   cl::Hidden);
 
+enum CompactBranchPolicy {
+  CBNever,
+  CBOptimal,
+  CBAlways
+};
+
+static cl::opt<CompactBranchPolicy> MipsCompactBranchPolicy(
+  "mips-compact-branches",cl::Optional,
+  cl::init(CBOptimal),
+  cl::desc("MIPS Specific: Compact branch policy."),
+  cl::values(
+    clEnumValN(CBNever, "never", "Do not use compact branches if possible."),
+    clEnumValN(CBOptimal, "optimal", "Use compact branches where appropiate (default)."),
+    clEnumValN(CBAlways, "always", "Always use compact branches if possible."),
+    clEnumValEnd
+  )
+);
+
 namespace {
   typedef MachineBasicBlock::iterator Iter;
   typedef MachineBasicBlock::reverse_iterator ReverseIter;
   typedef SmallDenseMap<MachineBasicBlock*, MachineInstr*, 2> BB2BrMap;
 
   class RegDefsUses {
   public:
     RegDefsUses(const TargetRegisterInfo &TRI);
for (Iter I = MBB.begin(); I != MBB.end(); ++I) {
 
     ++FilledSlots;
     Changed = true;
 
     // Delay slot filling is disabled at -O0.
     if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None)) {
       bool Filled = false;
 
+      if (MipsCompactBranchPolicy.getValue() != CBAlways ||
+           !TII->getEquivalentCompactForm(I)) {
         if (searchBackward(MBB, I)) {
           Filled = true;
         } else if (I->isTerminator()) {
           if (searchSuccBBs(MBB, I)) {
             Filled = true;
           }
         } else if (searchForward(MBB, I)) {
           Filled = true;
         }
+      }
 
       if (Filled) {
         // Get instruction with delay slot.
         MachineBasicBlock::instr_iterator DSI(I);
 
         if (InMicroMipsMode && TII->GetInstSizeInBytes(&*std::next(DSI)) == 2 &&
             DSI->isCall()) {
           // If instruction in delay slot is 16b change opcode to
           // corresponding instruction with short delay slot.
           DSI->setDesc(TII->get(getEquivalentCallShort(DSI->getOpcode())));
         }
         continue;
       }
     }
 
     // For microMIPS if instruction is BEQ or BNE with one ZERO register, then
     // instead of adding NOP replace this instruction with the corresponding
     // compact branch instruction, i.e. BEQZC or BNEZC. Additionally
     // PseudoReturn and PseudoIndirectBranch are expanded to JR_MM, so they can
     // be replaced with JRC16_MM.
 
     // For MIPSR6 attempt to produce the corresponding compact (no delay slot)
     // form of the CTI. For indirect jumps this will not require inserting a
     // NOP and for branches will hopefully avoid requiring a NOP.
-    if ((InMicroMipsMode || STI.hasMips32r6()) &&
-         TII->getEquivalentCompactForm(I)) {
+    if ((InMicroMipsMode ||
+         (STI.hasMips32r6() && MipsCompactBranchPolicy != CBNever)) &&
       I = replaceWithCompactBranch(MBB, I, I->getDebugLoc());
       continue;
     }
 
     // Bundle the NOP to the instruction with the delay slot.
     BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
     MIBundleBuilder(MBB, I, std::next(I, 2));
   }

test/CodeGen/Mips/compactbranches/compact-branch-policy.ll

+; Check that -mips-compact-branches={never,optimal,always} is accepted and honoured.
+; RUN: llc -march=mips -mcpu=mips32r6 -mips-compact-branches=never < %s | FileCheck %s -check-prefix=NEVER
+; RUN: llc -march=mips -mcpu=mips32r6 -mips-compact-branches=optimal < %s | FileCheck %s -check-prefix=OPTIMAL
+; RUN: llc -march=mips -mcpu=mips32r6 -mips-compact-branches=always < %s | FileCheck %s -check-prefix=ALWAYS
+
+define i32 @l(i32 signext %a, i32 signext %b) {
+entry:
+  %add = add nsw i32 %b, %a
+  %cmp = icmp slt i32 %add, 100
+; NEVER: beq
+; OPTIMAL: beq
+; ALWAYS: beqzc
+; ALWAYS: nop
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  %call = tail call i32 @k()
+  br label %if.end
+
+if.end:                                           ; preds = %entry, %if.then
+  %call.pn = phi i32 [ %call, %if.then ], [ -1, %entry ]
+  %c.0 = add nsw i32 %call.pn, %add
+  ret i32 %c.0
+}
+
+declare i32 @k() #1