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Differential D19602

[AMDGPU][llvm-mc] Add some missing testcases to trap.s
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Authored by artem.tamazov on Apr 27 2016, 10:24 AM.

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nhaustov
• tstellarAMD
Commits
rG5d3ae19bdf00: [AMDGPU][llvm-mc] Add some missing testcases to trap.s
rL268073: [AMDGPU][llvm-mc] Add some missing testcases to trap.s

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rL LLVM

Event Timeline

artem.tamazov updated this revision to Diff 55254.Apr 27 2016, 10:24 AM
artem.tamazov retitled this revision from to [AMDGPU][llvm-mc] Add some missing testcases to trap.s.
artem.tamazov updated this object.
artem.tamazov added a reviewer: nhaustov.
artem.tamazov set the repository for this revision to rL LLVM.
artem.tamazov added a project: Restricted Project.
artem.tamazov added a subscriber: Restricted Project.
Herald added a reviewer: • tstellarAMD. · View Herald TranscriptApr 27 2016, 10:24 AM
nhaustov accepted this revision.Apr 28 2016, 9:08 AM
nhaustov edited edge metadata.

Ok.

This revision is now accepted and ready to land.Apr 28 2016, 9:08 AM
Closed by commit rL268073: [AMDGPU][llvm-mc] Add some missing testcases to trap.s (authored by artem.tamazov). · Explain WhyApr 29 2016, 10:47 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
test/
MC/
AMDGPU/
25 lines

Diff 55624

llvm/trunk/test/MC/AMDGPU/trap.s

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
s_cmp_eq_i32 ttmp8, 0x000000fe s_cmp_eq_i32 ttmp8, 0x000000fe
// SICI: s_cmp_eq_i32 ttmp8, 0xfe ; encoding: [0x78,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00] // SICI: s_cmp_eq_i32 ttmp8, 0xfe ; encoding: [0x78,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00]
// VI: s_cmp_eq_i32 ttmp8, 0xfe ; encoding: [0x78,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00] // VI: s_cmp_eq_i32 ttmp8, 0xfe ; encoding: [0x78,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00]
s_lshr_b32 ttmp8, ttmp8, 12 s_lshr_b32 ttmp8, ttmp8, 12
// SICI: s_lshr_b32 ttmp8, ttmp8, 12 ; encoding: [0x78,0x8c,0x78,0x90] // SICI: s_lshr_b32 ttmp8, ttmp8, 12 ; encoding: [0x78,0x8c,0x78,0x90]
// VI: s_lshr_b32 ttmp8, ttmp8, 12 ; encoding: [0x78,0x8c,0x78,0x8f] // VI: s_lshr_b32 ttmp8, ttmp8, 12 ; encoding: [0x78,0x8c,0x78,0x8f]
v_mov_b32 v1, ttmp8
// SICI: v_mov_b32_e32 v1, ttmp8 ; encoding: [0x78,0x02,0x02,0x7e]
// VI: v_mov_b32_e32 v1, ttmp8 ; encoding: [0x78,0x02,0x02,0x7e]
s_mov_b32 m0, ttmp8 s_mov_b32 m0, ttmp8
// SICI: s_mov_b32 m0, ttmp8 ; encoding: [0x78,0x03,0xfc,0xbe] // SICI: s_mov_b32 m0, ttmp8 ; encoding: [0x78,0x03,0xfc,0xbe]
// VI: s_mov_b32 m0, ttmp8 ; encoding: [0x78,0x00,0xfc,0xbe] // VI: s_mov_b32 m0, ttmp8 ; encoding: [0x78,0x00,0xfc,0xbe]
s_mov_b32 ttmp10, 0 s_mov_b32 ttmp10, 0
// SICI: s_mov_b32 ttmp10, 0 ; encoding: [0x80,0x03,0xfa,0xbe] // SICI: s_mov_b32 ttmp10, 0 ; encoding: [0x80,0x03,0xfa,0xbe]
// VI: s_mov_b32 ttmp10, 0 ; encoding: [0x80,0x00,0xfa,0xbe] // VI: s_mov_b32 ttmp10, 0 ; encoding: [0x80,0x00,0xfa,0xbe]
Show All 20 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Trap Handler related - Pairs and quadruples of registers // Trap Handler related - Pairs and quadruples of registers
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
s_mov_b64 ttmp[4:5], exec s_mov_b64 ttmp[4:5], exec
// SICI: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x04,0xf4,0xbe] // SICI: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x04,0xf4,0xbe]
// VI: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf4,0xbe] // VI: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf4,0xbe]
s_mov_b64 [ttmp4,ttmp5], exec
// SICI: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x04,0xf4,0xbe]
// VI: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf4,0xbe]
s_mov_b64 exec, [ttmp4,ttmp5]
// SICI: s_mov_b64 exec, ttmp[4:5] ; encoding: [0x74,0x04,0xfe,0xbe]
// VI: s_mov_b64 exec, ttmp[4:5] ; encoding: [0x74,0x01,0xfe,0xbe]
s_mov_b64 tba, ttmp[4:5] s_mov_b64 tba, ttmp[4:5]
// SICI: s_mov_b64 tba, ttmp[4:5] ; encoding: [0x74,0x04,0xec,0xbe] // SICI: s_mov_b64 tba, ttmp[4:5] ; encoding: [0x74,0x04,0xec,0xbe]
// VI: s_mov_b64 tba, ttmp[4:5] ; encoding: [0x74,0x01,0xec,0xbe] // VI: s_mov_b64 tba, ttmp[4:5] ; encoding: [0x74,0x01,0xec,0xbe]
s_mov_b64 ttmp[4:5], tba s_mov_b64 ttmp[4:5], tba
// SICI: s_mov_b64 ttmp[4:5], tba ; encoding: [0x6c,0x04,0xf4,0xbe] // SICI: s_mov_b64 ttmp[4:5], tba ; encoding: [0x6c,0x04,0xf4,0xbe]
// VI: s_mov_b64 ttmp[4:5], tba ; encoding: [0x6c,0x01,0xf4,0xbe] // VI: s_mov_b64 ttmp[4:5], tba ; encoding: [0x6c,0x01,0xf4,0xbe]
s_mov_b64 tma, ttmp[4:5] s_mov_b64 tma, ttmp[4:5]
// SICI: s_mov_b64 tma, ttmp[4:5] ; encoding: [0x74,0x04,0xee,0xbe] // SICI: s_mov_b64 tma, ttmp[4:5] ; encoding: [0x74,0x04,0xee,0xbe]
// VI: s_mov_b64 tma, ttmp[4:5] ; encoding: [0x74,0x01,0xee,0xbe] // VI: s_mov_b64 tma, ttmp[4:5] ; encoding: [0x74,0x01,0xee,0xbe]
s_mov_b64 ttmp[4:5], tma s_mov_b64 ttmp[4:5], tma
// SICI: s_mov_b64 ttmp[4:5], tma ; encoding: [0x6e,0x04,0xf4,0xbe] // SICI: s_mov_b64 ttmp[4:5], tma ; encoding: [0x6e,0x04,0xf4,0xbe]
// VI: s_mov_b64 ttmp[4:5], tma ; encoding: [0x6e,0x01,0xf4,0xbe] // VI: s_mov_b64 ttmp[4:5], tma ; encoding: [0x6e,0x01,0xf4,0xbe]
//===----------------------------------------------------------------------===//
// Trap Handler related - Some specific instructions
//===----------------------------------------------------------------------===//
s_setpc_b64 [ttmp2,ttmp3]
// SICI: s_setpc_b64 ttmp[2:3] ; encoding: [0x72,0x20,0x80,0xbe]
// VI: s_setpc_b64 ttmp[2:3] ; encoding: [0x72,0x1d,0x80,0xbe]
v_readfirstlane_b32 ttmp8, v1
// SICI: v_readfirstlane_b32 ttmp8, v1 ; encoding: [0x01,0x05,0xf0,0x7e]
// VI: v_readfirstlane_b32 ttmp8, v1 ; encoding: [0x01,0x05,0xf0,0x7e]