[mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructions

[hvarga]

Summary

This patch implements SLT, SLTI, SLTIU and SLTU microMIPS32r6 instructions.

[sdardis]

LGTM with those 2 nits addressed.

lib/Target/Mips/MicroMips32r6InstrInfo.td

984–986 ↗

(On Diff #54463)

This change should be separate. Also, what's the reason behind this change?

lib/Target/Mips/MipsInstrInfo.td

1651–1661 ↗

(On Diff #54463)

Join these blocks together.

[hvarga]

lib/Target/Mips/MicroMips32r6InstrInfo.td

984–986 ↗

(On Diff #54463)

Well actually, It can't be in a separate patch. :)

The reason is that I needed to remove setting list<dag> Pattern = []; in MMArch class. Removing this caused test test/CodeGen/Mips/llvm-ir/add.ll to fail because of wrong instruction selection. In this test, it was expected to select the instruction ADDU16 but instead, instruction ADDU is selected. So, ADDu_MM is selected instead of ADDU16_MMR6.

Using the llvm-tblgen tool I have discovered that ADDu_MM is selected because this definition now, after removing the Pattern in MMArch, has a correct Pattern.

So the MMArch class is actually removing the Pattern which was, for ADDu_MM, defined in a class ArithLogicR. From my point, this is not the desired behavior.

It can be seen from the llvm-tblgen output that for the ADDu_MM the MMArch is set after the ArithLogicR in the inheritance chain. Hence, MMArch overrides the Pattern which was set in ArithLogicR class.

I am certain that this problem is also manifesting for SLT_MM and probably couple more instructions from this patch and the rest of codebase.

lib/Target/Mips/MipsInstrInfo.td

1651–1661 ↗

(On Diff #54463)

Will do.

[sdardis]

Thank you for the explanation. Go ahead and commit with the one nit addressed.

llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td

class LOAD_WORD_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> :
   dag InOperandList = (ins mem_mm_12:$addr);
   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
   string DecoderMethod = "DecodeMemMMImm9";
   bit mayLoad = 1;
 }
 class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd>;
 class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd>;
 class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
-      MMR6Arch<"addu16">;
+      MMR6Arch<"addu16"> {
+  int AddedComplexity  = 1;
+}
 class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
       MMR6Arch<"and16">;
 class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
       MMR6Arch<"andi16">;
 class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16">;
 class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
       MMR6Arch<"or16">;
 class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,

llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td

 }
 
 //===----------------------------------------------------------------------===//
 // MicroMIPS 32-bit Instruction Formats
 //===----------------------------------------------------------------------===//
 
 class MMArch {
   string Arch = "micromips";
-  list<dag> Pattern = [];
 }
 
 class ADD_FM_MM<bits<6> op, bits<10> funct> : MMArch {
   bits<5> rt;
   bits<5> rs;
   bits<5> rd;
 
   bits<32> Inst;

llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td

 def : MipsPat<(store GPR32:$src, addr:$addr),
               (SW_MM GPR32:$src, addr:$addr)>;
 
 def : MipsPat<(load addrimm4lsl2:$addr),
               (LW16_MM addrimm4lsl2:$addr)>;
 def : MipsPat<(load addr:$addr),
               (LW_MM addr:$addr)>;
 
+defm : SeteqPats<GPR32, SLTiu_MM, XOR_MM, SLTu_MM, ZERO>;
+
 //===----------------------------------------------------------------------===//
 // MicroMips instruction aliases
 //===----------------------------------------------------------------------===//
 
 class UncondBranchMMPseudo<string opstr> :
   MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
                     !strconcat(opstr, "\t$offset")>;
 
def : MipsInstAlias<"tlt $rs, $rt",
                     (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
 def : MipsInstAlias<"tltu $rs, $rt",
                     (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
 def : MipsInstAlias<"tne $rs, $rt",
                     (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
 def : MipsInstAlias<"rotr $rt, $imm",
                     (ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>;
 def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>;
+def : MipsInstAlias<"slt $rs, $rt, $imm",
+                    (SLTi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
 }

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

 /// Arithmetic Instructions (ALU Immediate)
 let AdditionalPredicates = [NotInMicroMips] in {
 def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16_relaxed, GPR32Opnd,
                                            II_ADDIU, immSExt16, add>,
             ADDI_FM<0x9>, IsAsCheapAsAMove;
 }
 def ADDi  : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd>, ADDI_FM<0x8>,
             ISA_MIPS1_NOT_32R6_64R6;
+let AdditionalPredicates = [NotInMicroMips] in {
 def SLTi  : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
             SLTI_FM<0xa>;
 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
             SLTI_FM<0xb>;
-let AdditionalPredicates = [NotInMicroMips] in {
 def ANDi  : MMRel, StdMMR6Rel,
             ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>,
             ADDI_FM<0xc>;
 }
 def ORi   : MMRel, StdMMR6Rel,
             ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>,
             ADDI_FM<0xd>;
 def XORi  : MMRel, StdMMR6Rel,
             ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>,
             ADDI_FM<0xe>;
 def LUi   : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM;
 let AdditionalPredicates = [NotInMicroMips] in {
 /// Arithmetic Instructions (3-Operand, R-Type)
 def ADDu  : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
             ADD_FM<0, 0x21>;
 def SUBu  : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
             ADD_FM<0, 0x23>;
 }
 let Defs = [HI0, LO0] in
 def MUL   : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
             ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
 def ADD   : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
 def SUB   : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
+let AdditionalPredicates = [NotInMicroMips] in {
 def SLT   : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
 def SLTu  : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
+}
 let AdditionalPredicates = [NotInMicroMips] in {
 def AND   : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
             ADD_FM<0, 0x24>;
 def OR    : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
             ADD_FM<0, 0x25>;
 def XOR   : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
             ADD_FM<0, 0x26>;
 }

 def : MipsInstAlias<"not $rt, $rs",
                     (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
 def : MipsInstAlias<"neg $rt, $rs",
                     (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
 def : MipsInstAlias<"negu $rt",
                     (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
 def : MipsInstAlias<"negu $rt, $rs",
                     (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
+let Predicates = [NotInMicroMips] in {
 def : MipsInstAlias<
           "slt $rs, $rt, $imm",
           (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
+}
 def : MipsInstAlias<
           "sltu $rt, $rs, $imm",
           (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
 def : MipsInstAlias<
           "xor $rs, $rt, $imm",
           (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
 def : MipsInstAlias<
           "xor $rs, $imm",

 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
                         Instruction SLTiuOp> {
   def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
                 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
   def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
                 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
 }
 
+let AdditionalPredicates = [NotInMicroMips] in {
 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
 defm : SetlePats<GPR32, SLT, SLTu>;
 defm : SetgtPats<GPR32, SLT, SLTu>;
 defm : SetgePats<GPR32, SLT, SLTu>;
+}
 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
 
 // bswap pattern
 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
 
 // Load halfword/word patterns.
 let AddedComplexity = 40 in {
   def : LoadRegImmPat<LBu, i32, zextloadi8>;

llvm/trunk/test/CodeGen/Mips/brconlt.ll

 ; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6
 
 @i = global i32 5, align 4
 @j = global i32 10, align 4
 @k = global i32 5, align 4
 @result = global i32 0, align 4
 
 define void @test() nounwind {
 entry:
   %0 = load i32, i32* @j, align 4
   %1 = load i32, i32* @i, align 4
   %cmp = icmp slt i32 %0, %1
   br i1 %cmp, label %if.end, label %if.then
 
 ; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
+; MM32R6:   slt ${{[0-9]+}}, ${{[0-9]+}}
 ; 16: btnez $[[LABEL:[0-9A-Ba-b_]+]]
 ; 16: $[[LABEL]]:
 
 if.then:                                          ; preds = %entry
   store i32 1, i32* @result, align 4
   br label %if.end
 
 if.end:                                           ; preds = %entry, %if.then
   ret void
 }
 
 

llvm/trunk/test/CodeGen/Mips/seteq.ll

 ; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
 
 @i = global i32 1, align 4
 @j = global i32 10, align 4
 @k = global i32 1, align 4
 @r1 = common global i32 0, align 4
 @r2 = common global i32 0, align 4
 
 define void @test() nounwind {
 entry:
   %0 = load i32, i32* @i, align 4
   %1 = load i32, i32* @k, align 4
   %cmp = icmp eq i32 %0, %1
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
 ; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
 ; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
+; MMR6:   sltiu   ${{[0-9]+}}, ${{[0-9]+}}, 1
 ; 16: move  ${{[0-9]+}}, $24
   ret void
 }
 

llvm/trunk/test/CodeGen/Mips/setltk.ll

 ; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6
 
 @j = global i32 -5, align 4
 @k = global i32 10, align 4
 @l = global i32 20, align 4
 @m = global i32 10, align 4
 @r1 = common global i32 0, align 4
 @r2 = common global i32 0, align 4
 @r3 = common global i32 0, align 4
 
 define void @test() nounwind {
 entry:
   %0 = load i32, i32* @j, align 4
   %cmp = icmp slt i32 %0, 10
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
-; 16: slti  $[[REGISTER:[0-9]+]], 10
-; 16: move  $[[REGISTER]], $24
+; 16:     slti  $[[REGISTER:[0-9]+]], 10
+; MM32R6:   slti    $[[REGISTER:[0-9]+]], $[[REGISTER:[0-9]+]], 10
+; 16:     move  $[[REGISTER]], $24
   ret void
 }

llvm/trunk/test/CodeGen/Mips/setne.ll

 ; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
 
 @i = global i32 1, align 4
 @j = global i32 10, align 4
 @k = global i32 1, align 4
 @r1 = common global i32 0, align 4
 @r2 = common global i32 0, align 4
 
 define void @test() nounwind {
 entry:
   %0 = load i32, i32* @i, align 4
   %1 = load i32, i32* @k, align 4
   %cmp = icmp ne i32 %0, %1
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
 ; 16: xor $[[REGISTER:[0-9]+]], ${{[0-9]+}}
 ; 16: sltu  ${{[0-9]+}}, $[[REGISTER]]
+; MMR6: sltu    ${{[0-9]+}}, $zero, ${{[0-9]+}}
 ; 16: move  ${{[0-9]+}}, $24
   ret void
 }

llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt

 0x54 0x44 0x3b 0x3b # CHECK: round.w.s $f2, $f4
 0x54 0x44 0x7b 0x3b # CHECK: round.w.d $f2, $f4
 0x54 0x41 0x08 0xb8 # CHECK: sel.s $f1, $f1, $f2
 0x54 0x82 0x02 0xb8 # CHECK: sel.d $f0, $f2, $f4
 0x54 0x62 0x08 0x38 # CHECK: seleqz.s $f1, $f2, $f3
 0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8
 0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3
 0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8
+0x00 0xa4 0x1b 0x50 # CHECK: slt $3, $4, $5
+0x90 0x64 0x01 0x00 # CHECK: slti $3, $4, 256
+0xb0 0x64 0x01 0x00 # CHECK: sltiu $3, $4, 256
+0x00 0xa4 0x1b 0x90 # CHECK: sltu $3, $4, $5
 0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3
 0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
 0x00 0x00 0x47 0x7c # CHECK: di
 0x00 0x0f 0x47 0x7c # CHECK: di $15
 0x00 0x00 0x43 0x7c # CHECK: tlbinv
 0x00 0x00 0x53 0x7c # CHECK: tlbinvf
 0x00 0xa9 0x02 0xfc # CHECK: mtc0 $5, $9, 0
 0x00 0xa9 0x02 0xfc # CHECK: mtc0 $5, $9

llvm/trunk/test/MC/Mips/micromips32r6/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
   round.w.s $f2, $f4       # CHECK: round.w.s $f2, $f4  # encoding: [0x54,0x44,0x3b,0x3b]
   round.w.d $f2, $f4       # CHECK: round.w.d $f2, $f4  # encoding: [0x54,0x44,0x7b,0x3b]
   sel.s $f1, $f1, $f2      # CHECK: sel.s $f1, $f1, $f2 # encoding: [0x54,0x41,0x08,0xb8]
   sel.d $f0, $f2, $f4      # CHECK: sel.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x02,0xb8]
   seleqz.s $f1, $f2, $f3   # CHECK: seleqz.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x38]
   seleqz.d $f2, $f4, $f8   # CHECK: seleqz.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x38]
   selnez.s $f1, $f2, $f3   # CHECK: selnez.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x78]
   selnez.d $f2, $f4, $f8   # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78]
+  slt $3, $4, $5           # CHECK: slt $3, $4, $5         # encoding: [0x00,0xa4,0x1b,0x50]
+  slti $3, $4, 256         # CHECK: slti $3, $4, 256       # encoding: [0x90,0x64,0x01,0x00]
+  sltiu $3, $4, 256        # CHECK: sltiu $3, $4, 256      # encoding: [0xb0,0x64,0x01,0x00]
+  sltu $3, $4, $5          # CHECK: sltu $3, $4, $5        # encoding: [0x00,0xa4,0x1b,0x90]
   class.s $f2, $f3         # CHECK: class.s $f2, $f3       # encoding: [0x54,0x62,0x00,0x60]
   class.d $f2, $f4         # CHECK: class.d $f2, $f4       # encoding: [0x54,0x82,0x02,0x60]
   deret                    # CHECK: deret                  # encoding: [0x00,0x00,0xe3,0x7c]
   tlbinv                   # CHECK: tlbinv                 # encoding: [0x00,0x00,0x43,0x7c]
   tlbinvf                  # CHECK: tlbinvf                # encoding: [0x00,0x00,0x53,0x7c]
   mtc0 $5, $9              # CHECK: mtc0 $5, $9, 0         # encoding: [0x00,0xa9,0x02,0xfc]
   mtc0 $1, $2, 7           # CHECK: mtc0 $1, $2, 7         # encoding: [0x00,0x22,0x3a,0xfc]
   mtc1 $3, $f4             # CHECK: mtc1 $3, $f4           # encoding: [0x54,0x64,0x28,0x3b]