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Differential D19150

[mips][microMIPS] Implement LL, SC, MOVEP, ROTR, ROTRV and SYSCALL instructions and add tests for LWM32 and SWM32
ClosedPublic

Authored by zbuljan on Apr 15 2016, 12:14 AM.

Details

Reviewers
dsanders
sdardis
vkalintiris
zoran.jovanovic
hvarga
Commits
rL266977: [mips][microMIPS] Implement LL, SC, MOVEP, ROTR, ROTRV and SYSCALL…
Summary

The patch implements microMIPSr6 LL, SC, MOVEP, ROTR, ROTRV and SYSCALL instructions and add tests for LWM32 and SWM32.

Diff Detail

Repository
rL LLVM

Event Timeline

zbuljan updated this revision to Diff 53850.Apr 15 2016, 12:14 AM
zbuljan retitled this revision from to [mips][microMIPS] Implement LL, SC, LWM32, SWM32, MOVEP, ROTR, ROTRV and SYSCALL instructions.
zbuljan updated this object.
zbuljan added reviewers: dsanders, hvarga, zoran.jovanovic.
zbuljan added subscribers: petarj, llvm-commits.
Herald added a reviewer: vkalintiris. · View Herald TranscriptApr 15 2016, 12:14 AM
Herald added subscribers: sdardis, dsanders. · View Herald Transcript
sdardis requested changes to this revision.Apr 15 2016, 3:12 AM
sdardis added a reviewer: sdardis.

Minor nits. When adding to the */(in)valid.s test files can you integrate the new instructions in alphabetical order with existing instructions? Also, group instructions of a similar size.

I know the files themselves aren't wholly consistent with this, so it doesn't have to be perfect.

lib/Target/Mips/Mips32r6InstrInfo.td
792–799 ↗(On Diff #53850)

Join these blocks together.

test/MC/Disassembler/Mips/micromips32r6/valid.txt
279–289 ↗(On Diff #53850)

As these are not ASE or floating point specific microMIPS instructions, can you place them between lines 31-100 in alphabetical order? It's more consistent that way.

The movep should be placed in one of the 16 bit instruction blocks.

test/MC/Disassembler/Mips/micromips64r6/valid.txt
218–228 ↗(On Diff #53850)

Here too, just place these instructions with the 32bit instructions? move should be with the 16bit instructions.

test/MC/Mips/micromips32r6/invalid.s
136 ↗(On Diff #53850)

Can you add rotrv with an immediate operand here, syscall with a register operand, syscall with an out of range immediate? Finally please place the instructions in alphabetical order with the existing instructions depending on whether their are 32bit or 16bit long.

test/MC/Mips/micromips32r6/valid.s
278–299 ↗(On Diff #53850)

Try to integrate these into the first 100~ lines alphabetically.

This revision now requires changes to proceed.Apr 15 2016, 3:12 AM
zbuljan updated this revision to Diff 54357.Apr 20 2016, 6:11 AM
zbuljan edited edge metadata.

Rebased to work with TOT.
All tests (valid.s/valid.txt/invalid.s) sorted in alphabetical order.
Added invalid test for rotrv with an immediate operand.
Invalid tests for syscall with a register operand and syscall with an out of range immediate placed in invalid-wrong-error.s because they currently emit wrong error messages.

sdardis added a comment.Apr 20 2016, 7:45 AM

Sorry, I should have been clearer, when I said "place the instructions in alphabetical order", I mean the instructions you were adding, not the entire test file.

Just place the new tests at the bottom of the test files. Then submit the tests from this diff (54357) as two separate review requests, one containing the invalid/invalid-wrong-error/valid files, and the other with the disassembly tests.

Secondly, you've added tests for swm32 and lwm32. If that's all you're doing can you update the commit message + title to reflect that?

Thanks.

zbuljan updated this revision to Diff 54467.Apr 21 2016, 1:57 AM
zbuljan retitled this revision from [mips][microMIPS] Implement LL, SC, LWM32, SWM32, MOVEP, ROTR, ROTRV and SYSCALL instructions to [mips][microMIPS] Implement LL, SC, MOVEP, ROTR, ROTRV and SYSCALL instructions and add tests for LWM32 and SWM32.
zbuljan updated this object.
zbuljan edited edge metadata.

Rearranged tests according to comments from sdardis.

sdardis accepted this revision.Apr 21 2016, 2:56 AM
sdardis edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Apr 21 2016, 2:56 AM
Closed by commit rL266977: [mips][microMIPS] Implement LL, SC, MOVEP, ROTR, ROTRV and SYSCALL… (authored by zbuljan). · Explain WhyApr 21 2016, 4:07 AM
This revision was automatically updated to reflect the committed changes.
zbuljan mentioned this in D19857: [mips][microMIPS] Add CodeGen support for microMIPSr6 ROTR and ROTRV and add tests for LL, SC, SYSCALL, ROTR, ROTRV, LWM32, SWM32 and MOVEP instructions.May 3 2016, 12:09 AM

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
AsmParser/
10 lines
3 lines
8 lines
16 lines
test/
MC/
Disassembler/
Mips/
micromips32r3/
2 lines
2 lines
micromips32r6/
10 lines
micromips64r6/
10 lines
Mips/
micromips/
1 line
4 lines
micromips32r6/
3 lines
16 lines
22 lines
micromips64r6/
3 lines
16 lines
22 lines

Diff 54481

llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Show First 20 Lines • Show All 1,138 Lines • ▼ Show 20 Lines bool isMovePRegPair() const {
if ((R0 == Mips::A1 && R1 == Mips::A2) || if ((R0 == Mips::A1 && R1 == Mips::A2) ||
(R0 == Mips::A1 && R1 == Mips::A3) || (R0 == Mips::A1 && R1 == Mips::A3) ||
(R0 == Mips::A2 && R1 == Mips::A3) || (R0 == Mips::A2 && R1 == Mips::A3) ||
(R0 == Mips::A0 && R1 == Mips::S5) || (R0 == Mips::A0 && R1 == Mips::S5) ||
(R0 == Mips::A0 && R1 == Mips::S6) || (R0 == Mips::A0 && R1 == Mips::S6) ||
(R0 == Mips::A0 && R1 == Mips::A1) || (R0 == Mips::A0 && R1 == Mips::A1) ||
(R0 == Mips::A0 && R1 == Mips::A2) || (R0 == Mips::A0 && R1 == Mips::A2) ||
(R0 == Mips::A0 && R1 == Mips::A3)) (R0 == Mips::A0 && R1 == Mips::A3) ||
(R0 == Mips::A1_64 && R1 == Mips::A2_64) ||
(R0 == Mips::A1_64 && R1 == Mips::A3_64) ||
(R0 == Mips::A2_64 && R1 == Mips::A3_64) ||
(R0 == Mips::A0_64 && R1 == Mips::S5_64) ||
(R0 == Mips::A0_64 && R1 == Mips::S6_64) ||
(R0 == Mips::A0_64 && R1 == Mips::A1_64) ||
(R0 == Mips::A0_64 && R1 == Mips::A2_64) ||
(R0 == Mips::A0_64 && R1 == Mips::A3_64))
return true; return true;
return false; return false;
} }
StringRef getToken() const { StringRef getToken() const {
assert(Kind == k_Token && "Invalid access!"); assert(Kind == k_Token && "Invalid access!");
return StringRef(Tok.Data, Tok.Length); return StringRef(Tok.Data, Tok.Length);
▲ Show 20 Lines • Show All 5,247 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td

Show First 20 Lines • Show All 1,025 Lines • ▼ Show 20 Lines
def : MipsInstAlias<"tgeu $rs, $rt", def : MipsInstAlias<"tgeu $rs, $rt",
(TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : MipsInstAlias<"tlt $rs, $rt", def : MipsInstAlias<"tlt $rs, $rt",
(TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : MipsInstAlias<"tltu $rs, $rt", def : MipsInstAlias<"tltu $rs, $rt",
(TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : MipsInstAlias<"tne $rs, $rt", def : MipsInstAlias<"tne $rs, $rt",
(TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : MipsInstAlias<"rotr $rt, $imm",
(ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>;
def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>;
} }

llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td

Show First 20 Lines • Show All 752 Lines • ▼ Show 20 Lineslet AdditionalPredicates = [NotInMicroMips] in {
def DIV : R6MMR6Rel, DIV_ENC, DIV_DESC, ISA_MIPS32R6; def DIV : R6MMR6Rel, DIV_ENC, DIV_DESC, ISA_MIPS32R6;
def DIVU : R6MMR6Rel, DIVU_ENC, DIVU_DESC, ISA_MIPS32R6; def DIVU : R6MMR6Rel, DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
} }
def JIALC : R6MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6; def JIALC : R6MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6; def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6;
def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6; def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6; def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6;
}
def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6; def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6;
}
def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6; def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6;
def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6; def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6;
def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6; def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6; def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6, HARDFLOAT; def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6, HARDFLOAT; def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT; def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
Show All 17 Lines
def MUHU : R6MMR6Rel, MUHU_ENC, MUHU_DESC, ISA_MIPS32R6; def MUHU : R6MMR6Rel, MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
def MUL_R6 : R6MMR6Rel, MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6; def MUL_R6 : R6MMR6Rel, MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
def MULU : R6MMR6Rel, MULU_ENC, MULU_DESC, ISA_MIPS32R6; def MULU : R6MMR6Rel, MULU_ENC, MULU_DESC, ISA_MIPS32R6;
def NAL; // BAL with rd=0 def NAL; // BAL with rd=0
def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6; def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT; def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT; def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT;
}
def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6; def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in {
def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6; def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6;
} }
def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6; def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32; def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6, HARDFLOAT; def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6, HARDFLOAT; def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6, HARDFLOAT;
} }
def SELNEZ : R6MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32; def SELNEZ : R6MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
▲ Show 20 Lines • Show All 103 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Show First 20 Lines • Show All 1,699 Lines • ▼ Show 20 Lines
def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>, def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
SRLV_FM<4, 0>; SRLV_FM<4, 0>;
def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>, def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
SRLV_FM<6, 0>; SRLV_FM<6, 0>;
def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>, def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
SRLV_FM<7, 0>; SRLV_FM<7, 0>;
// Rotate Instructions // Rotate Instructions
let AdditionalPredicates = [NotInMicroMips] in {
def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr, def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
immZExt5>, immZExt5>,
SRA_FM<2, 1>, ISA_MIPS32R2; SRA_FM<2, 1>, ISA_MIPS32R2;
def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>, def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
SRLV_FM<6, 1>, ISA_MIPS32R2; SRLV_FM<6, 1>, ISA_MIPS32R2;
}
/// Load and Store Instructions /// Load and Store Instructions
/// aligned /// aligned
def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>; def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel, def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
LW_FM<0x24>; LW_FM<0x24>;
def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel, def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
LW_FM<0x21>; LW_FM<0x21>;
▲ Show 20 Lines • Show All 497 Lines • ▼ Show 20 Lines
def : MipsInstAlias<"bnez $rs,$offset", def : MipsInstAlias<"bnez $rs,$offset",
(BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
def : MipsInstAlias<"bnezl $rs,$offset", def : MipsInstAlias<"bnezl $rs,$offset",
(BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; (BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
def : MipsInstAlias<"beqz $rs,$offset", def : MipsInstAlias<"beqz $rs,$offset",
(BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
def : MipsInstAlias<"beqzl $rs,$offset", def : MipsInstAlias<"beqzl $rs,$offset",
(BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"syscall", (SYSCALL 0), 1>; def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
}
def : MipsInstAlias<"break", (BREAK 0, 0), 1>; def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>; def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2; def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;
def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2; def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
} }
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
▲ Show 20 Lines • Show All 408 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt

Show First 20 Lines • Show All 183 Lines • ▼ Show 20 Lines
0xa4 0x60 0x08 0xaa # CHECK: she $5, 8($4) 0xa4 0x60 0x08 0xaa # CHECK: she $5, 8($4)
0xa4 0x60 0x08 0xae # CHECK: swe $5, 8($4) 0xa4 0x60 0x08 0xae # CHECK: swe $5, 8($4)
0x03 0x63 0x05 0xa2 # CHECK: swre $24, 5($3) 0x03 0x63 0x05 0xa2 # CHECK: swre $24, 5($3)
0x03 0x63 0x05 0xa0 # CHECK: swle $24, 5($3) 0x03 0x63 0x05 0xa0 # CHECK: swle $24, 5($3)
0x03 0x63 0x05 0x66 # CHECK: lwre $24, 5($3) 0x03 0x63 0x05 0x66 # CHECK: lwre $24, 5($3)
0x04 0x63 0x02 0x64 # CHECK: lwle $24, 2($4) 0x04 0x63 0x02 0x64 # CHECK: lwle $24, 2($4)
0x44 0x60 0x08 0x6c # CHECK: lle $2, 8($4) 0x44 0x60 0x08 0x6c # CHECK: lle $2, 8($4)
0x44 0x60 0x08 0xac # CHECK: sce $2, 8($4) 0x44 0x60 0x08 0xac # CHECK: sce $2, 8($4)
0x00 0x00 0x7c 0x8b # CHECK: syscall
0x8c 0x01 0x7c 0x8b # CHECK: syscall 396

llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt

Show First 20 Lines • Show All 183 Lines • ▼ Show 20 Lines
0x60 0xa4 0xaa 0x08 # CHECK: she $5, 8($4) 0x60 0xa4 0xaa 0x08 # CHECK: she $5, 8($4)
0x60 0xa4 0xae 0x08 # CHECK: swe $5, 8($4) 0x60 0xa4 0xae 0x08 # CHECK: swe $5, 8($4)
0x63 0x03 0xa2 0x05 # CHECK: swre $24, 5($3) 0x63 0x03 0xa2 0x05 # CHECK: swre $24, 5($3)
0x63 0x03 0xa0 0x05 # CHECK: swle $24, 5($3) 0x63 0x03 0xa0 0x05 # CHECK: swle $24, 5($3)
0x63 0x03 0x66 0x05 # CHECK: lwre $24, 5($3) 0x63 0x03 0x66 0x05 # CHECK: lwre $24, 5($3)
0x63 0x04 0x64 0x02 # CHECK: lwle $24, 2($4) 0x63 0x04 0x64 0x02 # CHECK: lwle $24, 2($4)
0x60 0x44 0x6c 0x08 # CHECK: lle $2, 8($4) 0x60 0x44 0x6c 0x08 # CHECK: lle $2, 8($4)
0x60 0x44 0xac 0x08 # CHECK: sce $2, 8($4) 0x60 0x44 0xac 0x08 # CHECK: sce $2, 8($4)
0x00 0x00 0x8b 0x7c # CHECK: syscall
0x01 0x8c 0x8b 0x7c # CHECK: syscall 396

llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt

Show All 15 Lines
0x45 0x23 # CHECK: jrc16 $9 0x45 0x23 # CHECK: jrc16 $9
0x44 0xb3 # CHECK: jrcaddiusp 20 0x44 0xb3 # CHECK: jrcaddiusp 20
0x65 0x88 # CHECK: lw $3, 32($gp) 0x65 0x88 # CHECK: lw $3, 32($gp)
0x48 0x66 # CHECK: lw $3, 24($sp) 0x48 0x66 # CHECK: lw $3, 24($sp)
0x6a 0x12 # CHECK: lw16 $4, 8($17) 0x6a 0x12 # CHECK: lw16 $4, 8($17)
0x29 0x82 # CHECK: lhu16 $3, 4($16) 0x29 0x82 # CHECK: lhu16 $3, 4($16)
0x09 0x94 # CHECK: lbu16 $3, 4($17) 0x09 0x94 # CHECK: lbu16 $3, 4($17)
0x09 0x9f # CHECK: lbu16 $3, -1($17) 0x09 0x9f # CHECK: lbu16 $3, -1($17)
0x84 0x34 # CHECK: movep $5, $6, $2, $3
0x04 0xcc # CHECK: addu16 $6, $17, $4 0x04 0xcc # CHECK: addu16 $6, $17, $4
0x44 0x21 # CHECK: and16 $16, $2 0x44 0x21 # CHECK: and16 $16, $2
0x2e 0x56 # CHECK: andi16 $4, $5, 8 0x2e 0x56 # CHECK: andi16 $4, $5, 8
0x46 0x70 # CHECK: not16 $4, $7 0x46 0x70 # CHECK: not16 $4, $7
0x45 0xf9 # CHECK: or16 $3, $7 0x45 0xf9 # CHECK: or16 $3, $7
0x25 0xe0 # CHECK: sll16 $3, $6, 8 0x25 0xe0 # CHECK: sll16 $3, $6, 8
0x25 0xe1 # CHECK: srl16 $3, $6, 8 0x25 0xe1 # CHECK: srl16 $3, $6, 8
0x00 0xa4 0x19 0x10 # CHECK: add $3, $4, $5 0x00 0xa4 0x19 0x10 # CHECK: add $3, $4, $5
Show All 36 Lines
0x00 0xa4 0x19 0x98 # CHECK: divu $3, $4, $5 0x00 0xa4 0x19 0x98 # CHECK: divu $3, $4, $5
0x00 0x00 0x18 0x00 # CHECK: ehb 0x00 0x00 0x18 0x00 # CHECK: ehb
0x00 0x00 0x57 0x7c # CHECK: ei 0x00 0x00 0x57 0x7c # CHECK: ei
0x00 0x0a 0x57 0x7c # CHECK: ei $10 0x00 0x0a 0x57 0x7c # CHECK: ei $10
0x00 0x00 0xf3 0x7c # CHECK: eret 0x00 0x00 0xf3 0x7c # CHECK: eret
0x00 0x01 0xf3 0x7c # CHECK: eretnc 0x00 0x01 0xf3 0x7c # CHECK: eretnc
0x80 0x05 0x01 0x00 # CHECK: jialc $5, 256 0x80 0x05 0x01 0x00 # CHECK: jialc $5, 256
0xa0 0x05 0x01 0x00 # CHECK: jic $5, 256 0xa0 0x05 0x01 0x00 # CHECK: jic $5, 256
0x60 0x44 0x30 0x08 # CHECK: ll $2, 8($4)
0x20 0x44 0x50 0x08 # CHECK: lwm32 $16, $17, 8($4)
0x21 0x3b 0x59 0x84 # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, -1660($27)
0x01 0x26 0x38 0xc0 # CHECK: rotr $9, $6, 7
0x00 0xc7 0x48 0xd0 # CHECK: rotrv $9, $6, $7
0x60 0x44 0xb0 0x08 # CHECK: sc $2, 8($4)
0x20 0x44 0xd0 0x08 # CHECK: swm32 $16, $17, 8($4)
0x00 0x00 0x8b 0x7c # CHECK: syscall
0x01 0x8c 0x8b 0x7c # CHECK: syscall 396
0xbd 0x0a 0x01 0x2c # CHECK: ldc1 $f8, 300($10) 0xbd 0x0a 0x01 0x2c # CHECK: ldc1 $f8, 300($10)
0x21 0x6c 0x23 0xff # CHECK: ldc2 $11, 1023($12) 0x21 0x6c 0x23 0xff # CHECK: ldc2 $11, 1023($12)
0x78 0x48 0x00 0x43 # CHECK: lwpc $2, 268 0x78 0x48 0x00 0x43 # CHECK: lwpc $2, 268
0x00 0x43 0x26 0x0f # CHECK: lsa $2, $3, $4, 4 0x00 0x43 0x26 0x0f # CHECK: lsa $2, $3, $4, 4
0x00 0xa4 0x19 0x58 # CHECK: mod $3, $4, $5 0x00 0xa4 0x19 0x58 # CHECK: mod $3, $4, $5
0x00 0xa4 0x19 0xd8 # CHECK: modu $3, $4, $5 0x00 0xa4 0x19 0xd8 # CHECK: modu $3, $4, $5
0x00 0xa4 0x18 0x18 # CHECK: mul $3, $4, $5 0x00 0xa4 0x18 0x18 # CHECK: mul $3, $4, $5
0x00 0xa4 0x18 0x58 # CHECK: muh $3, $4, $5 0x00 0xa4 0x18 0x58 # CHECK: muh $3, $4, $5
▲ Show 20 Lines • Show All 207 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt

Show All 15 Lines
0x48 0x66 # CHECK: lw $3, 24($sp) 0x48 0x66 # CHECK: lw $3, 24($sp)
0x6a 0x12 # CHECK: lw16 $4, 8($17) 0x6a 0x12 # CHECK: lw16 $4, 8($17)
0x29 0x82 # CHECK: lhu16 $3, 4($16) 0x29 0x82 # CHECK: lhu16 $3, 4($16)
0x09 0x94 # CHECK: lbu16 $3, 4($17) 0x09 0x94 # CHECK: lbu16 $3, 4($17)
0x09 0x9f # CHECK: lbu16 $3, -1($17) 0x09 0x9f # CHECK: lbu16 $3, -1($17)
0x45 0x2b # CHECK: jalr $9 0x45 0x2b # CHECK: jalr $9
0x45 0x23 # CHECK: jrc16 $9 0x45 0x23 # CHECK: jrc16 $9
0x44 0xb3 # CHECK: jrcaddiusp 20 0x44 0xb3 # CHECK: jrcaddiusp 20
0x84 0x34 # CHECK: movep $5, $6, $2, $3
0x60 0x44 0x30 0x08 # CHECK: ll $2, 8($4)
0x20 0x44 0x50 0x08 # CHECK: lwm32 $16, $17, 8($4)
0x21 0x3b 0x59 0x84 # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, -1660($27)
0x01 0x26 0x38 0xc0 # CHECK: rotr $9, $6, 7
0x00 0xc7 0x48 0xd0 # CHECK: rotrv $9, $6, $7
0x60 0x44 0xb0 0x08 # CHECK: sc $2, 8($4)
0x20 0x44 0xd0 0x08 # CHECK: swm32 $16, $17, 8($4)
0x00 0x00 0x8b 0x7c # CHECK: syscall
0x01 0x8c 0x8b 0x7c # CHECK: syscall 396
0xf0 0x64 0x00 0x05 # CHECK: daui $3, $4, 5 0xf0 0x64 0x00 0x05 # CHECK: daui $3, $4, 5
0x42 0x23 0x00 0x04 # CHECK: dahi $3, 4 0x42 0x23 0x00 0x04 # CHECK: dahi $3, 4
0x42 0x03 0x00 0x04 # CHECK: dati $3, 4 0x42 0x03 0x00 0x04 # CHECK: dati $3, 4
0x59 0x26 0x30 0xec # CHECK: dext $9, $6, 3, 7 0x59 0x26 0x30 0xec # CHECK: dext $9, $6, 3, 7
0x59 0x26 0x30 0xe4 # CHECK: dextm $9, $6, 3, 39 0x59 0x26 0x30 0xe4 # CHECK: dextm $9, $6, 3, 39
0x59 0x26 0x30 0xd4 # CHECK: dextu $9, $6, 35, 7 0x59 0x26 0x30 0xd4 # CHECK: dextu $9, $6, 35, 7
0x58 0x43 0x25 0x1c # CHECK: dalign $4, $2, $3, 5 0x58 0x43 0x25 0x1c # CHECK: dalign $4, $2, $3, 5
0x58 0xa4 0x19 0x18 # CHECK: ddiv $3, $4, $5 0x58 0xa4 0x19 0x18 # CHECK: ddiv $3, $4, $5
▲ Show 20 Lines • Show All 186 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/micromips/invalid-wrong-error.s

# Instructions that are correctly rejected but emit a wrong or misleading error. # Instructions that are correctly rejected but emit a wrong or misleading error.
# RUN: not llvm-mc %s -triple=mips -show-encoding -mattr=micromips 2>%t1 # RUN: not llvm-mc %s -triple=mips -show-encoding -mattr=micromips 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
# The 20-bit immediate supported by the standard encodings cause us to emit # The 20-bit immediate supported by the standard encodings cause us to emit
# the diagnostic for the 20-bit form. This isn't exactly wrong but it is # the diagnostic for the 20-bit form. This isn't exactly wrong but it is
# misleading. Ideally, we'd emit every way to achieve a valid match instead # misleading. Ideally, we'd emit every way to achieve a valid match instead
# of picking only one. # of picking only one.
sdbbp -1 # CHECK: :[[@LINE]]:9: error: expected 20-bit unsigned immediate sdbbp -1 # CHECK: :[[@LINE]]:9: error: expected 20-bit unsigned immediate
sdbbp 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled sdbbp 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
syscall -1 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate syscall -1 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
syscall $4 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
syscall 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled syscall 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled

llvm/trunk/test/MC/Mips/micromips/invalid.s

Show All 33 Lines# RUN: FileCheck %s < %t1
jraddiusp 125 # CHECK: :[[@LINE]]:13: error: expected both 7-bit unsigned immediate and multiple of 4 jraddiusp 125 # CHECK: :[[@LINE]]:13: error: expected both 7-bit unsigned immediate and multiple of 4
jraddiusp 128 # CHECK: :[[@LINE]]:13: error: expected both 7-bit unsigned immediate and multiple of 4 jraddiusp 128 # CHECK: :[[@LINE]]:13: error: expected both 7-bit unsigned immediate and multiple of 4
li16 $4, -2 # CHECK: :[[@LINE]]:12: error: expected immediate in range -1 .. 126 li16 $4, -2 # CHECK: :[[@LINE]]:12: error: expected immediate in range -1 .. 126
li16 $4, 127 # CHECK: :[[@LINE]]:12: error: expected immediate in range -1 .. 126 li16 $4, 127 # CHECK: :[[@LINE]]:12: error: expected immediate in range -1 .. 126
pref -1, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate pref -1, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
pref 32, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate pref 32, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
prefe 0, -513($7) # CHECK: :[[@LINE]]:12: error: expected memory with 9-bit signed offset prefe 0, -513($7) # CHECK: :[[@LINE]]:12: error: expected memory with 9-bit signed offset
prefe 0, 512($7) # CHECK: :[[@LINE]]:12: error: expected memory with 9-bit signed offset prefe 0, 512($7) # CHECK: :[[@LINE]]:12: error: expected memory with 9-bit signed offset
rotr $2, -1 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
rotr $2, 32 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
rotr $2, $3, -1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
rotrv $9, $6, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
sdbbp16 -1 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate sdbbp16 -1 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate
sdbbp16 16 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate sdbbp16 16 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate
sll $2, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate sll $2, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
sll $2, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate sll $2, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
sra $2, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate sra $2, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
sra $2, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate sra $2, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
srl $2, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate srl $2, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
srl $2, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate srl $2, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
sync -1 # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate sync -1 # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
sync 32 # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate sync 32 # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
swe $2, -513($gp) # CHECK: :[[@LINE]]:11: error: expected memory with $gp and 9-bit signed offset swe $2, -513($gp) # CHECK: :[[@LINE]]:11: error: expected memory with $gp and 9-bit signed offset
swe $2, 512($gp) # CHECK: :[[@LINE]]:11: error: expected memory with $gp and 9-bit signed offset swe $2, 512($gp) # CHECK: :[[@LINE]]:11: error: expected memory with $gp and 9-bit signed offset

llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s

Show All 21 Lines# RUN: FileCheck %s < %t1
tlt $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate tlt $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
tlt $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled tlt $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
tltu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate tltu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate
tltu $8, $9, -1 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate tltu $8, $9, -1 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate
tltu $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled tltu $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
tne $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate tne $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
tne $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate tne $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
tne $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled tne $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
syscall -1 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
syscall $4 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
syscall 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled

llvm/trunk/test/MC/Mips/micromips32r6/invalid.s

Show First 20 Lines • Show All 115 Lines • ▼ Show 20 Lines# RUN: FileCheck %s < %t1
mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mthc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mthc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mfc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mfc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mfc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mfc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mfhc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mfhc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mfhc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mfhc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
lwm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
lwm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
lwm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $24, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
movep $5, $6, $2, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
movep $5, $6, $5, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
movep $5, $21, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
movep $8, $6, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
rotr $2, -1 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
rotr $2, 32 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
rotr $2, $3, -1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
rotrv $9, $6, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
swm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand

llvm/trunk/test/MC/Mips/micromips32r6/valid.s

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
jrc16 $9 # CHECK: jrc16 $9 # encoding: [0x45,0x23] jrc16 $9 # CHECK: jrc16 $9 # encoding: [0x45,0x23]
jrcaddiusp 20 # CHECK: jrcaddiusp 20 # encoding: [0x44,0xb3] jrcaddiusp 20 # CHECK: jrcaddiusp 20 # encoding: [0x44,0xb3]
ldc1 $f8, 300($10) # CHECK: ldc1 $f8, 300($10) # encoding: [0xbd,0x0a,0x01,0x2c] ldc1 $f8, 300($10) # CHECK: ldc1 $f8, 300($10) # encoding: [0xbd,0x0a,0x01,0x2c]
ldc2 $11, 1023($12) # CHECK: ldc2 $11, 1023($12) # encoding: [0x21,0x6c,0x23,0xff] ldc2 $11, 1023($12) # CHECK: ldc2 $11, 1023($12) # encoding: [0x21,0x6c,0x23,0xff]
lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x43,0x24,0x0f] lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x43,0x24,0x0f]
lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0x78,0x48,0x00,0x43] lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0x78,0x48,0x00,0x43]
lwm $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22] lwm $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
lwm16 $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22] lwm16 $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
ll $2, 8($4) # CHECK: ll $2, 8($4) # encoding: [0x60,0x44,0x30,0x08]
lwm32 $16, $17, 8($4) # CHECK: lwm32 $16, $17, 8($4) # encoding: [0x20,0x44,0x50,0x08]
lwm32 $16, $17, 8($sp) # CHECK: lwm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0x50,0x08]
lwm32 $16, $17, $ra, 8($4) # CHECK: lwm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0x50,0x08]
lwm32 $16, $17, $ra, 64($sp) # CHECK: lwm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0x50,0x40]
lwm32 $16, $17, $18, $19, 8($4) # CHECK: lwm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0x50,0x08]
lwm32 $16, $17, $18, $19, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $ra, 8($4) # encoding: [0x22,0x84,0x50,0x08]
lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # encoding: [0x21,0x24,0x50,0x08]
lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3 # encoding: [0x84,0x34]
rotr $2, 7 # CHECK: rotr $2, $2, 7 # encoding: [0x00,0x42,0x38,0xc0]
rotr $9, $6, 7 # CHECK: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0]
rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
sc $2, 8($4) # CHECK: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08]
swm32 $16, $17, 8($4) # CHECK: swm32 $16, $17, 8($4) # encoding: [0x20,0x44,0xd0,0x08]
swm32 $16, $17, 8($sp) # CHECK: swm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0xd0,0x08]
swm32 $16, $17, $ra, 8($4) # CHECK: swm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0xd0,0x08]
swm32 $16, $17, $ra, 64($sp) # CHECK: swm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0xd0,0x40]
swm32 $16, $17, $18, $19, 8($4) # CHECK: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0xd0,0x08]
syscall # CHECK: syscall # encoding: [0x00,0x00,0x8b,0x7c]
syscall 396 # CHECK: syscall 396 # encoding: [0x01,0x8c,0x8b,0x7c]
mod $3, $4, $5 # CHECK: mod $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x58] mod $3, $4, $5 # CHECK: mod $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x58]
modu $3, $4, $5 # CHECK: modu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd8] modu $3, $4, $5 # CHECK: modu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd8]
mul $3, $4, $5 # CHECK mul $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x18] mul $3, $4, $5 # CHECK mul $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x18]
muh $3, $4, $5 # CHECK muh $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x58] muh $3, $4, $5 # CHECK muh $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x58]
mulu $3, $4, $5 # CHECK mulu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x98] mulu $3, $4, $5 # CHECK mulu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x98]
muhu $3, $4, $5 # CHECK muhu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xd8] muhu $3, $4, $5 # CHECK muhu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xd8]
nop # CHECK: nop # encoding: [0x00,0x00,0x00,0x00] nop # CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
nor $3, $4, $5 # CHECK: nor $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0xd0] nor $3, $4, $5 # CHECK: nor $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0xd0]
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llvm/trunk/test/MC/Mips/micromips64r6/invalid-wrong-error.s

Show All 21 Lines# RUN: FileCheck %s < %t1
tltu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate tltu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate
tltu $8, $9, -1 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate tltu $8, $9, -1 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate
tltu $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled tltu $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
tne $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate tne $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
tne $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate tne $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
tne $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled tne $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
dins $2, $3, -1, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate dins $2, $3, -1, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
dins $2, $3, 32, 1 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled dins $2, $3, 32, 1 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
syscall -1 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
syscall $4 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
syscall 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled

llvm/trunk/test/MC/Mips/micromips64r6/invalid.s

Show First 20 Lines • Show All 140 Lines • ▼ Show 20 Lines# RUN: FileCheck %s < %t1
mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mthc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mthc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
dmtc0 $4, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate dmtc0 $4, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
dmtc0 $4, $3, 8 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate dmtc0 $4, $3, 8 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
dmfc0 $4, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate dmfc0 $4, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
dmfc0 $4, $3, 8 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate dmfc0 $4, $3, 8 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
lwm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
lwm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
lwm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $24, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
movep $5, $6, $2, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
movep $5, $6, $5, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
movep $5, $21, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
movep $8, $6, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
rotr $2, -1 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
rotr $2, 32 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
rotr $2, $3, -1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
rotrv $9, $6, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
swm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand

llvm/trunk/test/MC/Mips/micromips64r6/valid.s

Show All 21 Linesa:
dextu $9, $6, 35, 7 # CHECK: dextu $9, $6, 35, 7 # encoding: [0x59,0x26,0x30,0xd4] dextu $9, $6, 35, 7 # CHECK: dextu $9, $6, 35, 7 # encoding: [0x59,0x26,0x30,0xd4]
dalign $4, $2, $3, 5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x58,0x43,0x25,0x1c] dalign $4, $2, $3, 5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x58,0x43,0x25,0x1c]
lw $3, 32($gp) # CHECK: lw $3, 32($gp) # encoding: [0x65,0x88] lw $3, 32($gp) # CHECK: lw $3, 32($gp) # encoding: [0x65,0x88]
lw $3, 24($sp) # CHECK: lw $3, 24($sp) # encoding: [0x48,0x66] lw $3, 24($sp) # CHECK: lw $3, 24($sp) # encoding: [0x48,0x66]
lw16 $4, 8($17) # CHECK: lw16 $4, 8($17) # encoding: [0x6a,0x12] lw16 $4, 8($17) # CHECK: lw16 $4, 8($17) # encoding: [0x6a,0x12]
lhu16 $3, 4($16) # CHECK: lhu16 $3, 4($16) # encoding: [0x29,0x82] lhu16 $3, 4($16) # CHECK: lhu16 $3, 4($16) # encoding: [0x29,0x82]
lbu16 $3, 4($17) # CHECK: lbu16 $3, 4($17) # encoding: [0x09,0x94] lbu16 $3, 4($17) # CHECK: lbu16 $3, 4($17) # encoding: [0x09,0x94]
lbu16 $3, -1($17) # CHECK: lbu16 $3, -1($17) # encoding: [0x09,0x9f] lbu16 $3, -1($17) # CHECK: lbu16 $3, -1($17) # encoding: [0x09,0x9f]
movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3 # encoding: [0x84,0x34]
ll $2, 8($4) # CHECK: ll $2, 8($4) # encoding: [0x60,0x44,0x30,0x08]
lwm32 $16, $17, 8($4) # CHECK: lwm32 $16, $17, 8($4) # encoding: [0x20,0x44,0x50,0x08]
lwm32 $16, $17, 8($sp) # CHECK: lwm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0x50,0x08]
lwm32 $16, $17, $ra, 8($4) # CHECK: lwm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0x50,0x08]
lwm32 $16, $17, $ra, 64($sp) # CHECK: lwm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0x50,0x40]
lwm32 $16, $17, $18, $19, 8($4) # CHECK: lwm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0x50,0x08]
lwm32 $16, $17, $18, $19, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $ra, 8($4) # encoding: [0x22,0x84,0x50,0x08]
lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # encoding: [0x21,0x24,0x50,0x08]
lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
rotr $2, 7 # CHECK: rotr $2, $2, 7 # encoding: [0x00,0x42,0x38,0xc0]
rotr $9, $6, 7 # CHECK: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0]
rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
sc $2, 8($4) # CHECK: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08]
swm32 $16, $17, 8($4) # CHECK: swm32 $16, $17, 8($4) # encoding: [0x20,0x44,0xd0,0x08]
swm32 $16, $17, 8($sp) # CHECK: swm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0xd0,0x08]
swm32 $16, $17, $ra, 8($4) # CHECK: swm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0xd0,0x08]
swm32 $16, $17, $ra, 64($sp) # CHECK: swm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0xd0,0x40]
swm32 $16, $17, $18, $19, 8($4) # CHECK: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0xd0,0x08]
syscall # CHECK: syscall # encoding: [0x00,0x00,0x8b,0x7c]
syscall 396 # CHECK: syscall 396 # encoding: [0x01,0x8c,0x8b,0x7c]
ddiv $3, $4, $5 # CHECK: ddiv $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x18] ddiv $3, $4, $5 # CHECK: ddiv $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x18]
dmod $3, $4, $5 # CHECK: dmod $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x58] dmod $3, $4, $5 # CHECK: dmod $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x58]
ddivu $3, $4, $5 # CHECK: ddivu $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x98] ddivu $3, $4, $5 # CHECK: ddivu $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x98]
dmodu $3, $4, $5 # CHECK: dmodu $3, $4, $5 # encoding: [0x58,0xa4,0x19,0xd8] dmodu $3, $4, $5 # CHECK: dmodu $3, $4, $5 # encoding: [0x58,0xa4,0x19,0xd8]
add.s $f3, $f4, $f5 # CHECK: add.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x30] add.s $f3, $f4, $f5 # CHECK: add.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x30]
add.d $f2, $f4, $f6 # CHECK: add.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x30] add.d $f2, $f4, $f6 # CHECK: add.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x30]
sub.s $f3, $f4, $f5 # CHECK: sub.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x70] sub.s $f3, $f4, $f5 # CHECK: sub.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x70]
sub.d $f2, $f4, $f6 # CHECK: sub.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x70] sub.d $f2, $f4, $f6 # CHECK: sub.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x70]
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