[SystemZ] Support conditional sibling calls via BRCL.

[• koriakin]

Summary

This adds a conditional variant of CallJG instruction, CallBRCL.
It can be used for conditional sibling calls. Unfortunately, due
to IfCvt limitations, it only really works well for functions without
arguments.

[• koriakin]

This is the third patch for issue #23417 - direct conditional sibling calls. Compare and branch instructions are of no use here, as they have limitted reach. This is not as useful as I hoped, as it usually only triggers for calls without parameters - eg. for f3 in the attached test, IfCvt bails on the llhi instruction loading the parameter, even after I make all the IsIfCvt*Profitable functions always return true.

I'll also submit a 4th patch for indirect conditional sibling calls, but these are even more limitted, since the transformation only triggers if the function to call is already in %r1 (otherwise, the unpredicable load disturbs IfCvt). I was also considering adding a plain BCR instruction as a predicated variant of BR for switches, but since switches always (?) have the address arithmetic instructions between value-in-range check and indirect jump, it'd be rather useless.

[uweigand]

LGTM, thanks. I'll check it in shortly.

llvm/trunk/lib/Target/SystemZ/SystemZAsmPrinter.cpp

LoweredMI = MCInstBuilder(SystemZ::BASR)
       .addReg(MI->getOperand(0).getReg());
     break;
 
   case SystemZ::CallJG:
     LoweredMI = MCInstBuilder(SystemZ::JG)
       .addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_PLT));
     break;
 
+  case SystemZ::CallBRCL:
+    LoweredMI = MCInstBuilder(SystemZ::BRCL)
+      .addImm(MI->getOperand(0).getImm())
+      .addImm(MI->getOperand(1).getImm())
+      .addExpr(Lower.getExpr(MI->getOperand(2), MCSymbolRefExpr::VK_PLT));
+    break;
+
   case SystemZ::CallBR:
     LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R1D);
     break;
 
   case SystemZ::TLS_GDCALL:
     LoweredMI = MCInstBuilder(SystemZ::BRASL)
       .addReg(SystemZ::R14D)
       .addExpr(getTLSGetOffset(MF->getContext()))

llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp

static unsigned getConditionalMove(unsigned Opcode) {
   default:           return 0;
   }
 }
 
 bool SystemZInstrInfo::isPredicable(MachineInstr &MI) const {
   unsigned Opcode = MI.getOpcode();
   if (STI.hasLoadStoreOnCond() && getConditionalMove(Opcode))
     return true;
-  if (Opcode == SystemZ::Return)
+  if (Opcode == SystemZ::Return ||
+      Opcode == SystemZ::CallJG)
     return true;
   return false;
 }
 
 bool SystemZInstrInfo::
 isProfitableToIfCvt(MachineBasicBlock &MBB,
                     unsigned NumCycles, unsigned ExtraPredCycles,
                     BranchProbability Probability) const {
bool SystemZInstrInfo::PredicateInstruction(
   }
   if (Opcode == SystemZ::Return) {
     MI.setDesc(get(SystemZ::CondReturn));
     MachineInstrBuilder(*MI.getParent()->getParent(), MI)
       .addImm(CCValid).addImm(CCMask)
       .addReg(SystemZ::CC, RegState::Implicit);
     return true;
   }
+  if (Opcode == SystemZ::CallJG) {
+    const GlobalValue *Global = MI.getOperand(0).getGlobal();
+    const uint32_t *RegMask = MI.getOperand(1).getRegMask();
+    MI.RemoveOperand(1);
+    MI.RemoveOperand(0);
+    MI.setDesc(get(SystemZ::CallBRCL));
+    MachineInstrBuilder(*MI.getParent()->getParent(), MI)
+      .addImm(CCValid).addImm(CCMask)
+      .addGlobalAddress(Global)
+      .addRegMask(RegMask)
+      .addReg(SystemZ::CC, RegState::Implicit);
+    return true;
+  }
   return false;
 }
 
 void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator MBBI,
                                    DebugLoc DL, unsigned DestReg,
                                    unsigned SrcReg, bool KillSrc) const {
   // Split 128-bit GPR moves into two 64-bit moves.  This handles ADDR128 too.

llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td

 // are argument registers and since branching to R0 is a no-op.
 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
   def CallJG : Alias<6, (outs), (ins pcrel32:$I2),
                      [(z_sibcall pcrel32:$I2)]>;
   let Uses = [R1D] in
     def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>;
 }
 
+let CCMaskFirst = 1, isCall = 1, isReturn = 1 in
+  def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1,
+                                   pcrel32:$I2), []>;
+
 // TLS calls.  These will be lowered into a call to __tls_get_offset,
 // with an extra relocation specifying the TLS symbol.
 let isCall = 1, Defs = [R14D, CC] in {
   def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops),
                          [(z_tls_gdcall tglobaltlsaddr:$I2)]>;
   def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops),
                          [(z_tls_ldcall tglobaltlsaddr:$I2)]>;
 }

llvm/trunk/test/CodeGen/SystemZ/call-04.ll

+; Test conditional sibling calls.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+declare void @fun_a()
+declare void @fun_b()
+declare void @fun_c(i32)
+
+@var = global i32 1;
+
+; Check a conditional sibling call.
+define void @f1(i32 %val1, i32 %val2) {
+; CHECK-LABEL: f1:
+; CHECK: cr %r2, %r3
+; CHECK: jgl fun_a@PLT
+; CHECK: br %r14
+  %cond = icmp slt i32 %val1, %val2;
+  br i1 %cond, label %a, label %b;
+
+a:
+  tail call void @fun_a()
+  ret void
+
+b:
+  store i32 1, i32 *@var;
+  ret void
+}
+
+; Check a conditional sibling call when there are two possibilities.
+define void @f2(i32 %val1, i32 %val2) {
+; CHECK-LABEL: f2:
+; CHECK: cr %r2, %r3
+; CHECK: jghe fun_b@PLT
+; CHECK: jg fun_a@PLT
+  %cond = icmp slt i32 %val1, %val2;
+  br i1 %cond, label %a, label %b;
+
+a:
+  tail call void @fun_a()
+  ret void
+
+b:
+  tail call void @fun_b()
+  ret void
+}
+
+; Check a conditional sibling call with an argument - not supported.
+define void @f3(i32 %val1, i32 %val2) {
+; CHECK-LABEL: f3:
+; CHECK: crjhe %r2, %r3
+; CHECK: jg fun_c@PLT
+; CHECK: br %r14
+  %cond = icmp slt i32 %val1, %val2;
+  br i1 %cond, label %a, label %b;
+
+a:
+  tail call void @fun_c(i32 1)
+  ret void
+
+b:
+  store i32 1, i32 *@var;
+  ret void
+}
+
+; Check a conditional sibling call - unsigned compare.
+define void @f4(i32 %val1, i32 %val2) {
+; CHECK-LABEL: f4:
+; CHECK: clr %r2, %r3
+; CHECK: jgl fun_a@PLT
+; CHECK: br %r14
+  %cond = icmp ult i32 %val1, %val2;
+  br i1 %cond, label %a, label %b;
+
+a:
+  tail call void @fun_a()
+  ret void
+
+b:
+  store i32 1, i32 *@var;
+  ret void
+}
+
+; Check a conditional sibling call - 64-bit compare.
+define void @f5(i64 %val1, i64 %val2) {
+; CHECK-LABEL: f5:
+; CHECK: cgr %r2, %r3
+; CHECK: jgl fun_a@PLT
+; CHECK: br %r14
+  %cond = icmp slt i64 %val1, %val2;
+  br i1 %cond, label %a, label %b;
+
+a:
+  tail call void @fun_a()
+  ret void
+
+b:
+  store i32 1, i32 *@var;
+  ret void
+}
+
+; Check a conditional sibling call - unsigned 64-bit compare.
+define void @f6(i64 %val1, i64 %val2) {
+; CHECK-LABEL: f6:
+; CHECK: clgr %r2, %r3
+; CHECK: jgl fun_a@PLT
+; CHECK: br %r14
+  %cond = icmp ult i64 %val1, %val2;
+  br i1 %cond, label %a, label %b;
+
+a:
+  tail call void @fun_a()
+  ret void
+
+b:
+  store i32 1, i32 *@var;
+  ret void
+}
+
+; Check a conditional sibling call - less-equal compare.
+define void @f7(i32 %val1, i32 %val2) {
+; CHECK-LABEL: f7:
+; CHECK: cr %r2, %r3
+; CHECK: jgle fun_a@PLT
+; CHECK: br %r14
+  %cond = icmp sle i32 %val1, %val2;
+  br i1 %cond, label %a, label %b;
+
+a:
+  tail call void @fun_a()
+  ret void
+
+b:
+  store i32 1, i32 *@var;
+  ret void
+}
+
+; Check a conditional sibling call - high compare.
+define void @f8(i32 %val1, i32 %val2) {
+; CHECK-LABEL: f8:
+; CHECK: cr %r2, %r3
+; CHECK: jgh fun_a@PLT
+; CHECK: br %r14
+  %cond = icmp sgt i32 %val1, %val2;
+  br i1 %cond, label %a, label %b;
+
+a:
+  tail call void @fun_a()
+  ret void
+
+b:
+  store i32 1, i32 *@var;
+  ret void
+}
+
+; Check a conditional sibling call - high-equal compare.
+define void @f9(i32 %val1, i32 %val2) {
+; CHECK-LABEL: f9:
+; CHECK: cr %r2, %r3
+; CHECK: jghe fun_a@PLT
+; CHECK: br %r14
+  %cond = icmp sge i32 %val1, %val2;
+  br i1 %cond, label %a, label %b;
+
+a:
+  tail call void @fun_a()
+  ret void
+
+b:
+  store i32 1, i32 *@var;
+  ret void
+}
+
+; Check a conditional sibling call - equal compare.
+define void @f10(i32 %val1, i32 %val2) {
+; CHECK-LABEL: f10:
+; CHECK: cr %r2, %r3
+; CHECK: jge fun_a@PLT
+; CHECK: br %r14
+  %cond = icmp eq i32 %val1, %val2;
+  br i1 %cond, label %a, label %b;
+
+a:
+  tail call void @fun_a()
+  ret void
+
+b:
+  store i32 1, i32 *@var;
+  ret void
+}
+
+; Check a conditional sibling call - unequal compare.
+define void @f11(i32 %val1, i32 %val2) {
+; CHECK-LABEL: f11:
+; CHECK: cr %r2, %r3
+; CHECK: jglh fun_a@PLT
+; CHECK: br %r14
+  %cond = icmp ne i32 %val1, %val2;
+  br i1 %cond, label %a, label %b;
+
+a:
+  tail call void @fun_a()
+  ret void
+
+b:
+  store i32 1, i32 *@var;
+  ret void
+}
+
+; Check a conditional sibling call - immediate slt.
+define void @f12(i32 %val1) {
+; CHECK-LABEL: f12:
+; CHECK: chi %r2, 4
+; CHECK: jgle fun_a@PLT
+; CHECK: br %r14
+  %cond = icmp slt i32 %val1, 5;
+  br i1 %cond, label %a, label %b;
+
+a:
+  tail call void @fun_a()
+  ret void
+
+b:
+  store i32 1, i32 *@var;
+  ret void
+}
+
+; Check a conditional sibling call - immediate sle.
+define void @f13(i32 %val1) {
+; CHECK-LABEL: f13:
+; CHECK: chi %r2, 5
+; CHECK: jgle fun_a@PLT
+; CHECK: br %r14
+  %cond = icmp sle i32 %val1, 5;
+  br i1 %cond, label %a, label %b;
+
+a:
+  tail call void @fun_a()
+  ret void
+
+b:
+  store i32 1, i32 *@var;
+  ret void
+}
+
+; Check a conditional sibling call - immediate sgt.
+define void @f14(i32 %val1) {
+; CHECK-LABEL: f14:
+; CHECK: chi %r2, 6
+; CHECK: jghe fun_a@PLT
+; CHECK: br %r14
+  %cond = icmp sgt i32 %val1, 5;
+  br i1 %cond, label %a, label %b;
+
+a:
+  tail call void @fun_a()
+  ret void
+
+b:
+  store i32 1, i32 *@var;
+  ret void
+}
+
+; Check a conditional sibling call - immediate sge.
+define void @f15(i32 %val1) {
+; CHECK-LABEL: f15:
+; CHECK: chi %r2, 5
+; CHECK: jghe fun_a@PLT
+; CHECK: br %r14
+  %cond = icmp sge i32 %val1, 5;
+  br i1 %cond, label %a, label %b;
+
+a:
+  tail call void @fun_a()
+  ret void
+
+b:
+  store i32 1, i32 *@var;
+  ret void
+}
+
+; Check a conditional sibling call - immediate eq.
+define void @f16(i32 %val1) {
+; CHECK-LABEL: f16:
+; CHECK: chi %r2, 5
+; CHECK: jge fun_a@PLT
+; CHECK: br %r14
+  %cond = icmp eq i32 %val1, 5;
+  br i1 %cond, label %a, label %b;
+
+a:
+  tail call void @fun_a()
+  ret void
+
+b:
+  store i32 1, i32 *@var;
+  ret void
+}
+
+; Check a conditional sibling call - immediate ne.
+define void @f17(i32 %val1) {
+; CHECK-LABEL: f17:
+; CHECK: chi %r2, 5
+; CHECK: jglh fun_a@PLT
+; CHECK: br %r14
+  %cond = icmp ne i32 %val1, 5;
+  br i1 %cond, label %a, label %b;
+
+a:
+  tail call void @fun_a()
+  ret void
+
+b:
+  store i32 1, i32 *@var;
+  ret void
+}
+
+; Check a conditional sibling call - immediate ult.
+define void @f18(i32 %val1) {
+; CHECK-LABEL: f18:
+; CHECK: clfi %r2, 4
+; CHECK: jgle fun_a@PLT
+; CHECK: br %r14
+  %cond = icmp ult i32 %val1, 5;
+  br i1 %cond, label %a, label %b;
+
+a:
+  tail call void @fun_a()
+  ret void
+
+b:
+  store i32 1, i32 *@var;
+  ret void
+}
+
+; Check a conditional sibling call - immediate 64-bit slt.
+define void @f19(i64 %val1) {
+; CHECK-LABEL: f19:
+; CHECK: cghi %r2, 4
+; CHECK: jgle fun_a@PLT
+; CHECK: br %r14
+  %cond = icmp slt i64 %val1, 5;
+  br i1 %cond, label %a, label %b;
+
+a:
+  tail call void @fun_a()
+  ret void
+
+b:
+  store i32 1, i32 *@var;
+  ret void
+}
+
+; Check a conditional sibling call - immediate 64-bit ult.
+define void @f20(i64 %val1) {
+; CHECK-LABEL: f20:
+; CHECK: clgfi %r2, 4
+; CHECK: jgle fun_a@PLT
+; CHECK: br %r14
+  %cond = icmp ult i64 %val1, 5;
+  br i1 %cond, label %a, label %b;
+
+a:
+  tail call void @fun_a()
+  ret void
+
+b:
+  store i32 1, i32 *@var;
+  ret void
+}