The patch fixes offsets for LLE, LWE, SBE, SCE and SHE instructions and adds a check of their operands.
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Hi,
There's probably some overlap between this patch and the rL265010 I committed earlier today. You seem to have spotted some bugs that I missed though (the changes from 12-bit offsets to 9-bit offsets).
lib/Target/Mips/MicroMips32r6InstrFormats.td | ||
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394–422 ↗ | (On Diff #52194) | Is there a need to provide bits 15-12 in an argument? We always pass the same value as far as I can see. If it's really necessary: this is a different change to the one described in the description and should be in a separate patch. |
lib/Target/Mips/MicroMips32r6InstrInfo.td | ||
912–938 ↗ | (On Diff #52194) | Similarly, is there a need for ImmOpnd to be an argument? We only use one value as far as I can see. The mem_mm_12 -> mem_simm9gpr change is correct. Thanks for spotting it since I missed it in the r265010 I committed earlier today. |
lib/Target/Mips/MipsEVAInstrInfo.td | ||
54–84 ↗ | (On Diff #52194) | mem_simm9 and mem_simm9gpr appear to be the same thing except for the predicate function, and it turns out that the body of those predicates are also equivalent. We should replace all uses of mem_simm9gpr with mem_simm9 and remove the code duplication. |
Removed mem_simm9gpr because it is redundand (also removed MipsMemSimm9GPRAsmOperand class and isMemWithSimmOffsetGPR() method).
Replaced all usages of mem_simm9gpr with mem_simm9.
Removed changes in enc. classes because they are not needed for this patch.
Added more invalid tests for instructions with mem_simm9 operand.
LGTM. There is another occurrence of taking 12 bit offsets that should be 9 which is the cache and pref instructions definitions for microMIPS32r6.