[mips][microMIPS] Implement BC1EQZC, BC1NEZC, BC2EQZC and BC2NEZC instructions

[zbuljan]

Summary

The patch implements microMIPSr6 BC1EQZC, BC1NEZC, BC2EQZC and BC2NEZC instructions.

[sdardis]

Small things mostly, comments inlined.

For the invalid/valid tests, can you sort the instructions you've added into alphabetical order?

lib/Target/Mips/MicroMips32r6InstrFormats.td

874 ↗

(On Diff #51286)

Rename this to POOL32I_BRANCH_COP_1_2_FM_MMR6. The class below is a copy-paste which is then not necessary and so can be deleted.

881 ↗

(On Diff #51286)

Just to be explicit, the encoding here is correct. The documentation isn't 100%.

887–898 ↗

(On Diff #51286)

See my above comment.

lib/Target/Mips/MicroMips32r6InstrInfo.td

173–176 ↗

(On Diff #51286)

See my comments on changing the class name to POOL32I_BRANCH_COP_1_2_FM_MMR6.

943 ↗

(On Diff #51286)

Formatting, break the line after "BRANCH_DESC_BASE," and indent "HARDFLOAT {" appropriately.

test/MC/Disassembler/Mips/micromips32r6/valid.txt

261–268 ↗

(On Diff #51286)

You don't need to check each instruction twice if there is no real difference between the operands.

Just once is sufficient provided you do not use zero values.

This applies to the rest of the */valid.s tests.

test/MC/Mips/micromips32r6/invalid.s

111–126 ↗

(On Diff #51286)

For these invalid tests, checking once for each type of error for each instruction is sufficient.

[sdardis]

lib/Target/Mips/MicroMips32r6InstrInfo.td

943 ↗

(On Diff #51286)

class BRANCH_COP1_MMR6_DESC also needs to inherit the relevant parameterised InstSE<> class.

This instruction should also define the register $at, like all other branches. $at is required to be defined by these instructions in case a long branch fixup needs to be emitted.

952 ↗

(On Diff #51286)

This instruction needs to define at as well, but you can skip the InstSE<> class inheritance as COP2 is implementation specific and likely to be targeted by intrinsics anyway.

[zbuljan]

Used only one format class POOL32I_BRANCH_COP_1_2_FM_MMR6 (other one was redundant so it is deleted).
Modified desc. class BRANCH_COP1_MMR6_DESC_BASE to inherit the relevant parameterised InstSE<> class.
Register $at is now defined in both desc. classes (BRANCH_COP1_MMR6_DESC_BASE and BRANCH_COP2_MMR6_DESC_BASE).
Removed redundant tests and added additional invalid tests.

[sdardis]

One change and one nit. The inheritance order needs to be changed so that the various fields of the instruction records get set correctly. Comments inlined.

lib/Target/Mips/MicroMips32r6InstrFormats.td

982 ↗

(On Diff #56124)

This class needs to inherit from MMR6Arch, as the current ordering does not set the Arch and BaseOpcode properly. The inheritance ordering should be similar to that of the existing microMIPSR6 branches, such as BGEC_MMR6.

lib/Target/Mips/MicroMips32r6InstrInfo.td

1140–1142 ↗

(On Diff #56124)

As coprocessor 2 is implementation dependant, $ft should be $rt.

[zbuljan]

Rebased to work with TOT.
Changed POOL32I_BRANCH_COP_1_2_FM_MMR6 format class to inherit from MMR6Arch.

[zbuljan]

Rebased to work with TOT.

[sdardis]

LGTM with 2 tiny nits.

test/MC/Mips/micromips32r6/valid.s

338–345 ↗

(On Diff #57564)

Checking each instruction once is sufficient. Just avoid using $zero or 0 as an operand because that may mask errors if values default to zero.

test/MC/Mips/micromips64r6/valid.s

276–283 ↗

(On Diff #57564)

Here too.

llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

if (MCID.isBranch() || MCID.isCall()) {
     case Mips::BGEZ_MM:
     case Mips::BGTZ_MM:
     case Mips::BLEZ_MM:
     case Mips::BLTZ_MM:
     case Mips::BGEZAL_MM:
     case Mips::BLTZAL_MM:
     case Mips::BC1F_MM:
     case Mips::BC1T_MM:
+    case Mips::BC1EQZC_MMR6:
+    case Mips::BC1NEZC_MMR6:
+    case Mips::BC2EQZC_MMR6:
+    case Mips::BC2NEZC_MMR6:
       assert(MCID.getNumOperands() == 2 && "unexpected number of operands");
       Offset = Inst.getOperand(1);
       if (!Offset.isImm())
         break; // We'll deal with this situation later on when applying fixups.
       if (!isIntN(inMicroMipsMode() ? 17 : 18, Offset.getImm()))
         return Error(IDLoc, "branch target out of range");
       if (OffsetToAlignment(Offset.getImm(),
                             1LL << (inMicroMipsMode() ? 1 : 2)))

llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td

class CMP_BRANCH_OFF21_FM_MMR6<string opstr, bits<6> funct> : MipsR6Inst {
   bits<21> offset;
 
   bits<32> Inst;
 
   let Inst{31-26} = funct;
   let Inst{25-21} = rs;
   let Inst{20-0} = offset;
 }
+
+class POOL32I_BRANCH_COP_1_2_FM_MMR6<string instr_asm, bits<5> funct>
+    : MMR6Arch<instr_asm> {
+  bits<5> rt;
+  bits<16> offset;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b010000;
+  let Inst{25-21} = funct;
+  let Inst{20-16} = rt;
+  let Inst{15-0}  = offset;
+}

llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td

 class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
 class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
 class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
 class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
 class TLBINV_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinv", 0x10d>;
 class TLBINVF_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinvf", 0x14d>;
 class DVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"dvp", 0b0001100101>;
 class EVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"evp", 0b0011100101>;
+class BC1EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1eqzc", 0b01000>;
+class BC1NEZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1nezc", 0b01001>;
+class BC2EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc2eqzc", 0b01010>;
+class BC2NEZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc2nezc", 0b01011>;
 
 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
                                   RegisterOperand GPROpnd>
     : BRANCH_DESC_BASE {
   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
   dag OutOperandList = (outs);
   string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
   list<Register> Defs = [AT];

 
 class BEQZC_MMR6_DESC
     : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21_mm, GPR32Opnd>,
       MMR6Arch<"beqzc">;
 class BNEZC_MMR6_DESC
     : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21_mm, GPR32Opnd>,
       MMR6Arch<"bnezc">;
 
+class BRANCH_COP1_MMR6_DESC_BASE<string opstr> :
+    InstSE<(outs), (ins FGR64Opnd:$rt, brtarget_mm:$offset),
+           !strconcat(opstr, "\t$rt, $offset"), [], II_BC1CCZ, FrmI>,
+    HARDFLOAT, BRANCH_DESC_BASE {
+  list<Register> Defs = [AT];
+}
+
+class BC1EQZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1eqzc">;
+class BC1NEZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1nezc">;
+
+class BRANCH_COP2_MMR6_DESC_BASE<string opstr> : BRANCH_DESC_BASE {
+  dag InOperandList = (ins COP2Opnd:$rt, brtarget_mm:$offset);
+  dag OutOperandList = (outs);
+  string AsmString = !strconcat(opstr, "\t$rt, $offset");
+  list<Register> Defs = [AT];
+}
+
+class BC2EQZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2eqzc">;
+class BC2NEZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2nezc">;
+
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
 //
 //===----------------------------------------------------------------------===//
 
 let DecoderNamespace = "MicroMipsR6" in {
 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;

 def CLASS_D_MMR6 : StdMMR6Rel, CLASS_D_MMR6_ENC, CLASS_D_MMR6_DESC,
                    ISA_MICROMIPS32R6;
 def TLBINV_MMR6 : StdMMR6Rel, TLBINV_MMR6_ENC, TLBINV_MMR6_DESC,
                   ISA_MICROMIPS32R6;
 def TLBINVF_MMR6 : StdMMR6Rel, TLBINVF_MMR6_ENC, TLBINVF_MMR6_DESC,
                    ISA_MICROMIPS32R6;
 def DVP_MMR6 : R6MMR6Rel, DVP_MMR6_ENC, DVP_MMR6_DESC, ISA_MICROMIPS32R6;
 def EVP_MMR6 : R6MMR6Rel, EVP_MMR6_ENC, EVP_MMR6_DESC, ISA_MICROMIPS32R6;
+def BC1EQZC_MMR6 : R6MMR6Rel, BC1EQZC_MMR6_DESC, BC1EQZC_MMR6_ENC,
+                   ISA_MICROMIPS32R6;
+def BC1NEZC_MMR6 : R6MMR6Rel, BC1NEZC_MMR6_DESC, BC1NEZC_MMR6_ENC,
+                   ISA_MICROMIPS32R6;
+def BC2EQZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2EQZC_MMR6_ENC, BC2EQZC_MMR6_DESC,
+                   ISA_MICROMIPS32R6;
+def BC2NEZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2NEZC_MMR6_ENC, BC2NEZC_MMR6_DESC,
+                   ISA_MICROMIPS32R6;
 }
 
 def BGEC_MMR6 : R6MMR6Rel, BGEC_MMR6_ENC, BGEC_MMR6_DESC, ISA_MICROMIPS32R6;
 def BGEUC_MMR6 : R6MMR6Rel, BGEUC_MMR6_ENC, BGEUC_MMR6_DESC, ISA_MICROMIPS32R6;
 def BLTC_MMR6 : R6MMR6Rel, BLTC_MMR6_ENC, BLTC_MMR6_DESC, ISA_MICROMIPS32R6;
 def BLTUC_MMR6 : R6MMR6Rel, BLTUC_MMR6_ENC, BLTUC_MMR6_DESC, ISA_MICROMIPS32R6;
 def BEQC_MMR6 : R6MMR6Rel, BEQC_MMR6_ENC, BEQC_MMR6_DESC, ISA_MICROMIPS32R6;
 def BNEC_MMR6 : R6MMR6Rel, BNEC_MMR6_ENC, BNEC_MMR6_DESC, ISA_MICROMIPS32R6;

llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td

 
 def ADDIUPC : R6MMR6Rel, ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
 def ALIGN : R6MMR6Rel, ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
 def ALUIPC : R6MMR6Rel, ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
 def AUI : R6MMR6Rel, AUI_ENC, AUI_DESC, ISA_MIPS32R6;
 def AUIPC : R6MMR6Rel, AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
 def BAL : BAL_ENC, BAL_DESC, ISA_MIPS32R6;
 def BALC : R6MMR6Rel, BALC_ENC, BALC_DESC, ISA_MIPS32R6;
+let AdditionalPredicates = [NotInMicroMips] in {
   def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6, HARDFLOAT;
   def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6, HARDFLOAT;
   def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6;
   def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;
+}
 def BC : R6MMR6Rel, BC_ENC, BC_DESC, ISA_MIPS32R6;
 def BEQC : R6MMR6Rel, BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
 def BEQZALC : R6MMR6Rel, BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
 def BEQZC : R6MMR6Rel, BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
 def BGEC : R6MMR6Rel, BGEC_ENC, BGEC_DESC, ISA_MIPS32R6;
 def BGEUC : R6MMR6Rel, BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6;
 def BGEZALC : R6MMR6Rel, BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
 def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;

llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt

 0x00 0x85 0x1f 0x3c # CHECK: jalrc.hb $4, $5
 0x00 0x65 0x10 0x10 # CHECK: sllv $2, $3, $5
 0x00 0x83 0x38 0x80 # CHECK: sra $4, $3, 7
 0x00 0x65 0x10 0x90 # CHECK: srav $2, $3, $5
 0x00 0x83 0x38 0x40 # CHECK: srl $4, $3, 7
 0x00 0x65 0x10 0x50 # CHECK: srlv $2, $3, $5
 0x22 0x04 0x10 0x08 # CHECK: lwp $16, 8($4)
 0x22 0x04 0x90 0x08 # CHECK: swp $16, 8($4)
+0x41 0x1f 0x00 0x02 # CHECK: bc1eqzc $f31, 4
+0x41 0x3f 0x00 0x02 # CHECK: bc1nezc $f31, 4
+0x41 0x5f 0x00 0x04 # CHECK: bc2eqzc $31, 8
+0x41 0x7f 0x00 0x04 # CHECK: bc2nezc $31, 8

llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt

 0x22 0x04 0x90 0x08 # CHECK: swp $16, 8($4)
 0x58 0x64 0x7b 0x3c # CHECK: dsbh $3, $4
 0x58 0x64 0xfb 0x3c # CHECK: dshd $3, $4
 0x58 0x64 0x28 0x00 # CHECK: dsll $3, $4, 5
 0x58 0x64 0x28 0x08 # CHECK: dsll32 $3, $4, 5
 0x58 0xa6 0x20 0x10 # CHECK: dsllv $4, $5, $6
 0x58 0x85 0x28 0x80 # CHECK: dsra $4, $5, 5
 0x58 0xa6 0x20 0x90 # CHECK: dsrav $4, $5, $6
+0x41 0x1f 0x00 0x02 # CHECK: bc1eqzc $f31, 4
+0x41 0x3f 0x00 0x02 # CHECK: bc1nezc $f31, 4
+0x41 0x5f 0x00 0x04 # CHECK: bc2eqzc $31, 8
+0x41 0x7f 0x00 0x04 # CHECK: bc2nezc $31, 8

llvm/trunk/test/MC/Mips/micromips32r6/invalid.s

# RUN: FileCheck %s < %t1
   lwp $16, 8($34)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
   lwp $16, 4096($4)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
   lwp $16, 8($16)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
   swp $31, 8($4)           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swp $16, 8($34)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
   swp $16, 4096($4)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
                            # bposge32 is microMIPS DSP instruction
   bposge32 342             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+  bc1eqzc $f32, 4          # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+  bc1eqzc $f31, -65535     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
+  bc1eqzc $f31, -65537     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
+  bc1eqzc $f31, 65535      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
+  bc1eqzc $f31, 65536      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
+  bc1nezc $f32, 4          # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+  bc1nezc $f31, -65535     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
+  bc1nezc $f31, -65537     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
+  bc1nezc $f31, 65535      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
+  bc1nezc $f31, 65536      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
+  bc2eqzc $32, 4           # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+  bc2eqzc $31, -65535      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
+  bc2eqzc $31, -65537      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
+  bc2eqzc $31, 65535       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
+  bc2eqzc $31, 65536       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
+  bc2nezc $32, 4           # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+  bc2nezc $31, -65535      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
+  bc2nezc $31, -65537      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
+  bc2nezc $31, 65535       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
+  bc2nezc $31, 65536       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range

llvm/trunk/test/MC/Mips/micromips32r6/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
   sll $2, $3               # CHECK: sllv $2, $2, $3        # encoding: [0x00,0x43,0x10,0x10]
   sra $2, $3               # CHECK: srav $2, $2, $3        # encoding: [0x00,0x43,0x10,0x90]
   srl $2, $3               # CHECK: srlv $2, $2, $3        # encoding: [0x00,0x43,0x10,0x50]
   sll $3, 7                # CHECK: sll $3, $3, 7          # encoding: [0x00,0x63,0x38,0x00]
   sra $3, 7                # CHECK: sra $3, $3, 7          # encoding: [0x00,0x63,0x38,0x80]
   srl $3, 7                # CHECK: srl $3, $3, 7          # encoding: [0x00,0x63,0x38,0x40]
   lwp $16, 8($4)           # CHECK: lwp $16, 8($4)         # encoding: [0x22,0x04,0x10,0x08]
   swp $16, 8($4)           # CHECK: swp $16, 8($4)         # encoding: [0x22,0x04,0x90,0x08]
+  bc1eqzc $f31, 4          # CHECK: bc1eqzc $f31, 4        # encoding: [0x41,0x1f,0x00,0x02]
+  bc1nezc $f31, 4          # CHECK: bc1nezc $f31, 4        # encoding: [0x41,0x3f,0x00,0x02]
+  bc2eqzc $31, 8           # CHECK: bc2eqzc $31, 8         # encoding: [0x41,0x5f,0x00,0x04]
+  bc2nezc $31, 8           # CHECK: bc2nezc $31, 8         # encoding: [0x41,0x7f,0x00,0x04]

llvm/trunk/test/MC/Mips/micromips64r6/invalid.s

# RUN: FileCheck %s < %t1
   dsll32 $3, $4, 32            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
   dsll32 $3, $4, -1            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
   dsra $4, $5, 64              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
   dsra $4, $5, -1              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
   dsra32 $4, $5, 32            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
   dsra32 $4, $5, -1            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
                                # bposge32 is microMIPS DSP instruction
   bposge32 342                 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+  bc1eqzc $f32, 4              # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+  bc1eqzc $f31, -65535         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
+  bc1eqzc $f31, -65537         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
+  bc1eqzc $f31, 65535          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
+  bc1eqzc $f31, 65536          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
+  bc1nezc $f32, 4              # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+  bc1nezc $f31, -65535         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
+  bc1nezc $f31, -65537         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
+  bc1nezc $f31, 65535          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
+  bc1nezc $f31, 65536          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
+  bc2eqzc $32, 4               # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+  bc2eqzc $31, -65535          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
+  bc2eqzc $31, -65537          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
+  bc2eqzc $31, 65535           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
+  bc2eqzc $31, 65536           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
+  bc2nezc $32, 4               # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+  bc2nezc $31, -65535          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
+  bc2nezc $31, -65537          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
+  bc2nezc $31, 65535           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
+  bc2nezc $31, 65536           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range

llvm/trunk/test/MC/Mips/micromips64r6/valid.s

a:
         dsbh $3, $4              # CHECK: dsbh $3, $4             # encoding: [0x58,0x64,0x7b,0x3c]
         dshd $3, $4              # CHECK: dshd $3, $4             # encoding: [0x58,0x64,0xfb,0x3c]
         dsll $3, $4, 5           # CHECK: dsll $3, $4, 5          # encoding: [0x58,0x64,0x28,0x00]
         dsll32 $3, $4, 5         # CHECK: dsll32 $3, $4, 5        # encoding: [0x58,0x64,0x28,0x08]
         dsllv $4, $5, $6         # CHECK: dsllv $4, $5, $6        # encoding: [0x58,0xa6,0x20,0x10]
         dsra $4, $5, 5           # CHECK: dsra $4, $5, 5          # encoding: [0x58,0x85,0x28,0x80]
         dsra32 $4, $5, 5         # CHECK: dsra32 $4, $5, 5        # encoding: [0x58,0x85,0x28,0x84]
         dsrav $4, $5, $6         # CHECK: dsrav $4, $5, $6        # encoding: [0x58,0xa6,0x20,0x90]
+        bc1eqzc $f31, 4          # CHECK: bc1eqzc $f31, 4         # encoding: [0x41,0x1f,0x00,0x02]
+        bc1nezc $f31, 4          # CHECK: bc1nezc $f31, 4         # encoding: [0x41,0x3f,0x00,0x02]
+        bc2eqzc $31, 8           # CHECK: bc2eqzc $31, 8          # encoding: [0x41,0x5f,0x00,0x04]
+        bc2nezc $31, 8           # CHECK: bc2nezc $31, 8          # encoding: [0x41,0x7f,0x00,0x04]
 
 1: