[mips] MIPSR6 Compact jump support

[sdardis]

Summary

This patch adds support for compact jumps similiar to the previous compact
branch support for MIPSR6. Unlike compact branches, compact jumps do not
have a forbidden slot.

As MipsInstrInfo::getEquivalentCompactForm can determine the correct
expansion for jumps and branches for both microMIPS and MIPSR6, simplify
the delay slot filler when producing compact CTIs in cases where a delay slot
can be filled.

[vkalintiris]

Hi Simon, I added some comments inline.

lib/Target/Mips/Mips64r6InstrInfo.td

88

I know that you probably based the definition on the 32-bit description, but do you know why we have to define $at?

122–126

Can you add the relevant MC tests for the new instructions? Either in a new review request or in this one would be fine with me.

lib/Target/Mips/MipsInstrInfo.cpp

260

Can we merge the functionality of this into getEquivalentCompactForm()? As far as I can tell, there's no other user of this member function and there's no point in duplicating the switch statement for every opcode twice.

368–369

I suggest that we move most of these conditions into the initialization of BranchWithZeroOperand in order to simplify the code.

391–392

Why do we need these cases? We don't update the NewOpc when they match.

396–407

What is going to happen to the defined register RA{,_64},

396–429

I believe that we should simplify this by handling the logic in three separate cases: (1) JIALC et al., (2) BranchWithZeroOperand == true, and (3) everything else. I'm afraid that this code could become very complicated in time if we consider all the ABIs & ISAs that we have to support.

413

We can use the convenient MIB.addImm() here.

test/CodeGen/Mips/llvm-ir/ret.ll

21–25

MTHC1 has *unmodeled side-effects* and the DSF bails out on these instructions (see Filler::terminateSearch). Can you update the comment to reflect this?

test/MC/Mips/mips32r6/valid.s

166–167

Indentation.

[dsanders]

lib/Target/Mips/Mips64r6InstrInfo.td

88

I haven't dug into the details of exactly what can/can't cause it and I don't know whether it applies to this instruction or not but the explanation I was given a couple years ago was that $at may be clobbered as a result of changes made by the linker (e.g. out-of-range jumps, plt stubs, etc.).

test/CodeGen/Mips/llvm-ir/ret.ll

21–25

MTHC1 shouldn't have side-effects, it looks like tablegen is inferring it from the lack of a codegen pattern.

[sdardis]

Response for reviewer comments.

[sdardis]

lib/Target/Mips/Mips64r6InstrInfo.td

88

After some discussion with Daniel, it's necessary as the long branch pass and some possible linker stubs clobber $at.

122–126

Are they not covered by test/MC/Mips/mips64r6/valid.s, line 145 & 146?

lib/Target/Mips/MipsInstrInfo.cpp

396–407

RA(_64) will be marked as implicit def/dead as required since its flags are copied from the original instruction. Not erasing that operand will result in contradictory information about RA(_64), as adding JIALC/JIALIC64 will mark %RA<imp-def>, however the function call will mark %RA<imp-def,dead>.

Looking at the MIR statement:
JIALC64 %T9_64, 0, <regmask %FP %GP %RA %D12 %D13 %D14 %D15 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %FP_64 %F_HI24 %F_HI25 %F_HI26 %F_HI27 %F_HI28 %F_HI29 %F_HI30 %F_HI31 %GP_64 %RA_64 %S0 %S1 %S2 %S3 %S4 %S5 %S6 %S7 %D24_64 %D25_64 %D26_64 %D27_64 %D28_64 %D29_64 %D30_64 %D31_64 %S0_64 %S1_64 %S2_64 %S3_64 %S4_64 %S5_64 %S6_64 %S7_64>, %RA<imp-def>, %RA<imp-def,dead>, %GP_64<imp-use>, %SP<imp-def>, %V0<imp-def>

%RA appears twice, with the flags duplicated partially. Hence why we have to delete it.

[vkalintiris]

LGTM with some minor inline comments. Clang-format before committing this, as I've spotted 2-3 cases with wrong indentation.

lib/Target/Mips/Mips64r6InstrInfo.td

122–126

Sorry, I missed the codegen-only bit.

lib/Target/Mips/MipsDelaySlotFiller.cpp

582

s/Pseduo/Pseudo/

lib/Target/Mips/MipsInstrInfo.cpp

263–270

There are way several conditions here. Can you replace this with a switch statement similar to the one you wrote in CTIHasCompactMMEncoding()?

[sdardis]

Committed as r265390.

lib/Target/Mips/Mips32r6InstrInfo.td

 
 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
                                 RegisterOperand GPROpnd,
                                 InstrItinClass itin = NoItinerary>
     : MipsR6Arch<opstr> {
   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
   string AsmString = !strconcat(opstr, "\t$rt, $offset");
   list<dag> Pattern = [];
-  bit isTerminator = 1;
   bit hasDelaySlot = 0;
   InstrItinClass Itinerary = itin;
   bit isCTI = 1;
+  bit isBranch = 1;
+  bit isIndirectBranch = 1;
 }
 
 class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
                                              GPR32Opnd, II_JIALC> {
   bit isCall = 1;
   list<Register> Defs = [RA];
 }
 
 class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
                                            GPR32Opnd, II_JIALC> {
   bit isBarrier = 1;
+  bit isTerminator = 1;
   list<Register> Defs = [AT];
 }
 
 class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
   bit isBranch = 1;
   bit isIndirectBranch = 1;
   bit hasDelaySlot = 1;
   bit isTerminator=1;

lib/Target/Mips/Mips64r6InstrInfo.td

 class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, II_DMUL, mul>;
 class DMULU_DESC   : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMUL>;
 class LDPC_DESC    : PCREL_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3, II_LDPC>;
 class LLD_R6_DESC   : LL_R6_DESC_BASE<"lld", GPR64Opnd, II_LLD>;
 class SCD_R6_DESC   : SC_R6_DESC_BASE<"scd", GPR64Opnd, II_SCD>;
 class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>;
 class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>;
 
+class JIALC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
+                                             GPR64Opnd> {
+  bit isCall = 1;
+  list<Register> Defs = [RA];
+}
+
+class JIC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR64Opnd> {
+  bit isBarrier = 1;
+  bit isTerminator = 1;
+  list<Register> Defs = [AT];
+}
+
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
 //
 //===----------------------------------------------------------------------===//
 
 let AdditionalPredicates = [NotInMicroMips] in {
   def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;

 def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
 def LDPC: LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
 def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS32R6;
 def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
 let DecoderNamespace = "Mips32r6_64r6_GP64" in {
   def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
   def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;
 }
-
+let isCodeGenOnly = 1 in {
+def JIALC64 : JIALC_ENC, JIALC64_DESC, ISA_MIPS64R6;
+def JIC64 : JIC_ENC, JIC64_DESC, ISA_MIPS64R6;
+}
 //===----------------------------------------------------------------------===//
 //
 // Instruction Aliases
 //
 //===----------------------------------------------------------------------===//
 
 def : MipsInstAlias<"jr $rs", (JALR64 ZERO_64, GPR64Opnd:$rs), 1>, ISA_MIPS64R6;
 
 //===----------------------------------------------------------------------===//

lib/Target/Mips/MipsDelaySlotFiller.cpp

public:
     }
 
   private:
     bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
 
     Iter replaceWithCompactBranch(MachineBasicBlock &MBB,
                                   Iter Branch, DebugLoc DL);
 
-    Iter replaceWithCompactJump(MachineBasicBlock &MBB,
-                                Iter Jump, DebugLoc DL);
-
     /// This function checks if it is valid to move Candidate to the delay slot
     /// and returns true if it isn't. It also updates memory and register
     /// dependence information.
     bool delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
                         InspectMemInstr &IM) const;
 
     /// This function searches range [Begin, End) for an instruction that can be
     /// moved to the delay slot. Returns true on success.
Iter Filler::replaceWithCompactBranch(MachineBasicBlock &MBB,
 
   unsigned NewOpcode = TII->getEquivalentCompactForm(Branch);
   Branch = TII->genInstrWithNewOpc(NewOpcode, Branch);
 
   std::next(Branch)->eraseFromParent();
   return Branch;
 }
 
-// Replace Jumps with the compact jump instruction.
-Iter Filler::replaceWithCompactJump(MachineBasicBlock &MBB,
-                                    Iter Jump, DebugLoc DL) {
-  const MipsInstrInfo *TII =
-      MBB.getParent()->getSubtarget<MipsSubtarget>().getInstrInfo();
-
-  const MCInstrDesc &NewDesc = TII->get(Mips::JRC16_MM);
-  MachineInstrBuilder MIB = BuildMI(MBB, Jump, DL, NewDesc);
-
-  MIB.addReg(Jump->getOperand(0).getReg());
-
-  Iter tmpIter = Jump;
-  Jump = std::prev(Jump);
-  MBB.erase(tmpIter);
-
-  return Jump;
-}
-
 // For given opcode returns opcode of corresponding instruction with short
 // delay slot.
 static int getEquivalentCallShort(int Opcode) {
   switch (Opcode) {
   case Mips::BGEZAL:
     return Mips::BGEZALS_MM;
   case Mips::BLTZAL:
     return Mips::BLTZALS_MM;
if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None)) {
         MachineBasicBlock::instr_iterator DSI(I);
 
         if (InMicroMipsMode && TII->GetInstSizeInBytes(&*std::next(DSI)) == 2 &&
             DSI->isCall()) {
           // If instruction in delay slot is 16b change opcode to
           // corresponding instruction with short delay slot.
           DSI->setDesc(TII->get(getEquivalentCallShort(DSI->getOpcode())));
         }
-
         continue;
       }
     }
 
-    // If instruction is BEQ or BNE with one ZERO register, then instead of
-    // adding NOP replace this instruction with the corresponding compact
-    // branch instruction, i.e. BEQZC or BNEZC.
-    if (InMicroMipsMode) {
-      if (TII->getEquivalentCompactForm(I)) {
-        I = replaceWithCompactBranch(MBB, I, I->getDebugLoc());
-        continue;
-      }
-
-      if (I->isIndirectBranch() || I->isReturn()) {
-        // For microMIPS the PseudoReturn and PseudoIndirectBranch are always
-        // expanded to JR_MM, so they can be replaced with JRC16_MM.
-        I = replaceWithCompactJump(MBB, I, I->getDebugLoc());
-        continue;
-      }
-    }
+    // For microMIPS if instruction is BEQ or BNE with one ZERO register, then
+    // instead of adding NOP replace this instruction with the corresponding
+    // compact branch instruction, i.e. BEQZC or BNEZC. Additionally
+    // PseduoReturn and PseudoIndirectBranch are expanded to JR_MM, so they can
+    // be replaced with JRC16_MM.
 
     // For MIPSR6 attempt to produce the corresponding compact (no delay slot)
-    // form of the branch. This should save putting in a NOP.
-    if ((STI.hasMips32r6()) && TII->getEquivalentCompactForm(I)) {
+    // form of the CTI. For indirect jumps this will not require inserting a
+    // NOP and for branches will hopefully avoid requiring a NOP.
+    if ((InMicroMipsMode || STI.hasMips32r6()) &&
+         TII->getEquivalentCompactForm(I)) {
       I = replaceWithCompactBranch(MBB, I, I->getDebugLoc());
       continue;
     }
 
     // Bundle the NOP to the instruction with the delay slot.
     BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
     MIBundleBuilder(MBB, I, std::next(I, 2));
   }

lib/Target/Mips/MipsInstrInfo.cpp

MipsInstrInfo::BranchType MipsInstrInfo::AnalyzeBranch(
 
   AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
   FBB = LastInst->getOperand(0).getMBB();
 
   return BT_CondUncond;
 }
 
 /// Return the corresponding compact (no delay slot) form of a branch.
 unsigned MipsInstrInfo::getEquivalentCompactForm(
     const MachineBasicBlock::iterator I) const {
   unsigned Opcode = I->getOpcode();
-  bool canUseShortMMBranches =
+  bool canUseShortMicroMipsCTI =
       Subtarget.inMicroMipsMode() &&
-      (Opcode == Mips::BNE || Opcode == Mips::BEQ) &&
-      I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg();
+      (((Opcode == Mips::BNE || Opcode == Mips::BEQ) &&
+        I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg()) ||
+       // For microMIPS the PseudoReturn and PseudoIndirectBranch are always
+       // expanded to JR_MM, so they can be replaced with JRC16_MM.
+       (Opcode == Mips::JR || Opcode == Mips::PseudoReturn ||
+        Opcode == Mips::PseudoIndirectBranch));
 
-  if (Subtarget.hasMips32r6() || canUseShortMMBranches) {
+  if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) {
     switch (Opcode) {
     case Mips::B:
       return Mips::BC;
     case Mips::BAL:
       return Mips::BALC;
     case Mips::BEQ:
-      if (canUseShortMMBranches)
+      if (canUseShortMicroMipsCTI)
         return Mips::BEQZC_MM;
       else
         return Mips::BEQC;
     case Mips::BNE:
-      if (canUseShortMMBranches)
+      if (canUseShortMicroMipsCTI)
         return Mips::BNEZC_MM;
       else
         return Mips::BNEC;
     case Mips::BGE:
       return Mips::BGEC;
     case Mips::BGEU:
       return Mips::BGEUC;
     case Mips::BGEZ:
       return Mips::BGEZC;
     case Mips::BGTZ:
       return Mips::BGTZC;
     case Mips::BLEZ:
       return Mips::BLEZC;
     case Mips::BLT:
       return Mips::BLTC;
     case Mips::BLTU:
       return Mips::BLTUC;
     case Mips::BLTZ:
       return Mips::BLTZC;
+    // For MIPSR6, the instruction 'jic' can be used for these cases. Some
+    // tools will accept 'jrc reg' as an alias for 'jic 0, $reg'.
+    case Mips::JR:
+    case Mips::PseudoReturn:
+    case Mips::PseudoIndirectBranch:
+      if (canUseShortMicroMipsCTI)
+        return Mips::JRC16_MM;
+      return Mips::JIC;
+    case Mips::JALRPseudo:
+      return Mips::JIALC;
+    case Mips::JR64:
+    case Mips::PseudoReturn64:
+    case Mips::PseudoIndirectBranch64:
+      return Mips::JIC64;
+    case Mips::JALR64Pseudo:
+      return Mips::JIALC64;
      default:
       return 0;
     }
   }
 
   return 0;
 }
 
 /// Predicate for distingushing between control transfer instructions and all
case Mips::CONSTPOOL_ENTRY:
     return MI->getOperand(2).getImm();
   }
 }
 
 MachineInstrBuilder
 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
                                   MachineBasicBlock::iterator I) const {
   MachineInstrBuilder MIB;
-  bool BranchWithZeroOperand = false;
 
   // Certain branches have two forms: e.g beq $1, $zero, dst vs beqz $1, dest
   // Pick the zero form of the branch for readable assembly and for greater
   // branch distance in non-microMIPS mode.
-  if (I->isBranch() && I->getOperand(1).isReg() &&
-      // FIXME: Certain atomic sequences on mips64 generate 32bit references to
-      // Mips::ZERO, which is incorrect. This test should be updated to use
-      // Subtarget.getABI().GetZeroReg() when those atomic sequences and others
-      // are fixed.
+  bool BranchWithZeroOperand =
+      (I->isBranch() && !I->isPseudo() && I->getOperand(1).isReg() &&
        (I->getOperand(1).getReg() == Mips::ZERO ||
-       I->getOperand(1).getReg() == Mips::ZERO_64)) {
-    BranchWithZeroOperand = true;
+        I->getOperand(1).getReg() == Mips::ZERO_64));
+
+  if (BranchWithZeroOperand) {
     switch (NewOpc) {
     case Mips::BEQC:
       NewOpc = Mips::BEQZC;
       break;
     case Mips::BNEC:
       NewOpc = Mips::BNEZC;
       break;
     case Mips::BGEC:
       NewOpc = Mips::BGEZC;
       break;
     case Mips::BLTC:
       NewOpc = Mips::BLTZC;
       break;
-    case Mips::BNEZC_MM:
-    case Mips::BEQZC_MM:
-      break;
-    default:
-      BranchWithZeroOperand = false;
-      break;
     }
   }
 
   MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
 
-  for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J)
-    if (!(BranchWithZeroOperand && (J == 1)))
+  // For MIPSR6 JI*C requires an immediate 0 as an operand, JIALC(64) an
+  // immediate 0 as an operand and requires the removal of it's %RA<imp-def>
+  // implicit operand as copying the implicit operations of the instructio we're
+  // looking at will give us the correct flags.
+  if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 ||
+      NewOpc == Mips::JIALC64) {
+
+    if (NewOpc == Mips::JIALC || NewOpc == Mips::JIALC64)
+      MIB->RemoveOperand(0);
+
+    for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
+      MIB.addOperand(I->getOperand(J));
+    }
+
+    MIB.addImm(0);
+
+ } else if (BranchWithZeroOperand) {
+    // For MIPSR6 and microMIPS branches with an explicit zero operand, copy
+    // everything after the zero.
+     MIB.addOperand(I->getOperand(0));
+
+    for (unsigned J = 2, E = I->getDesc().getNumOperands(); J < E; ++J) {
+      MIB.addOperand(I->getOperand(J));
+    }
+  } else {
+    // All other cases copy all other operands.
+    for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
       MIB.addOperand(I->getOperand(J));
+    }
+  }
+
+  MIB.copyImplicitOps(*I);
 
   MIB.setMemRefs(I->memoperands_begin(), I->memoperands_end());
   return MIB;
 }

test/CodeGen/Mips/compactbranches/compact-branches.ll

-; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=static < %s | FileCheck %s
+; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=static -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=STATIC32
+; RUN: llc -march=mipsel -mcpu=mips64r6 -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=PIC
 
 ; Function Attrs: nounwind
 define void @l()  {
 entry:
+; PIC: jialc $25, 0
   %call = tail call i32 @k()
+; PIC: jialc $25, 0
   %call1 = tail call i32 @j()
   %cmp = icmp eq i32 %call, %call1
 ; CHECK: bnec
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry:
-; CHECK: nop
-; CHECK: jal
+; STATIC: nop
+; STATIC: jal
+; PIC: jialc $25, 0
   tail call void @f(i32 signext -2)
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
+; CHECK: jic $ra, 0
   ret void
 }
 
 declare i32 @k()
 
 declare i32 @j()
 
 declare void @f(i32 signext) 
 
 ; Function Attrs: define void @l2()  {
 define void @l2()  {
 entry:
+; PIC: jialc $25, 0
   %call = tail call i32 @k()
+; PIC: jialc $25, 0
   %call1 = tail call i32 @i()
   %cmp = icmp eq i32 %call, %call1
 ; CHECK beqc
   br i1 %cmp, label %if.end, label %if.then
 
 if.then:                                          ; preds = %entry:
-; CHECK: nop
-; CHECK: jal
+; STATIC: nop
+; STATIC: jal
+; PIC: jialc $25, 0
   tail call void @f(i32 signext -1)
   br label %if.end
 
 if.end:                                           ; preds = %entry, %if.then
+; CHECK: jic $ra, 0
   ret void
 }
 
 declare i32 @i()
 
 ; Function Attrs: nounwind
 define void @l3()  {
 entry:
+; PIC: jialc $25, 0
   %call = tail call i32 @k()
   %cmp = icmp slt i32 %call, 0
 ; CHECK : bgez
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry:
-; CHECK: nop
-; CHECK: jal
+; STATIC: nop
+; STATIC: jal
+; PIC: jialc $25, 0
   tail call void @f(i32 signext 0)
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
+; CHECK: jic $ra, 0
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @l4()  {
 entry:
   %call = tail call i32 @k()
   %cmp = icmp slt i32 %call, 1
 ; CHECK: bgtzc
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry:
-; CHECK: nop
-; CHECK: jal
+; STATIC: nop
+; STATIC: jal
   tail call void @f(i32 signext 1)
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
+; CHECK: jic $ra, 0
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @l5()  {
 entry:
+; PIC: jialc $25, 0
   %call = tail call i32 @k()
+; PIC: jialc $25, 0
   %cmp = icmp sgt i32 %call, 0
 ; CHECK: blezc
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry:
-; CHECK: nop
-; CHECK: jal
+; STATIC: nop
+; STATIC: jal
+; PIC: jialc $25, 0
   tail call void @f(i32 signext 2) 
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
+; CHECK: jic $ra, 0
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @l6()  {
 entry:
+; PIC: jialc $25, 0
   %call = tail call i32 @k()
+; PIC: jialc $25, 0
   %cmp = icmp sgt i32 %call, -1
 ; CHECK: bltzc
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry:
-; CHECK: nop
-; CHECK: jal
+; STATIC: nop
+; STATIC: jal
+; PIC: jialc $25, 0
   tail call void @f(i32 signext 3)
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
+; CHECK: jic $ra, 0
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @l7()  {
 entry:
+; PIC: jialc $25, 0
   %call = tail call i32 @k()
   %cmp = icmp eq i32 %call, 0
 ; CHECK: bnezc
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry:
-; CHECK: nop
-; CHECK: jal
+; STATIC: nop
+; STATIC: jal
+; PIC: jialc $25, 0
   tail call void @f(i32 signext 4)
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
+; CHECK: jic $ra, 0
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @l8()  {
 entry:
+; PIC: jialc $25, 0
   %call = tail call i32 @k()
   %cmp = icmp eq i32 %call, 0
 ; CHECK: beqzc
   br i1 %cmp, label %if.end, label %if.then
 
 if.then:                                          ; preds = %entry:
-; CHECK: nop
-; CHECK: jal
+; STATIC: nop
+; STATIC: jal
+; PIC: jialc $25, 0
   tail call void @f(i32 signext 5)
   br label %if.end
 
 if.end:                                           ; preds = %entry, %if.then
+; CHECK: jic $ra, 0
   ret void
 }
+
+define i32 @l9(i8* ()* %i) #0 {
+entry:
+  %i.addr = alloca i8* ()*, align 4
+  store i8* ()* %i, i8* ()** %i.addr, align 4
+; STATIC32: jal
+; STATIC32: nop
+; PIC: jialc $25, 0
+  %call = call i32 @k()
+; PIC: jialc $25, 0
+  %cmp = icmp ne i32 %call, 0
+; CHECK: beqzc
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  %0 = load i8* ()*, i8* ()** %i.addr, align 4
+; CHECK: jialc $25, 0
+  %call1 = call i8* %0()
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+; CHECK: jic $ra, 0
+  ret i32 -1
+}

test/CodeGen/Mips/llvm-ir/call.ll

 ; Test the 'call' instruction and the tailcall variant.
 
 ; FIXME: We should remove the need for -enable-mips-tail-calls
-; RUN: llc -march=mips   -mcpu=mips32   -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
-; RUN: llc -march=mips   -mcpu=mips32r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
-; RUN: llc -march=mips   -mcpu=mips32r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
-; RUN: llc -march=mips   -mcpu=mips32r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
-; RUN: llc -march=mips   -mcpu=mips32r6 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
-; RUN: llc -march=mips   -mcpu=mips32r6 -mattr=+fp64,+nooddspreg -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
-; RUN: llc -march=mips64 -mcpu=mips4    -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
-; RUN: llc -march=mips64 -mcpu=mips64   -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
-; RUN: llc -march=mips64 -mcpu=mips64r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
-; RUN: llc -march=mips64 -mcpu=mips64r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
-; RUN: llc -march=mips64 -mcpu=mips64r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
-; RUN: llc -march=mips64 -mcpu=mips64r6 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
+; RUN: llc -march=mips   -mcpu=mips32 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
+; RUN: llc -march=mips   -mcpu=mips32r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
+; RUN: llc -march=mips   -mcpu=mips32r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
+; RUN: llc -march=mips   -mcpu=mips32r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
+; RUN: llc -march=mips   -mcpu=mips32r6 -disable-mips-delay-filler -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=R6C
+; RUN: llc -march=mips   -mcpu=mips32r6 -mattr=+fp64,+nooddspreg -disable-mips-delay-filler -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=R6C
+; RUN: llc -march=mips64 -mcpu=mips4    -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64   -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64r6 -disable-mips-delay-filler -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=R6C
 
 declare void @extern_void_void()
 declare i32 @extern_i32_void()
 declare float @extern_float_void()
 
 define i32 @call_void_void() {
 ; ALL-LABEL: call_void_void:
 
 ; O32:           lw $[[TGT:[0-9]+]], %call16(extern_void_void)($gp)
 
 ; N64:           ld $[[TGT:[0-9]+]], %call16(extern_void_void)($gp)
 
-; ALL:           jalr $[[TGT]]
+; NOT-R6C:       jalr $[[TGT]]
+; R6C:           jialc $[[TGT]], 0
 
   call void @extern_void_void()
   ret i32 0
 }
 
 define i32 @call_i32_void() {
 ; ALL-LABEL: call_i32_void:
 
 ; O32:           lw $[[TGT:[0-9]+]], %call16(extern_i32_void)($gp)
 
 ; N64:           ld $[[TGT:[0-9]+]], %call16(extern_i32_void)($gp)
 
-; ALL:           jalr $[[TGT]]
+; NOT-R6C:       jalr $[[TGT]]
+; R6C:           jialc $[[TGT]], 0
 
   %1 = call i32 @extern_i32_void()
   %2 = add i32 %1, 1
   ret i32 %2
 }
 
 define float @call_float_void() {
 ; ALL-LABEL: call_float_void:
 
 ; FIXME: Not sure why we don't use $gp directly on such a simple test. We should
 ;        look into it at some point.
 ; O32:           addu $[[GP:[0-9]+]], ${{[0-9]+}}, $25
 ; O32:           lw $[[TGT:[0-9]+]], %call16(extern_float_void)($[[GP]])
 
 ; N64:           ld $[[TGT:[0-9]+]], %call16(extern_float_void)($gp)
 
-; ALL:           jalr $[[TGT]]
+; NOT-R6C:       jalr $[[TGT]]
+; R6C:           jialc $[[TGT]], 0
 
-; O32:           move $gp, $[[GP]]
 
   %1 = call float @extern_float_void()
   %2 = fadd float %1, 1.0
   ret float %2
 }
 
 define void @musttail_call_void_void() {
 ; ALL-LABEL: musttail_call_void_void:
 
 ; O32:           lw $[[TGT:[0-9]+]], %call16(extern_void_void)($gp)
 
 ; N64:           ld $[[TGT:[0-9]+]], %call16(extern_void_void)($gp)
 
-; NOT-R6:        jr $[[TGT]]
-; R6:            r6.jr $[[TGT]]
+; ALL:           jr $[[TGT]]
 
   musttail call void @extern_void_void()
   ret void
 }
 
 define i32 @musttail_call_i32_void() {
 ; ALL-LABEL: musttail_call_i32_void:
 
 ; O32:           lw $[[TGT:[0-9]+]], %call16(extern_i32_void)($gp)
 
 ; N64:           ld $[[TGT:[0-9]+]], %call16(extern_i32_void)($gp)
 
-; NOT-R6:        jr $[[TGT]]
-; R6:            r6.jr $[[TGT]]
+; ALL:           jr $[[TGT]]
 
   %1 = musttail call i32 @extern_i32_void()
   ret i32 %1
 }
 
 define float @musttail_call_float_void() {
 ; ALL-LABEL: musttail_call_float_void:
 
 ; O32:           lw $[[TGT:[0-9]+]], %call16(extern_float_void)($gp)
 
 ; N64:           ld $[[TGT:[0-9]+]], %call16(extern_float_void)($gp)
 
-; NOT-R6:        jr $[[TGT]]
-; R6:            r6.jr $[[TGT]]
+; ALL:           jr $[[TGT]]
 
   %1 = musttail call float @extern_float_void()
   ret float %1
 }
 
 define i32 @indirect_call_void_void(void ()* %addr) {
 ; ALL-LABEL: indirect_call_void_void:
 
 ; ALL:           move $25, $4
-; ALL:           jalr $25
+; NOT-R6C:       jalr $25
+; R6C:           jialc $25, 0
+
 
   call void %addr()
   ret i32 0
 }
 
 define i32 @indirect_call_i32_void(i32 ()* %addr) {
 ; ALL-LABEL: indirect_call_i32_void:
 
 ; ALL:           move $25, $4
-; ALL:           jalr $25
+; NOT-R6C:       jalr $25
+; R6C:           jialc $25, 0
+
 
   %1 = call i32 %addr()
   %2 = add i32 %1, 1
   ret i32 %2
 }
 
 define float @indirect_call_float_void(float ()* %addr) {
 ; ALL-LABEL: indirect_call_float_void:
 
 ; ALL:           move $25, $4
-; ALL:           jalr $25
+; NOT-R6C:       jalr $25
+; R6C:           jialc $25, 0
+
 
   %1 = call float %addr()
   %2 = fadd float %1, 1.0
   ret float %2
 }
 
 ; We can't use 'musttail' here because the verifier is too conservative and
 ; prohibits any prototype difference.

 ; Check that passing undef as a double value doesn't cause machine code errors
 ; for FP64.
 declare hidden void @undef_double(i32 %this, double %volume) unnamed_addr align 2
 
 define hidden void @thunk_undef_double(i32 %this, double %volume) unnamed_addr align 2 {
 ; ALL-LABEL: thunk_undef_double:
 ; O32: # implicit-def: %A2
 ; O32: # implicit-def: %A3
-; ALL: jr $25
+; ALL:        jr $25
+
   tail call void @undef_double(i32 undef, double undef) #8
   ret void
 }
 
 ; Check that immediate addresses do not use jal.
 define i32 @jal_only_allows_symbols() {
 ; ALL-LABEL: jal_only_allows_symbols:
 
 ; ALL-NOT:       {{jal }}
 ; ALL:           addiu $[[TGT:[0-9]+]], $zero, 1234
 ; ALL-NOT:       {{jal }}
-; ALL:           jalr $[[TGT]]
+; NOT-R6C:       jalr $[[TGT]]
+; R6C:           jialc $[[TGT]], 0
 ; ALL-NOT:       {{jal }}
 
   call void () inttoptr (i32 1234 to void ()*)()
   ret i32 0
 }
 

test/CodeGen/Mips/llvm-ir/indirectbr.ll

 ; Test all important variants of the unconditional 'br' instruction.
 
 ; RUN: llc -march=mips   -mcpu=mips32   -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
 ; RUN: llc -march=mips   -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
 ; RUN: llc -march=mips   -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
 ; RUN: llc -march=mips   -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
-; RUN: llc -march=mips   -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6
+; RUN: llc -march=mips   -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6C
 ; RUN: llc -march=mips64 -mcpu=mips4    -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64   -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6
 
 define i32 @br(i8 *%addr) {
 ; ALL-LABEL: br:
 ; NOT-R6:        jr $4 # <MCInst #{{[0-9]+}} JR
-; R6:            jr $4 # <MCInst #{{[0-9]+}} JALR
+; R6C:           jic $4, 0 # <MCInst #{{[0-9]+}} JIC
+
 
 ; ALL: $BB0_1: # %L1
 ; NOT-R6:        jr $ra # <MCInst #{{[0-9]+}} JR
 ; R6:            jr $ra # <MCInst #{{[0-9]+}} JALR
+; R6C:           jr $ra # <MCInst #{{[0-9]+}} JALR
 ; ALL:           addiu $2, $zero, 0
 
 ; ALL: $BB0_2: # %L2
 ; NOT-R6:        jr $ra # <MCInst #{{[0-9]+}} JR
 ; R6:            jr $ra # <MCInst #{{[0-9]+}} JALR
+; R6C:           jr $ra # <MCInst #{{[0-9]+}} JALR
 ; ALL:           addiu $2, $zero, 1
 
 entry:
   indirectbr i8* %addr, [label %L1, label %L2]
 
 L1:
   ret i32 0
 
 L2:
   ret i32 1
 }

test/CodeGen/Mips/llvm-ir/ret.ll

 ; Test all important variants of the 'ret' instruction.
 ;
 ; For non-void returns it is necessary to have something to return so we also
 ; test constant generation here.
 ;
 ; We'll test pointer returns in a separate file since the relocation model
 ; affects it and it's undesirable to repeat the non-pointer returns for each
 ; relocation model.
 
 ; RUN: llc -march=mips   -mcpu=mips32   -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=NO-MTHC1 -check-prefix=NOT-R6
 ; RUN: llc -march=mips   -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
 ; RUN: llc -march=mips   -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
 ; RUN: llc -march=mips   -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
-; RUN: llc -march=mips   -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=R6
+; RUN: llc -march=mips   -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=R6C
 ; RUN: llc -march=mips64 -mcpu=mips4    -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64   -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
-; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=R6
+
+; FIXME: for the test ret_double_0x0, the delay slot of jr cannot be filled
+;        as mthc1 has unmodeled side effects. This is an artifact of our backend.
+;        Force the delay slot filler off to check that the sequence jr $ra; nop is
+;        turned into jic 0, $ra.
+
+; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 \
+; RUN:     -check-prefix=R6C
 
 define void @ret_void() {
 ; ALL-LABEL: ret_void:
 
 ; NOT-R6-DAG:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; R6-DAG:        jr $ra # <MCInst #{{[0-9]+}} JALR
+; R6C-DAG:       jic $ra, 0 # <MCInst #{{[0-9]+}} JIC
 
   ret void
 }
 
 define i8 @ret_i8() {
 ; ALL-LABEL: ret_i8:
 ; ALL-DAG:       addiu $2, $zero, 3
 

 ; ALL-LABEL: ret_float_0x3:
 
 ; Use a constant pool
 ; O32-DAG:       lwc1 $f0, %lo($CPI
 ; N64-DAG:       lwc1 $f0, %got_ofst($CPI
 
 ; NOT-R6-DAG:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; R6-DAG:        jr $ra # <MCInst #{{[0-9]+}} JALR
+; R6C-DAG:       jic $ra, 0 # <MCInst #{{[0-9]+}} JIC
 
 ; float constants are written as double constants
   ret float 0x36b8000000000000
 }
 
 define double @ret_double_0x0() {
 ; ALL-LABEL: ret_double_0x0:
 
 ; NO-MTHC1-DAG:  mtc1 $zero, $f0
 ; NO-MTHC1-DAG:  mtc1 $zero, $f1
 
 ; MTHC1-DAG:     mtc1 $zero, $f0
 ; MTHC1-DAG:     mthc1 $zero, $f0
 
 ; DMTC-DAG:      dmtc1 $zero, $f0
 
 ; NOT-R6-DAG:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; R6-DAG:        jr $ra # <MCInst #{{[0-9]+}} JALR
+; R6C-DAG:       jic $ra, 0 # <MCInst #{{[0-9]+}} JIC
 
   ret double 0x0000000000000000
 }
 
 define double @ret_double_0x3() {
 ; ALL-LABEL: ret_double_0x3:
 
 ; Use a constant pool
 ; O32-DAG:       ldc1 $f0, %lo($CPI
 ; N64-DAG:       ldc1 $f0, %got_ofst($CPI
 
 ; NOT-R6-DAG:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; R6-DAG:        jr $ra # <MCInst #{{[0-9]+}} JALR
+; R6C-DAG:       jic $ra, 0 # <MCInst #{{[0-9]+}} JIC
 
   ret double 0x0000000000000003
 }

test/CodeGen/Mips/mips64-f128.ll

 ; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips4 -mattr=+soft-float -O1 \
-; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=C_CC_FMT
+; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=C_CC_FMT -check-prefix=PRER6
 ; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64 -mattr=+soft-float -O1 \
-; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=C_CC_FMT
+; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=C_CC_FMT -check-prefix=PRER6
 ; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64r2 -mattr=+soft-float -O1 \
-; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=C_CC_FMT
+; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=C_CC_FMT -check-prefix=PRER6
 ; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64r6 -mattr=+soft-float -O1 \
-; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=CMP_CC_FMT
+; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=CMP_CC_FMT -check-prefix=R6
 
 @gld0 = external global fp128
 @gld1 = external global fp128
 @gld2 = external global fp128
 @gf1 = external global float
 @gd1 = external global double
 
 ; ALL-LABEL: addLD:

 
 define fp128 @load_LD_LD() {
 entry:
   %0 = load fp128, fp128* @gld1, align 16
   ret fp128 %0
 }
 
 ; ALL-LABEL: load_LD_float:
-; ALL: ld   $[[R0:[0-9]+]], %got_disp(gf1)
-; ALL: lw   $4, 0($[[R0]])
-; ALL: ld   $25, %call16(__extendsftf2)
-; ALL: jalr $25
+; ALL:   ld   $[[R0:[0-9]+]], %got_disp(gf1)
+; ALL:   lw   $4, 0($[[R0]])
+; ALL:   ld   $25, %call16(__extendsftf2)
+; PRER6: jalr $25
+; R6:    jialc $25, 0
 
 define fp128 @load_LD_float() {
 entry:
   %0 = load float, float* @gf1, align 4
   %conv = fpext float %0 to fp128
   ret fp128 %conv
 }
 
 ; ALL-LABEL: load_LD_double:
-; ALL: ld   $[[R0:[0-9]+]], %got_disp(gd1)
-; ALL: ld   $4, 0($[[R0]])
-; ALL: ld   $25, %call16(__extenddftf2)
-; ALL: jalr $25
+; ALL:   ld   $[[R0:[0-9]+]], %got_disp(gd1)
+; ALL:   ld   $4, 0($[[R0]])
+; ALL:   ld   $25, %call16(__extenddftf2)
+; PRER6: jalr $25
+; R6:    jialc $25, 0
 
 define fp128 @load_LD_double() {
 entry:
   %0 = load double, double* @gd1, align 8
   %conv = fpext double %0 to fp128
   ret fp128 %conv
 }
 
 ; ALL-LABEL: store_LD_LD:
 ; ALL: ld $[[R0:[0-9]+]], %got_disp(gld1)
 ; ALL: ld $[[R1:[0-9]+]], 0($[[R0]])
 ; ALL: ld $[[R2:[0-9]+]], 8($[[R0]])
 ; ALL: ld $[[R3:[0-9]+]], %got_disp(gld0)
 ; ALL: sd $[[R2]], 8($[[R3]])
 ; ALL: sd $[[R1]], 0($[[R3]])
 
 define void @store_LD_LD() {
 entry:
   %0 = load fp128, fp128* @gld1, align 16
   store fp128 %0, fp128* @gld0, align 16
   ret void
 }
 
 ; ALL-LABEL: store_LD_float:
-; ALL: ld   $[[R0:[0-9]+]], %got_disp(gld1)
-; ALL: ld   $4, 0($[[R0]])
-; ALL: ld   $5, 8($[[R0]])
-; ALL: ld   $25, %call16(__trunctfsf2)
-; ALL: jalr $25
-; ALL: ld   $[[R1:[0-9]+]], %got_disp(gf1)
-; ALL: sw   $2, 0($[[R1]])
+; ALL:   ld   $[[R0:[0-9]+]], %got_disp(gld1)
+; ALL:   ld   $4, 0($[[R0]])
+; ALL:   ld   $5, 8($[[R0]])
+; ALL:   ld   $25, %call16(__trunctfsf2)
+; PRER6: jalr $25
+; R6:    jialc $25, 0
+; ALL:   ld   $[[R1:[0-9]+]], %got_disp(gf1)
+; ALL:   sw   $2, 0($[[R1]])
 
 define void @store_LD_float() {
 entry:
   %0 = load fp128, fp128* @gld1, align 16
   %conv = fptrunc fp128 %0 to float
   store float %conv, float* @gf1, align 4
   ret void
 }
 
 ; ALL-LABEL: store_LD_double:
-; ALL: ld   $[[R0:[0-9]+]], %got_disp(gld1)
-; ALL: ld   $4, 0($[[R0]])
-; ALL: ld   $5, 8($[[R0]])
-; ALL: ld   $25, %call16(__trunctfdf2)
-; ALL: jalr $25
-; ALL: ld   $[[R1:[0-9]+]], %got_disp(gd1)
-; ALL: sd   $2, 0($[[R1]])
+; ALL:   ld   $[[R0:[0-9]+]], %got_disp(gld1)
+; ALL:   ld   $4, 0($[[R0]])
+; ALL:   ld   $5, 8($[[R0]])
+; ALL:   ld   $25, %call16(__trunctfdf2)
+; PRER6: jalr $25
+; R6:    jialc $25, 0
+; ALL:   ld   $[[R1:[0-9]+]], %got_disp(gd1)
+; ALL:   sd   $2, 0($[[R1]])
 
 define void @store_LD_double() {
 entry:
   %0 = load fp128, fp128* @gld1, align 16
   %conv = fptrunc fp128 %0 to double
   store double %conv, double* @gd1, align 8
   ret void
 }

 }
 
 ; ALL-LABEL: selectCC_LD:
 ; ALL:           move $[[R0:[0-9]+]], $11
 ; ALL:           move $[[R1:[0-9]+]], $10
 ; ALL:           move $[[R2:[0-9]+]], $9
 ; ALL:           move $[[R3:[0-9]+]], $8
 ; ALL:           ld   $25, %call16(__gttf2)($gp)
-; ALL:           jalr $25
+; PRER6:         jalr $25
+; R6:            jialc $25, 0
 
 ; C_CC_FMT:      slti $[[CC:[0-9]+]], $2, 1
 ; C_CC_FMT:      movz $[[R1]], $[[R3]], $[[CC]]
 ; C_CC_FMT:      movz $[[R0]], $[[R2]], $[[CC]]
 ; C_CC_FMT:      move $2, $[[R1]]
 ; C_CC_FMT:      move $4, $[[R0]]
 
 ; CMP_CC_FMT:    slt $[[CC:[0-9]+]], $zero, $2

test/MC/Mips/mips32r6/valid.s

a:
                                  # CHECK:                        #   fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
         j       a                # CHECK: j a                    # encoding: [0b000010AA,A,A,A]
                                  # CHECK:                        #   fixup A - offset: 0, value: a, kind: fixup_Mips_26
         j       1328             # CHECK: j 1328                 # encoding: [0x08,0x00,0x01,0x4c]
         jal       21100                # CHECK: jal 21100     # encoding: [0x0c,0x00,0x14,0x9b]
         jr.hb   $4               # CHECK: jr.hb $4               # encoding: [0x00,0x80,0x04,0x09]
         jalr.hb $4               # CHECK: jalr.hb $4             # encoding: [0x00,0x80,0xfc,0x09]
         jalr.hb $4, $5           # CHECK: jalr.hb $4, $5         # encoding: [0x00,0xa0,0x24,0x09]
+        jialc   $15, 16161       # CHECK: jialc $15, 16161       # encoding: [0xf8,0x0f,0x3f,0x21]
+        jic     $12, -3920       # CHECK: jic $12, -3920         # encoding: [0xd8,0x0c,0xf0,0xb0]
         ldc2    $8, -701($at)    # CHECK: ldc2 $8, -701($1)      # encoding: [0x49,0xc8,0x0d,0x43]
         lwc2    $18,-841($a2)    # CHECK: lwc2 $18, -841($6)     # encoding: [0x49,0x52,0x34,0xb7]
         sdc2    $20,629($s2)     # CHECK: sdc2 $20, 629($18)     # encoding: [0x49,0xf4,0x92,0x75]
         swc2    $25,304($s0)     # CHECK: swc2 $25, 304($16)     # encoding: [0x49,0x79,0x81,0x30]
         ll      $v0,-153($s2)    # CHECK: ll $2, -153($18)       # encoding: [0x7e,0x42,0xb3,0xb6]
         sc      $15,-40($s3)     # CHECK: sc $15, -40($19)       # encoding: [0x7e,0x6f,0xec,0x26]
         clo     $11,$a1          # CHECK: clo $11, $5            # encoding: [0x00,0xa0,0x58,0x51]
         clz     $sp,$gp          # CHECK: clz $sp, $gp           # encoding: [0x03,0x80,0xe8,0x50]