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[DAGCombine] Catch the case where extract_vector_elt can cause an any_ext while processing AND SDNodes
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Authored by sbaranga on Mar 17 2016, 10:06 AM.

Details

Summary

extract_vector_elt can cause an implicit any_ext if the types don't
match. When processing the following pattern:

(and (extract_vector_elt (load ([non_ext|any_ext|zero_ext] V))), c)

DAGCombine was ignoring the possible extend, and sometimes removing
the AND even though it was required to maintain some of the bits
in the result to 0, resulting in a miscompile.

This change fixes the issue by limiting the transformation only to
cases where the extract_vector_elt doesn't perform the implicit
extend.

Diff Detail

Repository
rL LLVM

Event Timeline

sbaranga updated this revision to Diff 50950.Mar 17 2016, 10:06 AM
sbaranga retitled this revision from to [DAGCombine] Catch the case where extract_vector_elt can cause an any_ext while processing AND SDNodes.
sbaranga updated this object.
sbaranga added reviewers: t.p.northover, jmolloy.
sbaranga added a subscriber: llvm-commits.
jmolloy accepted this revision.Mar 21 2016, 2:33 AM
jmolloy edited edge metadata.

LGTM!

This revision is now accepted and ready to land.Mar 21 2016, 2:33 AM
sbaranga closed this revision.Mar 21 2016, 4:48 AM
This revision was automatically updated to reflect the committed changes.

Thanks, James! r263935

-Silviu