Add additional Hi/Lo registers to Clang MipsTargetInfoBase

[hvarga]

Summary

This patch fixes bug https://dmz-portal.mips.com/bugz/show_bug.cgi?id=2300 by adding additional (missing) Hi/Lo registers to the Clang MipsTargetInfoBase class.

[hvarga]

I'm not sure if I added all of the necessary reviewers or even the correct ones. So please feel free to correct this if it's wrong.

[hvarga]

Are there any thoughts about this patch?

[chandlerc]

I don't know anything about MIPS and this seems a highly MIPS specific change, so I can't provide any useful review here. You have someone with MIPS specific knowledge on the review though, so you seem to have the appropriate people looped in...

[dsanders]

LGTM

Sorry for missing this when it was first posted. I've also been away for roughly half of the two weeks since Petar added me to the review.

cfe/trunk/lib/Basic/Targets.cpp

static const char *const GCCRegNames[] = {
       "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
       // Floating point register names
       "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
       "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
       "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
       "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
       // Hi/lo and condition register names
       "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
-      "$fcc5","$fcc6","$fcc7",
+      "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo",
+      "$ac3hi","$ac3lo",
       // MSA register names
       "$w0",  "$w1",  "$w2",  "$w3",  "$w4",  "$w5",  "$w6",  "$w7",
       "$w8",  "$w9",  "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
       "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
       "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
       // MSA control register names
       "$msair",      "$msacsr", "$msaaccess", "$msasave", "$msamodify",
       "$msarequest", "$msamap", "$msaunmap"

cfe/trunk/test/CodeGen/mips-inline-asm.c

void ZC () {
   asm("ll $1, %0" :: "ZC"(data));
   // CHECK: call void asm sideeffect "ll $$1, $0", "*^ZC,~{$1}"(i32* @data)
 }
 
 void R () {
   asm("lw $1, %0" :: "R"(data));
   // CHECK: call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* @data)
 }
+
+int additionalClobberedRegisters () {
+  int temp0;
+  asm volatile(
+                "mfhi %[temp0], $ac1 \n\t"
+                  : [temp0]"=&r"(temp0)
+                  :
+                  : "memory", "t0", "t1", "$ac1hi", "$ac1lo", "$ac2hi", "$ac2lo", "$ac3hi", "$ac3lo"
+  );
+  return 0;
+  // CHECK: call i32 asm sideeffect "mfhi $0, $$ac1 \0A\09", "=&r,~{memory},~{$8},~{$9},~{$ac1hi},~{$ac1lo},~{$ac2hi},~{$ac2lo},~{$ac3hi},~{$ac3lo},~{$1}"
+}