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Differential D16849

[mips][microMIPS] Implement TLBINV and TLBINVF instructions
ClosedPublic

Authored by zbuljan on Feb 3 2016, 5:11 AM.

Details

Reviewers
dsanders
vkalintiris
zoran.jovanovic
hvarga
Commits
rL261211: [mips][microMIPS] Implement TLBINV and TLBINVF instructions
Summary

The patch implements microMIPSr6 TLBINV and TLBINVF instructions.

Diff Detail

Repository
rL LLVM

Event Timeline

zbuljan updated this revision to Diff 46774.Feb 3 2016, 5:11 AM
zbuljan retitled this revision from to [mips][microMIPS] Implement TLBINV and TLBINVF instructions.
zbuljan updated this object.
zbuljan added reviewers: dsanders, hvarga, zoran.jovanovic.
zbuljan added subscribers: petarj, llvm-commits.
Herald added a reviewer: vkalintiris. · View Herald TranscriptFeb 3 2016, 5:11 AM
Herald added a subscriber: dsanders. · View Herald Transcript
vkalintiris accepted this revision.Feb 17 2016, 9:03 AM
vkalintiris edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Feb 17 2016, 9:03 AM
Closed by commit rL261211: [mips][microMIPS] Implement TLBINV and TLBINVF instructions (authored by zbuljan). · Explain WhyFeb 18 2016, 6:15 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
10 lines
16 lines
6 lines
test/
MC/
Disassembler/
Mips/
micromips32r6/
2 lines
micromips64r6/
2 lines
Mips/
micromips32r6/
2 lines
micromips64r6/
2 lines

Diff 48307

llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td

Show First 20 Lines • Show All 854 Lines • ▼ Show 20 Linesclass POOL32F_CLASS_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
let Inst{31-26} = 0b010101; let Inst{31-26} = 0b010101;
let Inst{25-21} = fs; let Inst{25-21} = fs;
let Inst{20-16} = fd; let Inst{20-16} = fd;
let Inst{15-11} = 0b00000; let Inst{15-11} = 0b00000;
let Inst{10-9} = fmt; let Inst{10-9} = fmt;
let Inst{8-0} = funct; let Inst{8-0} = funct;
} }
class POOL32A_TLBINV_FM_MMR6<string instr_asm, bits<10> funct>
: MMR6Arch<instr_asm>, MipsR6Inst {
bits<32> Inst;
let Inst{31-26} = 0x0;
let Inst{25-16} = 0x0;
let Inst{15-6} = funct;
let Inst{5-0} = 0b111100;
}

llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td

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class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>, MicroMipsR6Inst16; class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>, MicroMipsR6Inst16;
class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>, MicroMipsR6Inst16; class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>, MicroMipsR6Inst16;
class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>; class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>;
class LI16_MMR6_ENC : LI_FM_MM16; class LI16_MMR6_ENC : LI_FM_MM16;
class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>; class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>; class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6; class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>; class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
class TLBINV_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinv", 0x10d>;
class TLBINVF_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinvf", 0x14d>;
class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd, class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
RegisterOperand GPROpnd> RegisterOperand GPROpnd>
: BRANCH_DESC_BASE, MMR6Arch<instr_asm> { : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
dag InOperandList = (ins GPROpnd:$rt, opnd:$offset); dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
dag OutOperandList = (outs); dag OutOperandList = (outs);
string AsmString = !strconcat(instr_asm, "\t$rt, $offset"); string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
list<Register> Defs = [AT]; list<Register> Defs = [AT];
▲ Show 20 Lines • Show All 740 Lines • ▼ Show 20 Lines
class SWSP_MMR6_DESC class SWSP_MMR6_DESC
: MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset), : MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset),
!strconcat("sw", "\t$rt, $offset"), [], II_SW, FrmI>, !strconcat("sw", "\t$rt, $offset"), [], II_SW, FrmI>,
MMR6Arch<"sw">, MicroMipsR6Inst16 { MMR6Arch<"sw">, MicroMipsR6Inst16 {
let DecoderMethod = "DecodeMemMMSPImm5Lsl2"; let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
let mayStore = 1; let mayStore = 1;
} }
class TLBINV_MMR6_DESC_BASE<string opstr> {
dag OutOperandList = (outs);
dag InOperandList = (ins);
string AsmString = opstr;
list<dag> Pattern = [];
}
class TLBINV_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinv">;
class TLBINVF_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinvf">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Instruction Definitions // Instruction Definitions
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let DecoderNamespace = "MicroMipsR6" in { let DecoderNamespace = "MicroMipsR6" in {
def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6; def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
▲ Show 20 Lines • Show All 262 Lines • ▼ Show 20 Lines
def SELENZ_S_MMR6 : StdMMR6Rel, SELENZ_S_MMR6_ENC, SELENZ_S_MMR6_DESC, def SELENZ_S_MMR6 : StdMMR6Rel, SELENZ_S_MMR6_ENC, SELENZ_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def SELENZ_D_MMR6 : StdMMR6Rel, SELENZ_D_MMR6_ENC, SELENZ_D_MMR6_DESC, def SELENZ_D_MMR6 : StdMMR6Rel, SELENZ_D_MMR6_ENC, SELENZ_D_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def CLASS_S_MMR6 : StdMMR6Rel, CLASS_S_MMR6_ENC, CLASS_S_MMR6_DESC, def CLASS_S_MMR6 : StdMMR6Rel, CLASS_S_MMR6_ENC, CLASS_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def CLASS_D_MMR6 : StdMMR6Rel, CLASS_D_MMR6_ENC, CLASS_D_MMR6_DESC, def CLASS_D_MMR6 : StdMMR6Rel, CLASS_D_MMR6_ENC, CLASS_D_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def TLBINV_MMR6 : StdMMR6Rel, TLBINV_MMR6_ENC, TLBINV_MMR6_DESC,
ISA_MICROMIPS32R6;
def TLBINVF_MMR6 : StdMMR6Rel, TLBINVF_MMR6_ENC, TLBINVF_MMR6_DESC,
ISA_MICROMIPS32R6;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// MicroMips instruction aliases // MicroMips instruction aliases
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Show All 21 Lines

llvm/trunk/lib/Target/Mips/MipsEVAInstrInfo.td

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} }
/// Load-linked EVA, Store-conditional EVA /// Load-linked EVA, Store-conditional EVA
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def LLE : LLE_ENC, LLE_DESC, INSN_EVA; def LLE : LLE_ENC, LLE_DESC, INSN_EVA;
def SCE : SCE_ENC, SCE_DESC, INSN_EVA; def SCE : SCE_ENC, SCE_DESC, INSN_EVA;
} }
let AdditionalPredicates = [NotInMicroMips] in {
def TLBINV : TLBINV_ENC, TLBINV_DESC, INSN_EVA; def TLBINV : TLBINV_ENC, TLBINV_DESC, INSN_EVA;
def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, INSN_EVA; def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, INSN_EVA;
}
def CACHEE : CACHEE_ENC, CACHEE_DESC, INSN_EVA; def CACHEE : CACHEE_ENC, CACHEE_DESC, INSN_EVA;
def PREFE : PREFE_ENC, PREFE_DESC, INSN_EVA; def PREFE : PREFE_ENC, PREFE_DESC, INSN_EVA;

llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt

Show First 20 Lines • Show All 250 Lines • ▼ Show 20 Lines
0x54 0x62 0x08 0x38 # CHECK: seleqz.s $f1, $f2, $f3 0x54 0x62 0x08 0x38 # CHECK: seleqz.s $f1, $f2, $f3
0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8 0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8
0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3 0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3
0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8 0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8
0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3 0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3
0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4 0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
0x00 0x00 0x47 0x7c # CHECK: di 0x00 0x00 0x47 0x7c # CHECK: di
0x00 0x0f 0x47 0x7c # CHECK: di $15 0x00 0x0f 0x47 0x7c # CHECK: di $15
0x00 0x00 0x43 0x7c # CHECK: tlbinv
0x00 0x00 0x53 0x7c # CHECK: tlbinvf

llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt

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0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8 0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8
0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3 0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3
0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8 0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8
0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3 0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3
0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4 0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
0x00 0x00 0xe3 0x7c # CHECK: deret 0x00 0x00 0xe3 0x7c # CHECK: deret
0x00 0x00 0x47 0x7c # CHECK: di 0x00 0x00 0x47 0x7c # CHECK: di
0x00 0x0f 0x47 0x7c # CHECK: di $15 0x00 0x0f 0x47 0x7c # CHECK: di $15
0x00 0x00 0x43 0x7c # CHECK: tlbinv
0x00 0x00 0x53 0x7c # CHECK: tlbinvf

llvm/trunk/test/MC/Mips/micromips32r6/valid.s

Show First 20 Lines • Show All 244 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
sel.d $f0, $f2, $f4 # CHECK: sel.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x02,0xb8] sel.d $f0, $f2, $f4 # CHECK: sel.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x02,0xb8]
seleqz.s $f1, $f2, $f3 # CHECK: seleqz.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x38] seleqz.s $f1, $f2, $f3 # CHECK: seleqz.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x38]
seleqz.d $f2, $f4, $f8 # CHECK: seleqz.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x38] seleqz.d $f2, $f4, $f8 # CHECK: seleqz.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x38]
selnez.s $f1, $f2, $f3 # CHECK: selnez.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x78] selnez.s $f1, $f2, $f3 # CHECK: selnez.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x78]
selnez.d $f2, $f4, $f8 # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78] selnez.d $f2, $f4, $f8 # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78]
class.s $f2, $f3 # CHECK: class.s $f2, $f3 # encoding: [0x54,0x62,0x00,0x60] class.s $f2, $f3 # CHECK: class.s $f2, $f3 # encoding: [0x54,0x62,0x00,0x60]
class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x60] class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x60]
deret # CHECK: deret # encoding: [0x00,0x00,0xe3,0x7c] deret # CHECK: deret # encoding: [0x00,0x00,0xe3,0x7c]
tlbinv # CHECK: tlbinv # encoding: [0x00,0x00,0x43,0x7c]
tlbinvf # CHECK: tlbinvf # encoding: [0x00,0x00,0x53,0x7c]

llvm/trunk/test/MC/Mips/micromips64r6/valid.s

Show First 20 Lines • Show All 148 Lines • ▼ Show 20 Linesa:
deret # CHECK: deret # encoding: [0x00,0x00,0xe3,0x7c] deret # CHECK: deret # encoding: [0x00,0x00,0xe3,0x7c]
di # CHECK: di # encoding: [0x00,0x00,0x47,0x7c] di # CHECK: di # encoding: [0x00,0x00,0x47,0x7c]
di $0 # CHECK: di # encoding: [0x00,0x00,0x47,0x7c] di $0 # CHECK: di # encoding: [0x00,0x00,0x47,0x7c]
di $15 # CHECK: di $15 # encoding: [0x00,0x0f,0x47,0x7c] di $15 # CHECK: di $15 # encoding: [0x00,0x0f,0x47,0x7c]
ceil.l.s $f1, $f3 # CHECK: ceil.l.s $f1, $f3 # encoding: [0x54,0x23,0x13,0x3b] ceil.l.s $f1, $f3 # CHECK: ceil.l.s $f1, $f3 # encoding: [0x54,0x23,0x13,0x3b]
ceil.l.d $f1, $f3 # CHECK: ceil.l.d $f1, $f3 # encoding: [0x54,0x23,0x53,0x3b] ceil.l.d $f1, $f3 # CHECK: ceil.l.d $f1, $f3 # encoding: [0x54,0x23,0x53,0x3b]
floor.l.s $f1, $f3 # CHECK: floor.l.s $f1, $f3 # encoding: [0x54,0x23,0x03,0x3b] floor.l.s $f1, $f3 # CHECK: floor.l.s $f1, $f3 # encoding: [0x54,0x23,0x03,0x3b]
floor.l.d $f1, $f3 # CHECK: floor.l.d $f1, $f3 # encoding: [0x54,0x23,0x43,0x3b] floor.l.d $f1, $f3 # CHECK: floor.l.d $f1, $f3 # encoding: [0x54,0x23,0x43,0x3b]
tlbinv # CHECK: tlbinv # encoding: [0x00,0x00,0x43,0x7c]
tlbinvf # CHECK: tlbinvf # encoding: [0x00,0x00,0x53,0x7c]
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