[mips][micromips] Implement DSBH, DSHD, DSLL, DSLL32, DSLLV, DSRA, DSRA32 and DSRAV instructions

[hvarga]

Summary

Patch implements DSBH, DSHD, DSLL, DSLL32, DSLLV, DSRA, DSRA32 and DSRAV instructions for microMIPS64r6.

[sdardis]

LGTM with one pseudo nit: class POOL32S_2RSA5B0_FM_MMR6 should be class POOL32S_2R_SA5_FM_MMR6. I believe I've mentioned it in other patches which define that class.

[sdardis]

Apologies, you can retain the name of POOL32S_2RSA5B0_FM_MMR6 as it follows the existing style.

llvm/trunk/lib/Target/Mips/MicroMips64r6InstrFormats.td

class PCREL18_FM_MMR6<bits<3> funct> : MipsR6Inst {
 
   bits<32> Inst;
 
   let Inst{31-26} = 0b011110;
   let Inst{25-21} = rt;
   let Inst{20-18} = funct;
   let Inst{17-0} = imm;
 }
+
+class POOL32S_2R_FM_MMR6<bits<10> funct> {
+  bits<5> rt;
+  bits<5> rs;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b010110;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rs;
+  let Inst{15-6} = funct;
+  let Inst{5-0} = 0b111100;
+}
+
+class POOL32S_2RSA5B0_FM_MMR6<bits<9> funct> {
+  bits<5> rt;
+  bits<5> rs;
+  bits<5> sa;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b010110;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rs;
+  let Inst{15-11} = sa;
+  let Inst{10-9} = 0b00;
+  let Inst{8-0} = funct;
+}
+
+class POOL32S_3R_FM_MMR6<bits<9> funct> {
+  bits<5> rt;
+  bits<5> rs;
+  bits<5> rd;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b010110;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rs;
+  let Inst{15-11} = rd;
+  let Inst{10-9} = 0b00;
+  let Inst{8-0} = funct;
+}

llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td

 class DADDU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"daddu", 0b101010000>;
 class LDPC_MMR646_ENC : PCREL18_FM_MMR6<0b110>;
 class DSUB_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dsub", 0b110010000>;
 class DSUBU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dsubu", 0b111010000>;
 class DMUL_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmul", 0b000011000>;
 class DMUH_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmuh", 0b001011000>;
 class DMULU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmulu", 0b010011000>;
 class DMUHU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmuhu", 0b011011000>;
+class DSBH_MM64R6_ENC : POOL32S_2R_FM_MMR6<0b0111101100>;
+class DSHD_MM64R6_ENC : POOL32S_2R_FM_MMR6<0b1111101100>;
+class DSLL_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<0b000000000>;
+class DSLL32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<0b000001000>;
+class DSLLV_MM64R6_ENC : POOL32S_3R_FM_MMR6<0b000010000>;
+class DSRAV_MM64R6_ENC : POOL32S_3R_FM_MMR6<0b010010000>;
+class DSRA_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<0b010000000>;
+class DSRA32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<0b010000100>;
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Descriptions
 //
 //===----------------------------------------------------------------------===//
 
 class DAUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>

 
 class DMUL_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmul", GPR64Opnd, II_DMUL, mul>;
 class DMUH_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmuh", GPR64Opnd, II_DMUH,
                                               mulhs>;
 class DMULU_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMULU>;
 class DMUHU_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmuhu", GPR64Opnd, II_DMUHU,
                                                mulhu>;
 
+class DSBH_DSHD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
+    : MMR6Arch<instr_asm>, MipsR6Inst {
+  dag OutOperandList = (outs GPROpnd:$rt);
+  dag InOperandList = (ins GPROpnd:$rs);
+  string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
+  bit hasSideEffects = 0;
+  list<dag> Pattern = [];
+  InstrItinClass Itinerary = NoItinerary;
+  Format Form = FrmR;
+}
+
+class DSBH_MM64R6_DESC : DSBH_DSHD_DESC_BASE<"dsbh", GPR64Opnd>;
+class DSHD_MM64R6_DESC : DSBH_DSHD_DESC_BASE<"dshd", GPR64Opnd>;
+
+class DSLL_DSLL32_DESC_BASE<string instr_asm, Operand ImmOpnd,
+                            InstrItinClass itin,
+                            SDPatternOperator OpNode = null_frag,
+                            SDPatternOperator PO = null_frag>
+    : MMR6Arch<instr_asm>, MipsR6Inst {
+  dag OutOperandList = (outs GPR64Opnd:$rt);
+  dag InOperandList = (ins GPR64Opnd:$rs, ImmOpnd:$sa);
+  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
+  InstrItinClass Itinerary = itin;
+  list<dag> Pattern = [(set GPR64Opnd:$rt, (OpNode GPR64Opnd:$rs, PO:$sa))];
+  string TwoOperandAliasConstraint = "$rs = $rt";
+}
+
+class DSLL_MM64R6_DESC : DSLL_DSLL32_DESC_BASE<"dsll", uimm6, II_DSLL, shl,
+                                               immZExt6>;
+class DSLL32_MM64R6_DESC : DSLL_DSLL32_DESC_BASE<"dsll32", uimm5, II_DSLL32>;
+
+class DSLLV_DSRAV_MM64R6_DESC_BASE<string instr_asm, RegisterOperand RO,
+                                   InstrItinClass itin,
+                                   SDPatternOperator OpNode = null_frag>
+    : MMR6Arch<instr_asm>, MipsR6Inst {
+  dag OutOperandList = (outs RO:$rd);
+  dag InOperandList = (ins RO:$rt, GPR32Opnd:$rs);
+  string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs");
+  list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))];
+  InstrItinClass Itinerary = itin;
+  Format Form = FrmR;
+}
+
+class DSLLV_MM64R6_DESC : DSLLV_DSRAV_MM64R6_DESC_BASE<"dsllv", GPR64Opnd,
+                                                       II_DSLLV, shl>;
+class DSRAV_MM64R6_DESC : DSLLV_DSRAV_MM64R6_DESC_BASE<"dsrav", GPR64Opnd,
+                                                       II_DSRAV, sra>;
+
+class DSRA_DSRA32_MM64R6_DESC_BASE<string instr_asm, Operand ImmOpnd,
+                              RegisterOperand RO, InstrItinClass itin,
+                              SDPatternOperator OpNode = null_frag,
+                              SDPatternOperator PF = null_frag>
+    : MMR6Arch<instr_asm>, MipsR6Inst {
+  dag OutOperandList = (outs RO:$rt);
+  dag InOperandList = (ins RO:$rs, ImmOpnd:$sa);
+  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
+  list<dag> Pattern = [(set RO:$rt, (OpNode RO:$rs, PF:$sa))];
+  InstrItinClass Itinerary = itin;
+  Format Form = FrmR;
+  string BaseOpcode = instr_asm;
+}
+
+class DSRA_MM64R6_DESC : DSRA_DSRA32_MM64R6_DESC_BASE<"dsra", uimm6, GPR64Opnd,
+                                                      II_DSRA, sra, immZExt6>;
+class DSRA32_MM64R6_DESC : DSRA_DSRA32_MM64R6_DESC_BASE<"dsra32", uimm5,
+                                                        GPR64Opnd, II_DSRA32>;
+
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
 //
 //===----------------------------------------------------------------------===//
 
 let DecoderNamespace = "MicroMipsR6" in {
   def DAUI_MM64R6 : StdMMR6Rel, DAUI_MMR6_DESC, DAUI_MMR6_ENC, ISA_MICROMIPS64R6;
let DecoderNamespace = "MicroMipsR6" in {
   def DMUL_MM64R6 : R6MMR6Rel, DMUL_MM64R6_DESC, DMUL_MM64R6_ENC,
                     ISA_MICROMIPS64R6;
   def DMUH_MM64R6 : R6MMR6Rel, DMUH_MM64R6_DESC, DMUH_MM64R6_ENC,
                     ISA_MICROMIPS64R6;
   def DMULU_MM64R6 : R6MMR6Rel, DMULU_MM64R6_DESC, DMULU_MM64R6_ENC,
                      ISA_MICROMIPS64R6;
   def DMUHU_MM64R6 : R6MMR6Rel, DMUHU_MM64R6_DESC, DMUHU_MM64R6_ENC,
                      ISA_MICROMIPS64R6;
+  def DSBH_MM64R6 : R6MMR6Rel, DSBH_MM64R6_DESC, DSBH_MM64R6_ENC,
+                    ISA_MICROMIPS64R6;
+  def DSHD_MM64R6 : R6MMR6Rel, DSHD_MM64R6_DESC, DSHD_MM64R6_ENC,
+                    ISA_MICROMIPS64R6;
+  def DSLL_MM64R6 : R6MMR6Rel, DSLL_MM64R6_DESC, DSLL_MM64R6_ENC,
+                    ISA_MICROMIPS64R6;
+  def DSLL32_MM64R6 : R6MMR6Rel, DSLL32_MM64R6_DESC, DSLL32_MM64R6_ENC,
+                    ISA_MICROMIPS64R6;
+  def DSLLV_MM64R6 : R6MMR6Rel, DSLLV_MM64R6_DESC, DSLLV_MM64R6_ENC,
+                     ISA_MICROMIPS64R6;
+  def DSRAV_MM64R6 : R6MMR6Rel, DSRAV_MM64R6_DESC, DSRAV_MM64R6_ENC,
+                    ISA_MICROMIPS64R6;
+  def DSRA_MM64R6 : R6MMR6Rel, DSRA_MM64R6_DESC, DSRA_MM64R6_ENC,
+                    ISA_MICROMIPS64R6;
+  def DSRA32_MM64R6 : R6MMR6Rel, DSRA32_MM64R6_DESC, DSRA32_MM64R6_ENC,
+                    ISA_MICROMIPS64R6;
 }
 
 //===----------------------------------------------------------------------===//
 //
 // Arbitrary patterns that map to one or more instructions
 //
 //===----------------------------------------------------------------------===//
 

llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td

 def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>;
 def AND64  : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>;
 def OR64   : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>;
 def XOR64  : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>;
 def NOR64  : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>;
 }
 
 /// Shift Instructions
-def DSLL   : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, immZExt6>,
+let AdditionalPredicates = [NotInMicroMips] in {
+  def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, immZExt6>,
                SRA_FM<0x38, 0>, ISA_MIPS3;
+}
 def DSRL   : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, immZExt6>,
              SRA_FM<0x3a, 0>, ISA_MIPS3;
-def DSRA   : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, immZExt6>,
+let AdditionalPredicates = [NotInMicroMips] in {
+  def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, immZExt6>,
              SRA_FM<0x3b, 0>, ISA_MIPS3;
+}
+let AdditionalPredicates = [NotInMicroMips] in {
   def DSLLV  : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
              SRLV_FM<0x14, 0>, ISA_MIPS3;
+}
 def DSRLV  : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
              SRLV_FM<0x16, 0>, ISA_MIPS3;
+let AdditionalPredicates = [NotInMicroMips] in {
   def DSRAV  : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
                SRLV_FM<0x17, 0>, ISA_MIPS3;
+}
+let AdditionalPredicates = [NotInMicroMips] in {
   def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
                SRA_FM<0x3c, 0>, ISA_MIPS3;
+}
 def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
              SRA_FM<0x3e, 0>, ISA_MIPS3;
+let AdditionalPredicates = [NotInMicroMips] in {
   def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
                SRA_FM<0x3f, 0>, ISA_MIPS3;
+}
 
 // Rotate Instructions
 def DROTR  : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
                               immZExt6>,
              SRA_FM<0x3a, 1>, ISA_MIPS64R2;
 def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
              SRLV_FM<0x16, 1>, ISA_MIPS64R2;
 def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>,
             ISA_MIPS32R2;
 }
 
 /// Count Leading
 def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>, ISA_MIPS64_NOT_64R6;
 def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>, ISA_MIPS64_NOT_64R6;
 
 /// Double Word Swap Bytes/HalfWords
+let AdditionalPredicates = [NotInMicroMips] in {
   def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>, ISA_MIPS64R2;
   def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>, ISA_MIPS64R2;
+}
 
 def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
 
 let isCodeGenOnly = 1 in
 def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
 
 let AdditionalPredicates = [NotInMicroMips] in {
   // The 'pos + size' constraints are enforced by the code that lowers into

llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt

 0x00 0xa4 0x18 0x98 # CHECK: mulu $3, $4, $5
 0x00 0xa4 0x18 0xd8 # CHECK: muhu $3, $4, $5
 0x58 0xa4 0x18 0x18 # CHECK: dmul $3, $4, $5
 0x58 0xa4 0x18 0x58 # CHECK: dmuh $3, $4, $5
 0x58 0xa4 0x18 0x98 # CHECK: dmulu $3, $4, $5
 0x58 0xa4 0x18 0xd8 # CHECK: dmuhu $3, $4, $5
 0x22 0x04 0x10 0x08 # CHECK: lwp $16, 8($4)
 0x22 0x04 0x90 0x08 # CHECK: swp $16, 8($4)
+0x58 0x64 0x7b 0x3c # CHECK: dsbh $3, $4
+0x58 0x64 0xfb 0x3c # CHECK: dshd $3, $4
+0x58 0x64 0x28 0x00 # CHECK: dsll $3, $4, 5
+0x58 0x64 0x28 0x08 # CHECK: dsll32 $3, $4, 5
+0x58 0xa6 0x20 0x10 # CHECK: dsllv $4, $5, $6
+0x58 0x85 0x28 0x80 # CHECK: dsra $4, $5, 5
+0x58 0xa6 0x20 0x90 # CHECK: dsrav $4, $5, $6

llvm/trunk/test/MC/Mips/micromips64r6/invalid.s

# RUN: FileCheck %s < %t1
   lwp $31, 8($4)               # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
                                # FIXME: This ought to point at the $34 but memory is treated as one operand.
   lwp $16, 8($34)              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
   lwp $16, 4096($4)            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
   lwp $16, 8($16)              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
   swp $31, 8($4)               # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swp $16, 8($34)              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
   swp $16, 4096($4)            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
+  dsll $3, $4, 64              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
+  dsll $3, $4, -1              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
+  dsll32 $3, $4, 32            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
+  dsll32 $3, $4, -1            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
+  dsra $4, $5, 64              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
+  dsra $4, $5, -1              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
+  dsra32 $4, $5, 32            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
+  dsra32 $4, $5, -1            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate

llvm/trunk/test/MC/Mips/micromips64r6/valid.s

a:
         mulu $3, $4, $5          # CHECK mulu $3, $4, $5          # encoding: [0x00,0xa4,0x18,0x98]
         muhu $3, $4, $5          # CHECK muhu $3, $4, $5          # encoding: [0x00,0xa4,0x18,0xd8]
         dmul $3, $4, $5          # CHECK dmul $3, $4, $5          # encoding: [0x58,0xa4,0x18,0x18]
         dmuh $3, $4, $5          # CHECK dmuh $3, $4, $5          # encoding: [0x58,0xa4,0x18,0x58]
         dmulu $3, $4, $5         # CHECK dmulu $3, $4, $5         # encoding: [0x58,0xa4,0x18,0x98]
         dmuhu $3, $4, $5         # CHECK dmuhu $3, $4, $5         # encoding: [0x58,0xa4,0x18,0xd8]
         lwp $16, 8($4)           # CHECK: lwp $16, 8($4)          # encoding: [0x22,0x04,0x10,0x08]
         swp $16, 8($4)           # CHECK: swp $16, 8($4)          # encoding: [0x22,0x04,0x90,0x08]
+        dsbh $3, $4              # CHECK: dsbh $3, $4             # encoding: [0x58,0x64,0x7b,0x3c]
+        dshd $3, $4              # CHECK: dshd $3, $4             # encoding: [0x58,0x64,0xfb,0x3c]
+        dsll $3, $4, 5           # CHECK: dsll $3, $4, 5          # encoding: [0x58,0x64,0x28,0x00]
+        dsll32 $3, $4, 5         # CHECK: dsll32 $3, $4, 5        # encoding: [0x58,0x64,0x28,0x08]
+        dsllv $4, $5, $6         # CHECK: dsllv $4, $5, $6        # encoding: [0x58,0xa6,0x20,0x10]
+        dsra $4, $5, 5           # CHECK: dsra $4, $5, 5          # encoding: [0x58,0x85,0x28,0x80]
+        dsra32 $4, $5, 5         # CHECK: dsra32 $4, $5, 5        # encoding: [0x58,0x85,0x28,0x84]
+        dsrav $4, $5, $6         # CHECK: dsrav $4, $5, $6        # encoding: [0x58,0xa6,0x20,0x90]
 
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