[mips][microMIPS] Add CodeGen support for AND*, OR16, OR*, XOR*, NOT16 and NOR instructions

[zbuljan]

Summary

The patch adds CodeGen support for microMIPSr6 AND16, ANDI16, AND, ANDI, OR16, OR, ORI, XOR16, XOR, XORI, NOT16 and NOR instructions:

• updated .ll files with tests for microMIPSr6 AND*, OR16, OR*, XOR*, NOT16 and NOR instructions
• added alias definitions for microMIPS and microMIPSr6 instructions
• added DAG pattern definitions for proper selection of instructions
• separated microMIPSr6 instructions from equivalent MIPS instructions using NotInMicroMips predicate
• added tests for the standard encodings

[sdardis]

lib/Target/Mips/MicroMips32r6InstrInfo.td

1226 ↗

(On Diff #46366)

Shouldn't the immediate by of type uimm16 ?

1229 ↗

(On Diff #46366)

Here too.

lib/Target/Mips/MicroMipsInstrInfo.td

1006 ↗

(On Diff #46366)

Can you provide a terminating } for the let Predicates = [InMicroMips] (line 966 of the diff} here.

1010 ↗

(On Diff #46366)

Move the "let Predicates = [InMicroMips] in {" from line 1022 to line 1010. Then you can remove the closing branch on line 1020 and have this aliases section guarded clearly.

lib/Target/Mips/MipsInstrInfo.td

1368–1384 ↗

(On Diff #46366)

These two "let AdditionalPredicates =" blocks can be joined together.

test/CodeGen/Mips/llvm-ir/and.ll

45 ↗

(On Diff #46366)

Near ToT is not giving me this nop and the other nops. I see it with certain broken combinations of options (e.g. mips64 and +micromips).

155–252 ↗

(On Diff #46366)

Check some other constants other than 4 that are encodable. Also add 1 or 2 cases where the value is not encodable in 16bit form and check that a normal andi is generated.

test/CodeGen/Mips/llvm-ir/or.ll

266 ↗

(On Diff #46366)

As with the andi case, check some other short form encodable constants and add 1or 2 cases where the constant is not encodable in the 16bit form for andi.

test/MC/Mips/micromips32r6/valid.s

253 ↗

(On Diff #46366)

Indentation for the "#encoding..."

test/MC/Mips/micromips64r6/valid.s

153–169 ↗

(On Diff #46366)

Indentation for the "#encoding..."

[zbuljan]

Rebased to work with TOT.
Changed immediate to uimm16 in alias definitions for AND instruction.
Added DAG patterns to description clases of AND, OR and XOR instructions.
Added AddedComplexity parameter to definitions of AND16, OR16 and XOR16 instructions so they can be prioritized during instruction selection.
Updated and.ll and or.ll with IR code to check some constants that are and are not encodable in 16-bit form.
Added invalid tests for operand checking.

[sdardis]

Some nits and a question as to why llvm is generating 2 instructions instead of 1.

lib/Target/Mips/MicroMips32r6InstrInfo.td

605 ↗

(On Diff #57028)

Requires AddedComplexity = 1.

1007 ↗

(On Diff #57028)

Also requires AddedComplexity = 1

lib/Target/Mips/MicroMipsInstrInfo.td

1052 ↗

(On Diff #57028)

This needs to be covered with "let Predicates = [InMicroMips] in {"

test/CodeGen/Mips/llvm-ir/or.ll

173–174 ↗

(On Diff #57028)

Why is LLVM generating two instructions here rather than a single long form 'or'? Similarly for xor.

test/MC/Disassembler/Mips/micromips32r3/valid-el.txt

197 ↗

(On Diff #57028)

This requires not16 and nor. The 32bit andi, ori, xori, not are not required as they already exist in this file.

test/MC/Disassembler/Mips/micromips32r3/valid.txt

197 ↗

(On Diff #57028)

See my above comment.

test/MC/Disassembler/Mips/micromips32r6/valid.txt

315 ↗

(On Diff #57028)

andi, ori, xori are already exist in this file, so there's no need to duplicate them.

test/MC/Mips/micromips-alu-instructions.s

132 ↗

(On Diff #57028)

Already covered by and $9, $6, 17767

136 ↗

(On Diff #57028)

Already covered by xor $9, $6, 17767

test/MC/Mips/micromips64r6/valid.s

15 ↗

(On Diff #57028)

This also needs to check not16.

[zbuljan]

lib/Target/Mips/MicroMipsInstrInfo.td

1052 ↗

(On Diff #57028)

It should be already covered with ISA_MICROMIPS predicate. Do you still want me to change it?

[zbuljan]

Rebased to work with TOT.
Added AddedComplexity = 1 to ORI and NOT16 description classes.
Added DAG patterns for proper selection of ORI and XORI instructions.
Separated MIPS ANDI, ORI and XORI from equivalent microMIPS instructions using ISA_NOT_MICROMIPS predicate.
Updated not.ll with tests for NOR instruction.
Removed redundant asm/disasm tests.
Added asm/disasm tests for the instructions which were not covered.

[sdardis]

Can you explain the shift away from "let AdditionalPredicates = [NotInMicroMips] in" to using ISA_NOT_MICROMIPS for ANDi, ORi, XORi?

test/CodeGen/Mips/llvm-ir/and.ll

28 ↗

(On Diff #59022)

The check prefix MMR6 should be changed to MM or MMALL, since you're using it with microMIPSR3, microMIPSR6 and microMIPS64R6.

567–571 ↗

(On Diff #59022)

These can be reduced down to 'ALL:'

test/MC/Mips/micromips/invalid.s

121 ↗

(On Diff #59022)

This should also check 'not' with a register and immediate. This should also go into the other invalid files you're changing.

[zbuljan]

As I can see now there is no reason for usage of ISA_NOT_MICROMIPS instead of "let AdditionalPredicates = [NotInMicroMips] in" so I'll change it.

[zbuljan]

Rebased to work with TOT.
Removed ISA_NOT_MICROMIPS because it is not needed and used "let AdditionalPredicates = [NotInMicroMips]" instead.
Replaced MMR6 check prefix with MM.
Added 'not' with a register and immediate to invalid tests.

[sdardis]

LGTM.

llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp

bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) {
   case Mips::JALR:
     // jalr $ra, $r1 => jalr $r1
     return isReg<Mips::RA>(MI, 0) && printAlias("jalr", MI, 1, OS);
   case Mips::JALR64:
     // jalr $ra, $r1 => jalr $r1
     return isReg<Mips::RA_64>(MI, 0) && printAlias("jalr", MI, 1, OS);
   case Mips::NOR:
   case Mips::NOR_MM:
+  case Mips::NOR_MMR6:
     // nor $r0, $r1, $zero => not $r0, $r1
     return isReg<Mips::ZERO>(MI, 2) && printAlias("not", MI, 0, 1, OS);
   case Mips::NOR64:
     // nor $r0, $r1, $zero => not $r0, $r1
     return isReg<Mips::ZERO_64>(MI, 2) && printAlias("not", MI, 0, 1, OS);
   case Mips::OR:
     // or $r0, $r1, $zero => move $r0, $r1
     return isReg<Mips::ZERO>(MI, 2) && printAlias("move", MI, 0, 1, OS);

llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td

class DIVMOD_MMR6_DESC_BASE<string opstr, RegisterOperand GPROpnd,
   // This instruction doesn't trap division by zero itself. We must insert
   // teq instructions as well.
   bit usesCustomInserter = 1;
 }
 class DIV_MMR6_DESC  : DIVMOD_MMR6_DESC_BASE<"div", GPR32Opnd, sdiv>;
 class DIVU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"divu", GPR32Opnd, udiv>;
 class MOD_MMR6_DESC  : DIVMOD_MMR6_DESC_BASE<"mod", GPR32Opnd, srem>;
 class MODU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"modu", GPR32Opnd, urem>;
-class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>;
-class ANDI_MMR6_DESC : ArithLogicI<"andi", uimm16, GPR32Opnd>;
-class NOR_MMR6_DESC : ArithLogicR<"nor", GPR32Opnd>;
-class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd>;
-class ORI_MMR6_DESC : ArithLogicI<"ori", uimm16, GPR32Opnd>;
-class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>;
-class XORI_MMR6_DESC : ArithLogicI<"xori", uimm16, GPR32Opnd>;
+class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>;
+class ANDI_MMR6_DESC : ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI>;
+class NOR_MMR6_DESC : LogicNOR<"nor", GPR32Opnd>;
+class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>;
+class ORI_MMR6_DESC : ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
+                                  or> {
+  int AddedComplexity = 1;
+}
+class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>;
+class XORI_MMR6_DESC : ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI,
+                                   immZExt16, xor>;
 
 class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO,
                   SDPatternOperator OpNode = null_frag,
                   InstrItinClass Itin = NoItinerary,
                   ComplexPattern Addr = addr> :
   InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
          [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
   let DecoderMethod = "DecodeMem";

 }
 class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd>;
 class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd>;
 class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
       MMR6Arch<"addu16"> {
   int AddedComplexity = 1;
 }
 class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
-      MMR6Arch<"and16">;
+      MMR6Arch<"and16"> {
+  int AddedComplexity = 1;
+}
 class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
       MMR6Arch<"andi16">;
-class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16">;
+class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16"> {
+  int AddedComplexity = 1;
+}
 class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
       MMR6Arch<"or16"> {
   int AddedComplexity = 1;
 }
 class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
       MMR6Arch<"sll16">;
 class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
       MMR6Arch<"srl16">;
 class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16">, MMR6Arch<"break16">,
       MicroMipsR6Inst16;
 class LI16_MMR6_DESC : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>,
       MMR6Arch<"li16">, MicroMipsR6Inst16, IsAsCheapAsAMove;
 class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">,
       MicroMipsR6Inst16;
 class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16">, MMR6Arch<"sdbbp16">,
       MicroMipsR6Inst16;
 class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
       MMR6Arch<"subu16">, MicroMipsR6Inst16 {
   int AddedComplexity = 1;
 }
 class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
-      MMR6Arch<"xor16">;
+      MMR6Arch<"xor16"> {
+  int AddedComplexity = 1;
+}
 
 class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
   dag OutOperandList = (outs GPR32Opnd:$rt);
   dag InOperandList = (ins mem:$addr);
   string AsmString = "lw\t$rt, $addr";
   let DecoderMethod = "DecodeMemMMImm16";
   let canFoldAsLoad = 1;
   let mayLoad = 1;
def : MipsInstAlias<"mfhc0 $rt, $rs",
                     (MFHC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
                     ISA_MICROMIPS32R6;
 def : MipsInstAlias<"jalrc.hb $rs", (JALRC_HB_MMR6 RA, GPR32Opnd:$rs), 1>,
                     ISA_MICROMIPS32R6;
 def : MipsInstAlias<"dvp", (DVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
 def : MipsInstAlias<"evp", (EVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
 def : MipsInstAlias<"jalrc $rs", (JALRC_MMR6 RA, GPR32Opnd:$rs), 1>,
       ISA_MICROMIPS32R6;
+def : MipsInstAlias<"and $rs, $rt, $imm",
+                    (ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
+                    ISA_MICROMIPS32R6;
+def : MipsInstAlias<"and $rs, $imm",
+                    (ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
+                    ISA_MICROMIPS32R6;
+def : MipsInstAlias<"or $rs, $rt, $imm",
+                    (ORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
+                    ISA_MICROMIPS32R6;
+def : MipsInstAlias<"or $rs, $imm",
+                    (ORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
+                    ISA_MICROMIPS32R6;
+def : MipsInstAlias<"xor $rs, $rt, $imm",
+                    (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
+                    ISA_MICROMIPS32R6;
+def : MipsInstAlias<"xor $rs, $imm",
+                    (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
+                    ISA_MICROMIPS32R6;
+def : MipsInstAlias<"not $rt, $rs",
+                    (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>,
+                    ISA_MICROMIPS32R6;
 
 //===----------------------------------------------------------------------===//
 //
 // MicroMips arbitrary patterns that map to one or more instructions
 //
 //===----------------------------------------------------------------------===//
 
 def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
def : MipsPat<(select i32:$cond, immz, i32:$f),
               (SELEQZ_MMR6 i32:$f, i32:$cond)>,
               ISA_MICROMIPS32R6;
 
 defm : SelectInt_Pats<i32, OR_MM, XORI_MMR6, SLTi_MM, SLTiu_MM, SELEQZ_MMR6,
                       SELNEZ_MMR6, immZExt16, i32>, ISA_MICROMIPS32R6;
 
 defm S_MMR6 : Cmp_Pats<f32, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6;
 defm D_MMR6 : Cmp_Pats<f64, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6;
+
+def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
+              (ANDI16_MMR6 GPRMM16:$src, immZExtAndi16:$imm)>,
+              ISA_MICROMIPS32R6;
+def : MipsPat<(and GPR32:$src, immZExt16:$imm),
+              (ANDI_MMR6 GPR32:$src, immZExt16:$imm)>, ISA_MICROMIPS32R6;
+def : MipsPat<(i32 immZExt16:$imm),
+              (XORI_MMR6 ZERO, immZExt16:$imm)>, ISA_MICROMIPS32R6;
+def : MipsPat<(not GPRMM16:$in),
+              (NOT16_MMR6 GPRMM16:$in)>, ISA_MICROMIPS32R6;
+def : MipsPat<(not GPR32:$in),
+              (NOR_MMR6 GPR32Opnd:$in, ZERO)>, ISA_MICROMIPS32R6;

llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td

let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
   def ADDi_MM  : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
                  ADDI_FM_MM<0x4>;
   def SLTi_MM  : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
                  SLTI_FM_MM<0x24>;
   def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
                  SLTI_FM_MM<0x2c>;
   def ANDi_MM  : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
                  ADDI_FM_MM<0x34>;
-  def ORi_MM   : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
-                 ADDI_FM_MM<0x14>;
-  def XORi_MM  : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
-                 ADDI_FM_MM<0x1c>;
+  def ORi_MM   : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
+                                    or>, ADDI_FM_MM<0x14>;
+  def XORi_MM  : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI,
+                                    immZExt16, xor>, ADDI_FM_MM<0x1c>;
   def LUi_MM   : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM_MM;
 
   def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
                      LW_FM_MM<0xc>;
 
   /// Arithmetic Instructions (3-Operand, R-Type)
   def ADDu_MM  : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
                  ADD_FM_MM<0, 0x150>;
let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
   def PREFX_MM : PrefetchIndexed<"prefx">, POOL32F_PREFX_FM_MM<0x15, 0x1A0>;
 }
 
 let DecoderNamespace = "MicroMips" in {
   def RDHWR_MM : MMRel, R6MMR6Rel, ReadHardware<GPR32Opnd, HWRegsOpnd>,
                  RDHWR_FM_MM, ISA_MICROMIPS32_NOT_MIPS32R6;
 }
 
-let Predicates = [InMicroMips] in {
-
 //===----------------------------------------------------------------------===//
 // MicroMips arbitrary patterns that map to one or more instructions
 //===----------------------------------------------------------------------===//
 
+let Predicates = [InMicroMips] in {
   def : MipsPat<(i32 immLi16:$imm),
                 (LI16_MM immLi16:$imm)>;
   def : MipsPat<(i32 immSExt16:$imm),
                 (ADDiu_MM ZERO, immSExt16:$imm)>;
   def : MipsPat<(i32 immZExt16:$imm),
                 (ORi_MM ZERO, immZExt16:$imm)>;
+
+  def : MipsPat<(not GPRMM16:$in),
+                (NOT16_MM GPRMM16:$in)>;
   def : MipsPat<(not GPR32:$in),
                 (NOR_MM GPR32Opnd:$in, ZERO)>;
 
   def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),
                 (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>;
   def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
                 (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>;
   def : MipsPat<(add GPR32:$src, immSExt16:$imm),
                 (ADDiu_MM GPR32:$src, immSExt16:$imm)>;
 
   def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
                 (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>;
   def : MipsPat<(and GPR32:$src, immZExt16:$imm),
                 (ANDi_MM GPR32:$src, immZExt16:$imm)>;
 
   def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm),
                 (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
   def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
                 (SLL_MM GPR32:$src, immZExt5:$imm)>;
   def : MipsPat<(shl GPR32:$lhs, GPR32:$rhs),
                 (SLLV_MM GPR32:$lhs, GPR32:$rhs)>;
 
   def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
                 (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
   def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
                 (SRL_MM GPR32:$src, immZExt5:$imm)>;
   def : MipsPat<(srl GPR32:$lhs, GPR32:$rhs),
                 (SRLV_MM GPR32:$lhs, GPR32:$rhs)>;
 
   def : MipsPat<(sra GPR32:$src, immZExt5:$imm),
                 (SRA_MM GPR32:$src, immZExt5:$imm)>;
   def : MipsPat<(sra GPR32:$lhs, GPR32:$rhs),
                 (SRAV_MM GPR32:$lhs, GPR32:$rhs)>;
 
   def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
                 (SW16_MM GPRMM16:$src, addrimm4lsl2:$addr)>;
   def : MipsPat<(store GPR32:$src, addr:$addr),
                 (SW_MM GPR32:$src, addr:$addr)>;
 
   def : MipsPat<(load addrimm4lsl2:$addr),
                 (LW16_MM addrimm4lsl2:$addr)>;
   def : MipsPat<(load addr:$addr),
                 (LW_MM addr:$addr)>;
   def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
                 (SUBu_MM GPR32:$lhs, GPR32:$rhs)>;
+}
 
 let AddedComplexity = 40 in {
   def : MipsPat<(i32 (sextloadi16 addrRegImm:$a)),
                 (LH_MM addrRegImm:$a)>;
 }
 def : MipsPat<(atomic_load_16 addr:$a),
               (LH_MM addr:$a)>;
 def : MipsPat<(i32 (extloadi16 addr:$src)),
               (LHu_MM addr:$src)>;
 
 //===----------------------------------------------------------------------===//
 // MicroMips instruction aliases
 //===----------------------------------------------------------------------===//
 
 class UncondBranchMMPseudo<string opstr> :
   MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
                     !strconcat(opstr, "\t$offset")>;
 
 def B_MM_Pseudo : UncondBranchMMPseudo<"b">, ISA_MICROMIPS;
 
+let Predicates = [InMicroMips] in {
   def SDIV_MM_Pseudo : MultDivPseudo<SDIV_MM, ACC64, GPR32Opnd, MipsDivRem,
                                      II_DIV, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
   def UDIV_MM_Pseudo : MultDivPseudo<UDIV_MM, ACC64, GPR32Opnd, MipsDivRemU,
                                      II_DIVU, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
 
   def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;
   def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>;
   def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>;
-}
-
-let Predicates = [InMicroMips] in {
   def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MIPS32R2;
   def : MipsInstAlias<"di", (DI_MM ZERO), 1>, ISA_MIPS32R2;
   def : MipsInstAlias<"teq $rs, $rt",
                       (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
   def : MipsInstAlias<"tge $rs, $rt",
                       (TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
   def : MipsInstAlias<"tgeu $rs, $rt",
                       (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
   def : MipsInstAlias<"tlt $rs, $rt",
                       (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
   def : MipsInstAlias<"tltu $rs, $rt",
                       (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
   def : MipsInstAlias<"tne $rs, $rt",
                       (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
   def : MipsInstAlias<"sll $rd, $rt, $rs",
                       (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
   def : MipsInstAlias<"sra $rd, $rt, $rs",
                       (SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
   def : MipsInstAlias<"srl $rd, $rt, $rs",
                       (SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
   def : MipsInstAlias<"sll $rd, $rt",
                       (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
   def : MipsInstAlias<"sra $rd, $rt",
                       (SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
   def : MipsInstAlias<"srl $rd, $rt",
                       (SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
   def : MipsInstAlias<"sll $rd, $shamt",
                       (SLL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
   def : MipsInstAlias<"sra $rd, $shamt",
                       (SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
   def : MipsInstAlias<"srl $rd, $shamt",
                       (SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
   def : MipsInstAlias<"rotr $rt, $imm",
                       (ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>;
   def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>;
+  def : MipsInstAlias<"and $rs, $rt, $imm",
+                      (ANDi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
+  def : MipsInstAlias<"and $rs, $imm",
+                      (ANDi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
+  def : MipsInstAlias<"or $rs, $rt, $imm",
+                      (ORi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
+  def : MipsInstAlias<"or $rs, $imm",
+                      (ORi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
+  def : MipsInstAlias<"xor $rs, $rt, $imm",
+                      (XORi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
+  def : MipsInstAlias<"xor $rs, $imm",
+                      (XORi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
+  def : MipsInstAlias<"not $rt, $rs",
+                      (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
 }

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

 // Instruction definition
 //===----------------------------------------------------------------------===//
 //===----------------------------------------------------------------------===//
 // MipsI Instructions
 //===----------------------------------------------------------------------===//
 
 /// Arithmetic Instructions (ALU Immediate)
 let AdditionalPredicates = [NotInMicroMips] in {
   def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16_relaxed, GPR32Opnd,
                                              II_ADDIU, immSExt16, add>,
               ADDI_FM<0x9>, IsAsCheapAsAMove;
-}
-def ADDi  : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd, II_ADDI>, ADDI_FM<0x8>,
-            ISA_MIPS1_NOT_32R6_64R6;
-def SLTi  : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
-            SLTI_FM<0xa>;
-def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
-            SLTI_FM<0xb>;
-let AdditionalPredicates = [NotInMicroMips] in {
-def ANDi  : MMRel, StdMMR6Rel,
+
+  def ANDi : MMRel, StdMMR6Rel,
              ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>,
              ADDI_FM<0xc>;
-}
-def ORi   : MMRel, StdMMR6Rel,
+  def ORi  : MMRel, StdMMR6Rel,
              ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>,
              ADDI_FM<0xd>;
-def XORi  : MMRel, StdMMR6Rel,
+  def XORi : MMRel, StdMMR6Rel,
              ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>,
              ADDI_FM<0xe>;
+}
+def ADDi  : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd, II_ADDI>, ADDI_FM<0x8>,
+            ISA_MIPS1_NOT_32R6_64R6;
+def SLTi  : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
+            SLTI_FM<0xa>;
+def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
+            SLTI_FM<0xb>;
 def LUi   : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM;
 let AdditionalPredicates = [NotInMicroMips] in {
 /// Arithmetic Instructions (3-Operand, R-Type)
 def ADDu  : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
             ADD_FM<0, 0x21>;
 def SUBu  : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
             ADD_FM<0, 0x23>;
 }
 let Defs = [HI0, LO0] in
 def MUL   : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
             ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
 def ADD   : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>, ADD_FM<0, 0x20>;
 def SUB   : MMRel, StdMMR6Rel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>, ADD_FM<0, 0x22>;
 def SLT   : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
 def SLTu  : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
 let AdditionalPredicates = [NotInMicroMips] in {
 def AND   : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
             ADD_FM<0, 0x24>;
 def OR    : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
             ADD_FM<0, 0x25>;
 def XOR   : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
             ADD_FM<0, 0x26>;
-}
 def NOR   : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
+}
 
 /// Shift Instructions
 let AdditionalPredicates = [NotInMicroMips] in {
 def SLL  : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
                                    immZExt5>, SRA_FM<0, 0>;
 def SRL  : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
                                    immZExt5>, SRA_FM<2, 0>;
 def SRA  : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,

 def : MipsInstAlias<
           "and $rs, $imm",
           (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
 let Predicates = [NotInMicroMips] in {
 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
 }
 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
-def : MipsInstAlias<"not $rt, $rs",
-                    (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
 def : MipsInstAlias<"neg $rt, $rs",
                     (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
 def : MipsInstAlias<"negu $rt",
                     (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
 def : MipsInstAlias<"negu $rt, $rs",
                     (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
 def : MipsInstAlias<
           "slt $rs, $rt, $imm",
           (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
 def : MipsInstAlias<
           "sltu $rt, $rs, $imm",
           (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
+let AdditionalPredicates = [NotInMicroMips] in {
+  def : MipsInstAlias<
+          "and $rs, $rt, $imm",
+          (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
+  def : MipsInstAlias<
+          "and $rs, $imm",
+          (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
   def : MipsInstAlias<
           "xor $rs, $rt, $imm",
           (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
   def : MipsInstAlias<
           "xor $rs, $imm",
           (XORi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
   def : MipsInstAlias<
           "or $rs, $rt, $imm",
           (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
   def : MipsInstAlias<
           "or $rs, $imm",
           (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
-let AdditionalPredicates = [NotInMicroMips] in {
+  def : MipsInstAlias<
+          "not $rt, $rs",
+          (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
   def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
 }
 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>;
 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, COP2Opnd:$rd, 0), 0>;
 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 COP2Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
 let AdditionalPredicates = [NotInMicroMips] in {
 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
 }

llvm/trunk/test/CodeGen/Mips/fcmp.ll

 ; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.ueq.s $f12, $f14
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
 ; MM64R6-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
-; MMR6-DAG:      nor $[[T2:[0-9]+]], $[[T1]]
+; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
 ; MMR6-DAG:      andi16 $2, $[[T2]], 1
 
   %1 = fcmp one float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ord_f32(float %a, float %b) nounwind {

 ; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.un.s  $f12, $f14
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
 ; MM64R6-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
-; MMR6-DAG:      nor $[[T2:[0-9]+]], $[[T1]], $zero
+; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
 ; MMR6-DAG:      andi16 $2, $[[T2]], 1
 
   %1 = fcmp ord float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ueq_f32(float %a, float %b) nounwind {

 ; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.eq.s $f12, $f14
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
 ; MM64R6-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
-; MMR6-DAG:      nor $[[T2:[0-9]+]], $[[T1]], $zero
+; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
 ; MMR6-DAG:      andi16 $2, $[[T2]], 1
 
   %1 = fcmp une float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @uno_f32(float %a, float %b) nounwind {

 ; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.ueq.d $f12, $f14
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
 ; MM64R6-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
-; MMR6-DAG:      nor $[[T2:[0-9]+]], $[[T1]], $zero
+; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
 ; MMR6-DAG:      andi16 $2, $[[T2]], 1
 
   %1 = fcmp one double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ord_f64(double %a, double %b) nounwind {

 ; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.un.d $f12, $f14
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
 ; MM64R6-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
-; MMR6-DAG:      nor $[[T2:[0-9]+]], $[[T1]], $zero
+; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
 ; MMR6-DAG:      andi16 $2, $[[T2]], 1
 
   %1 = fcmp ord double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ueq_f64(double %a, double %b) nounwind {

 ; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
 ; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
 ; MM32R3-DAG:    c.eq.d  $f12, $f14
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
 ; MM64R6-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
-; MMR6-DAG:      nor $[[T2:[0-9]+]], $[[T1]], $zero
+; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
 ; MMR6-DAG:      andi16 $2, $[[T2]], 1
 
   %1 = fcmp une double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @uno_f64(double %a, double %b) nounwind {

llvm/trunk/test/CodeGen/Mips/llvm-ir/and.ll

 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MM32
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MM32
+; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MM64
 
 define signext i1 @and_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: and_i1:
 
-  ; ALL:          and     $2, $4, $5
+  ; GP32:         and     $2, $4, $5
+
+  ; GP64:         and     $2, $4, $5
+
+  ; MM:           and16   $[[T0:[0-9]+]], $5
+  ; MM:           move    $2, $[[T0]]
 
   %r = and i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @and_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: and_i8:
 
-  ; ALL:          and     $2, $4, $5
+  ; GP32:         and     $2, $4, $5
+
+  ; GP64:         and     $2, $4, $5
+
+  ; MM:           and16   $[[T0:[0-9]+]], $5
+  ; MM:           move    $2, $[[T0]]
 
   %r = and i8 %a, %b
   ret i8 %r
 }
 
 define signext i16 @and_i16(i16 signext %a, i16 signext %b) {
 entry:
 ; ALL-LABEL: and_i16:
 
-  ; ALL:          and     $2, $4, $5
+  ; GP32:         and     $2, $4, $5
+
+  ; GP64:         and     $2, $4, $5
+
+  ; MM:           and16   $[[T0:[0-9]+]], $5
+  ; MM:           move    $2, $[[T0]]
 
   %r = and i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @and_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: and_i32:
 
   ; GP32:         and     $2, $4, $5
 
   ; GP64:         and     $[[T0:[0-9]+]], $4, $5
   ; GP64:         sll     $2, $[[T0]], 0
 
+  ; MM32:         and16   $[[T0:[0-9]+]], $5
+  ; MM32:         move    $2, $[[T0]]
+
+  ; MM64:         and     $[[T0:[0-9]+]], $4, $5
+  ; MM64:         sll     $2, $[[T0]], 0
+
   %r = and i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @and_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: and_i64:
 
   ; GP32:         and     $2, $4, $6
   ; GP32:         and     $3, $5, $7
 
   ; GP64:         and     $2, $4, $5
 
+  ; MM32:         and16   $[[T0:[0-9]+]], $6
+  ; MM32:         and16   $[[T1:[0-9]+]], $7
+  ; MM32:         move    $2, $[[T0]]
+  ; MM32:         move    $3, $[[T1]]
+
+  ; MM64:         and     $2, $4, $5
+
   %r = and i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @and_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: and_i128:
 
   ; GP32:         lw      $[[T0:[0-9]+]], 24($sp)
   ; GP32:         lw      $[[T1:[0-9]+]], 20($sp)
   ; GP32:         lw      $[[T2:[0-9]+]], 16($sp)
   ; GP32:         and     $2, $4, $[[T2]]
   ; GP32:         and     $3, $5, $[[T1]]
   ; GP32:         and     $4, $6, $[[T0]]
   ; GP32:         lw      $[[T3:[0-9]+]], 28($sp)
   ; GP32:         and     $5, $7, $[[T3]]
 
   ; GP64:         and     $2, $4, $6
   ; GP64:         and     $3, $5, $7
 
+  ; MM32:         lw      $[[T0:[0-9]+]], 20($sp)
+  ; MM32:         lw      $[[T1:[0-9]+]], 16($sp)
+  ; MM32:         and16   $[[T1]], $4
+  ; MM32:         and16   $[[T0]], $5
+  ; MM32:         lw      $[[T2:[0-9]+]], 24($sp)
+  ; MM32:         and16   $[[T2]], $6
+  ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
+  ; MM32:         and16   $[[T3]], $7
+
+  ; MM64:         and     $2, $4, $6
+  ; MM64:         and     $3, $5, $7
+
   %r = and i128 %a, %b
   ret i128 %r
 }
+
+define signext i1 @and_i1_4(i1 signext %b) {
+entry:
+; ALL-LABEL: and_i1_4:
+
+  ; GP32:         addiu   $2, $zero, 0
+
+  ; GP64:         addiu   $2, $zero, 0
+
+  ; MM:           lui     $2, 0
+
+  %r = and i1 4, %b
+  ret i1 %r
+}
+
+define signext i8 @and_i8_4(i8 signext %b) {
+entry:
+; ALL-LABEL: and_i8_4:
+
+  ; GP32:         andi    $2, $4, 4
+
+  ; GP64:         andi    $2, $4, 4
+
+  ; MM:           andi16  $2, $4, 4
+
+  %r = and i8 4, %b
+  ret i8 %r
+}
+
+define signext i16 @and_i16_4(i16 signext %b) {
+entry:
+; ALL-LABEL: and_i16_4:
+
+  ; GP32:         andi    $2, $4, 4
+
+  ; GP64:         andi    $2, $4, 4
+
+  ; MM:           andi16  $2, $4, 4
+
+  %r = and i16 4, %b
+  ret i16 %r
+}
+
+define signext i32 @and_i32_4(i32 signext %b) {
+entry:
+; ALL-LABEL: and_i32_4:
+
+  ; GP32:         andi    $2, $4, 4
+
+  ; GP64:         andi    $2, $4, 4
+
+  ; MM:           andi16  $2, $4, 4
+
+  %r = and i32 4, %b
+  ret i32 %r
+}
+
+define signext i64 @and_i64_4(i64 signext %b) {
+entry:
+; ALL-LABEL: and_i64_4:
+
+  ; GP32:         andi    $3, $5, 4
+  ; GP32:         addiu   $2, $zero, 0
+
+  ; GP64:         andi    $2, $4, 4
+
+  ; MM32:         andi16  $3, $5, 4
+  ; MM32:         lui     $2, 0
+
+  ; MM64:         andi    $2, $4, 4
+
+  %r = and i64 4, %b
+  ret i64 %r
+}
+
+define signext i128 @and_i128_4(i128 signext %b) {
+entry:
+; ALL-LABEL: and_i128_4:
+
+  ; GP32:         andi    $5, $7, 4
+  ; GP32:         addiu   $2, $zero, 0
+  ; GP32:         addiu   $3, $zero, 0
+  ; GP32:         addiu   $4, $zero, 0
+
+  ; GP64:         andi    $3, $5, 4
+  ; GP64:         daddiu  $2, $zero, 0
+
+  ; MM32:         andi16  $5, $7, 4
+  ; MM32:         lui     $2, 0
+  ; MM32:         lui     $3, 0
+  ; MM32:         lui     $4, 0
+
+  ; MM64:         andi    $3, $5, 4
+  ; MM64:         daddiu  $2, $zero, 0
+
+  %r = and i128 4, %b
+  ret i128 %r
+}
+
+define signext i1 @and_i1_31(i1 signext %b) {
+entry:
+; ALL-LABEL: and_i1_31:
+
+  ; ALL:          move    $2, $4
+
+  %r = and i1 31, %b
+  ret i1 %r
+}
+
+define signext i8 @and_i8_31(i8 signext %b) {
+entry:
+; ALL-LABEL: and_i8_31:
+
+  ; GP32:         andi    $2, $4, 31
+
+  ; GP64:         andi    $2, $4, 31
+
+  ; MM:           andi16  $2, $4, 31
+
+  %r = and i8 31, %b
+  ret i8 %r
+}
+
+define signext i16 @and_i16_31(i16 signext %b) {
+entry:
+; ALL-LABEL: and_i16_31:
+
+  ; GP32:         andi    $2, $4, 31
+
+  ; GP64:         andi    $2, $4, 31
+
+  ; MM:           andi16  $2, $4, 31
+
+  %r = and i16 31, %b
+  ret i16 %r
+}
+
+define signext i32 @and_i32_31(i32 signext %b) {
+entry:
+; ALL-LABEL: and_i32_31:
+
+  ; GP32:         andi    $2, $4, 31
+
+  ; GP64:         andi    $2, $4, 31
+
+  ; MM:           andi16  $2, $4, 31
+
+  %r = and i32 31, %b
+  ret i32 %r
+}
+
+define signext i64 @and_i64_31(i64 signext %b) {
+entry:
+; ALL-LABEL: and_i64_31:
+
+  ; GP32:         andi    $3, $5, 31
+  ; GP32:         addiu   $2, $zero, 0
+
+  ; GP64:         andi    $2, $4, 31
+
+  ; MM32:         andi16  $3, $5, 31
+  ; MM32:         lui     $2, 0
+
+  ; MM64:         andi    $2, $4, 31
+
+  %r = and i64 31, %b
+  ret i64 %r
+}
+
+define signext i128 @and_i128_31(i128 signext %b) {
+entry:
+; ALL-LABEL: and_i128_31:
+
+  ; GP32:         andi    $5, $7, 31
+  ; GP32:         addiu   $2, $zero, 0
+  ; GP32:         addiu   $3, $zero, 0
+  ; GP32:         addiu   $4, $zero, 0
+
+  ; GP64:         andi    $3, $5, 31
+  ; GP64:         daddiu  $2, $zero, 0
+
+  ; MM32:         andi16  $5, $7, 31
+  ; MM32:         lui     $2, 0
+  ; MM32:         lui     $3, 0
+  ; MM32:         lui     $4, 0
+
+  ; MM64:         andi    $3, $5, 31
+  ; MM64:         daddiu  $2, $zero, 0
+
+  %r = and i128 31, %b
+  ret i128 %r
+}
+
+define signext i1 @and_i1_255(i1 signext %b) {
+entry:
+; ALL-LABEL: and_i1_255:
+
+  ; ALL:          move    $2, $4
+
+  %r = and i1 255, %b
+  ret i1 %r
+}
+
+define signext i8 @and_i8_255(i8 signext %b) {
+entry:
+; ALL-LABEL: and_i8_255:
+
+  ; ALL:          move    $2, $4
+
+  %r = and i8 255, %b
+  ret i8 %r
+}
+
+define signext i16 @and_i16_255(i16 signext %b) {
+entry:
+; ALL-LABEL: and_i16_255:
+
+  ; GP32:         andi    $2, $4, 255
+
+  ; GP64:         andi    $2, $4, 255
+
+  ; MM:           andi16  $2, $4, 255
+
+  %r = and i16 255, %b
+  ret i16 %r
+}
+
+define signext i32 @and_i32_255(i32 signext %b) {
+entry:
+; ALL-LABEL: and_i32_255:
+
+  ; GP32:         andi    $2, $4, 255
+
+  ; GP64:         andi    $2, $4, 255
+
+  ; MM:           andi16  $2, $4, 255
+
+  %r = and i32 255, %b
+  ret i32 %r
+}
+
+define signext i64 @and_i64_255(i64 signext %b) {
+entry:
+; ALL-LABEL: and_i64_255:
+
+  ; GP32:         andi    $3, $5, 255
+  ; GP32:         addiu   $2, $zero, 0
+
+  ; GP64:         andi    $2, $4, 255
+
+  ; MM32:         andi16  $3, $5, 255
+  ; MM32:         lui     $2, 0
+
+  ; MM64:         andi    $2, $4, 255
+
+  %r = and i64 255, %b
+  ret i64 %r
+}
+
+define signext i128 @and_i128_255(i128 signext %b) {
+entry:
+; ALL-LABEL: and_i128_255:
+
+  ; GP32:         andi    $5, $7, 255
+  ; GP32:         addiu   $2, $zero, 0
+  ; GP32:         addiu   $3, $zero, 0
+  ; GP32:         addiu   $4, $zero, 0
+
+  ; GP64:         andi    $3, $5, 255
+  ; GP64:         daddiu  $2, $zero, 0
+
+  ; MM32:         andi16  $5, $7, 255
+  ; MM32:         lui     $2, 0
+  ; MM32:         lui     $3, 0
+  ; MM32:         lui     $4, 0
+
+  ; MM64:         andi    $3, $5, 255
+  ; MM64:         daddiu  $2, $zero, 0
+
+  %r = and i128 255, %b
+  ret i128 %r
+}
+
+define signext i1 @and_i1_32768(i1 signext %b) {
+entry:
+; ALL-LABEL: and_i1_32768:
+
+  ; GP32:         addiu  $2, $zero, 0
+
+  ; GP64:         addiu  $2, $zero, 0
+
+  ; MM:           lui    $2, 0
+
+  %r = and i1 32768, %b
+  ret i1 %r
+}
+
+define signext i8 @and_i8_32768(i8 signext %b) {
+entry:
+; ALL-LABEL: and_i8_32768:
+
+  ; GP32:         addiu  $2, $zero, 0
+
+  ; GP64:         addiu  $2, $zero, 0
+
+  ; MM:           lui    $2, 0
+
+  %r = and i8 32768, %b
+  ret i8 %r
+}
+
+define signext i16 @and_i16_32768(i16 signext %b) {
+entry:
+; ALL-LABEL: and_i16_32768:
+
+  ; GP32:         addiu  $[[T0:[0-9]+]], $zero, -32768
+  ; GP32:         and    $2, $4, $[[T0]]
+
+  ; GP64:         addiu  $[[T0:[0-9]+]], $zero, -32768
+  ; GP64:         and    $2, $4, $[[T0]]
+
+  ; MM:           addiu  $2, $zero, -32768
+  ; MM:           and16  $2, $4
+
+  %r = and i16 32768, %b
+  ret i16 %r
+}
+
+define signext i32 @and_i32_32768(i32 signext %b) {
+entry:
+; ALL-LABEL: and_i32_32768:
+
+  ; GP32:         andi    $2, $4, 32768
+
+  ; GP64:         andi    $2, $4, 32768
+
+  ; MM:           andi16  $2, $4, 32768
+
+  %r = and i32 32768, %b
+  ret i32 %r
+}
+
+define signext i64 @and_i64_32768(i64 signext %b) {
+entry:
+; ALL-LABEL: and_i64_32768:
+
+  ; GP32:         andi    $3, $5, 32768
+  ; GP32:         addiu   $2, $zero, 0
+
+  ; GP64:         andi    $2, $4, 32768
+
+  ; MM32:         andi16  $3, $5, 32768
+  ; MM32:         lui     $2, 0
+
+  ; MM64:         andi    $2, $4, 32768
+
+  %r = and i64 32768, %b
+  ret i64 %r
+}
+
+define signext i128 @and_i128_32768(i128 signext %b) {
+entry:
+; ALL-LABEL: and_i128_32768:
+
+  ; GP32:         andi    $5, $7, 32768
+  ; GP32:         addiu   $2, $zero, 0
+  ; GP32:         addiu   $3, $zero, 0
+  ; GP32:         addiu   $4, $zero, 0
+
+  ; GP64:         andi    $3, $5, 32768
+  ; GP64:         daddiu  $2, $zero, 0
+
+  ; MM32:         andi16  $5, $7, 32768
+  ; MM32:         lui     $2, 0
+  ; MM32:         lui     $3, 0
+  ; MM32:         lui     $4, 0
+
+  ; MM64:         andi    $3, $5, 32768
+  ; MM64:         daddiu  $2, $zero, 0
+
+  %r = and i128 32768, %b
+  ret i128 %r
+}
+
+define signext i1 @and_i1_65(i1 signext %b) {
+entry:
+; ALL-LABEL: and_i1_65:
+
+  ; ALL:          move    $2, $4
+
+  %r = and i1 65, %b
+  ret i1 %r
+}
+
+define signext i8 @and_i8_65(i8 signext %b) {
+entry:
+; ALL-LABEL: and_i8_65:
+
+  ; ALL:          andi    $2, $4, 65
+
+  %r = and i8 65, %b
+  ret i8 %r
+}
+
+define signext i16 @and_i16_65(i16 signext %b) {
+entry:
+; ALL-LABEL: and_i16_65:
+
+  ; ALL:          andi    $2, $4, 65
+
+  %r = and i16 65, %b
+  ret i16 %r
+}
+
+define signext i32 @and_i32_65(i32 signext %b) {
+entry:
+; ALL-LABEL: and_i32_65:
+
+  ; ALL:          andi    $2, $4, 65
+
+  %r = and i32 65, %b
+  ret i32 %r
+}
+
+define signext i64 @and_i64_65(i64 signext %b) {
+entry:
+; ALL-LABEL: and_i64_65:
+
+  ; GP32:         andi    $3, $5, 65
+  ; GP32:         addiu   $2, $zero, 0
+
+  ; GP64:         andi    $2, $4, 65
+
+  ; MM32:         andi    $3, $5, 65
+  ; MM32:         lui     $2, 0
+
+  ; MM64:         andi    $2, $4, 65
+
+  %r = and i64 65, %b
+  ret i64 %r
+}
+
+define signext i128 @and_i128_65(i128 signext %b) {
+entry:
+; ALL-LABEL: and_i128_65:
+
+  ; GP32:         andi    $5, $7, 65
+  ; GP32:         addiu   $2, $zero, 0
+  ; GP32:         addiu   $3, $zero, 0
+  ; GP32:         addiu   $4, $zero, 0
+
+  ; GP64:         andi    $3, $5, 65
+  ; GP64:         daddiu  $2, $zero, 0
+
+  ; MM32:         andi    $5, $7, 65
+  ; MM32:         lui     $2, 0
+  ; MM32:         lui     $3, 0
+  ; MM32:         lui     $4, 0
+
+  ; MM64:         andi    $3, $5, 65
+  ; MM64:         daddiu  $2, $zero, 0
+
+  %r = and i128 65, %b
+  ret i128 %r
+}
+
+define signext i1 @and_i1_256(i1 signext %b) {
+entry:
+; ALL-LABEL: and_i1_256:
+
+  ; GP32:         addiu   $2, $zero, 0
+
+  ; GP64:         addiu   $2, $zero, 0
+
+  ; MM:           lui     $2, 0
+
+  %r = and i1 256, %b
+  ret i1 %r
+}
+
+define signext i8 @and_i8_256(i8 signext %b) {
+entry:
+; ALL-LABEL: and_i8_256:
+
+  ; GP32:         addiu   $2, $zero, 0
+
+  ; GP64:         addiu   $2, $zero, 0
+
+  ; MM:           lui     $2, 0
+
+  %r = and i8 256, %b
+  ret i8 %r
+}
+
+define signext i16 @and_i16_256(i16 signext %b) {
+entry:
+; ALL-LABEL: and_i16_256:
+
+  ; ALL:          andi    $2, $4, 256
+
+  %r = and i16 256, %b
+  ret i16 %r
+}
+
+define signext i32 @and_i32_256(i32 signext %b) {
+entry:
+; ALL-LABEL: and_i32_256:
+
+  ; ALL:          andi    $2, $4, 256
+
+  %r = and i32 256, %b
+  ret i32 %r
+}
+
+define signext i64 @and_i64_256(i64 signext %b) {
+entry:
+; ALL-LABEL: and_i64_256:
+
+  ; GP32:         andi    $3, $5, 256
+  ; GP32:         addiu   $2, $zero, 0
+
+  ; GP64:         andi    $2, $4, 256
+
+  ; MM32:         andi    $3, $5, 256
+  ; MM32:         lui     $2, 0
+
+  ; MM64:         andi    $2, $4, 256
+
+  %r = and i64 256, %b
+  ret i64 %r
+}
+
+define signext i128 @and_i128_256(i128 signext %b) {
+entry:
+; ALL-LABEL: and_i128_256:
+
+  ; GP32:         andi    $5, $7, 256
+  ; GP32:         addiu   $2, $zero, 0
+  ; GP32:         addiu   $3, $zero, 0
+  ; GP32:         addiu   $4, $zero, 0
+
+  ; GP64:         andi    $3, $5, 256
+  ; GP64:         daddiu  $2, $zero, 0
+
+  ; MM32:         andi    $5, $7, 256
+  ; MM32:         lui     $2, 0
+  ; MM32:         lui     $3, 0
+  ; MM32:         lui     $4, 0
+
+  ; MM64:         andi    $3, $5, 256
+  ; MM64:         daddiu  $2, $zero, 0
+
+  %r = and i128 256, %b
+  ret i128 %r
+}

llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll

; ALL-LABEL: ashr_i64:
 
   ; MMR6:       srav      $[[T0:[0-9]+]], $4, $7
   ; MMR6:       andi16    $[[T1:[0-9]+]], $7, 32
   ; MMR6:       seleqz    $[[T2:[0-9]+]], $[[T0]], $[[T1]]
   ; MMR6:       sra       $[[T3:[0-9]+]], $4, 31
   ; MMR6:       selnez    $[[T4:[0-9]+]], $[[T3]], $[[T1]]
   ; MMR6:       or        $[[T5:[0-9]+]], $[[T4]], $[[T2]]
   ; MMR6:       srlv      $[[T6:[0-9]+]], $5, $7
-  ; MMR6:       not       $[[T7:[0-9]+]], $7
-  ; MMR6:       sll16     $[[T8:[0-9]+]], $4, 1
-  ; MMR6:       sllv      $[[T9:[0-9]+]], $[[T8]], $[[T7]]
+  ; MMR6:       sll16     $[[T7:[0-9]+]], $4, 1
+  ; MMR6:       not16     $[[T8:[0-9]+]], $7
+  ; MMR6:       sllv      $[[T9:[0-9]+]], $[[T7]], $[[T8]]
   ; MMR6:       or16      $[[T10:[0-9]+]], $[[T6]]
   ; MMR6:       seleqz    $[[T11:[0-9]+]], $[[T10]], $[[T1]]
   ; MMR6:       selnez    $[[T12:[0-9]+]], $[[T0]], $[[T1]]
   ; MMR6:       or        $3, $[[T12]], $[[T11]]
 
   %r = ashr i64 %a, %b
   ret i64 %r
 }

llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll

; ALL-LABEL: lshr_i64:
   ; MMR3:       or16      $[[T4:[0-9]+]], $[[T0]]
   ; MMR3:       srlv      $[[T5:[0-9]+]], $4, $7
   ; MMR3:       andi16    $[[T6:[0-9]+]], $7, 32
   ; MMR3:       movn      $[[T7:[0-9]+]], $[[T5]], $[[T6]]
   ; MMR3:       lui       $[[T8:[0-9]+]], 0
   ; MMR3:       movn      $2, $[[T8]], $[[T6]]
 
   ; MMR6:       srlv      $[[T0:[0-9]+]], $5, $7
-  ; MMR6:       not       $[[T1:[0-9]+]], $7
-  ; MMR6:       sll16     $[[T2:[0-9]+]], $4, 1
-  ; MMR6:       sllv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+  ; MMR6:       sll16     $[[T1:[0-9]+]], $4, 1
+  ; MMR6:       not16     $[[T2:[0-9]+]], $7
+  ; MMR6:       sllv      $[[T3:[0-9]+]], $[[T1]], $[[T2]]
   ; MMR6:       or16      $[[T4:[0-9]+]], $[[T0]]
   ; MMR6:       andi16    $[[T5:[0-9]+]], $7, 32
   ; MMR6:       seleqz    $[[T6:[0-9]+]], $[[T4]], $[[T5]]
   ; MMR6:       srlv      $[[T7:[0-9]+]], $4, $7
   ; MMR6:       selnez    $[[T8:[0-9]+]], $[[T7]], $[[T5]]
   ; MMR6:       or        $3, $[[T8]], $[[T6]]
   ; MMR6:       seleqz    $2, $[[T7]], $[[T5]]
 

llvm/trunk/test/CodeGen/Mips/llvm-ir/not.ll

+; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MM32
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MM32
+; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MM64
+
+define signext i1 @not_i1(i1 signext %a) {
+entry:
+; ALL-LABEL: not_i1:
+
+  ; GP32:         not     $2, $4
+
+  ; GP64:         not     $2, $4
+
+  ; MM:           not16   $2, $4
+
+  %r = xor i1 %a, -1
+  ret i1 %r
+}
+
+define signext i8 @not_i8(i8 signext %a) {
+entry:
+; ALL-LABEL: not_i8:
+
+  ; GP32:         not     $2, $4
+
+  ; GP64:         not     $2, $4
+
+  ; MM:           not16   $2, $4
+
+  %r = xor i8 %a, -1
+  ret i8 %r
+}
+
+define signext i16 @not_i16(i16 signext %a) {
+entry:
+; ALL-LABEL: not_i16:
+
+  ; GP32:         not     $2, $4
+
+  ; GP64:         not     $2, $4
+
+  ; MM:           not16   $2, $4
+
+  %r = xor i16 %a, -1
+  ret i16 %r
+}
+
+define signext i32 @not_i32(i32 signext %a) {
+entry:
+; ALL-LABEL: not_i32:
+
+  ; GP32:         not     $2, $4
+
+  ; GP64:         not     $2, $4
+
+  ; MM:           not16   $2, $4
+
+  %r = xor i32 %a, -1
+  ret i32 %r
+}
+
+define signext i64 @not_i64(i64 signext %a) {
+entry:
+; ALL-LABEL: not_i64:
+
+  ; GP32:         not     $2, $4
+  ; GP32:         not     $3, $5
+
+  ; GP64:         daddiu  $[[T0:[0-9]+]], $zero, -1
+  ; GP64:         xor     $2, $4, $[[T0]]
+
+  ; MM32:         not16   $2, $4
+  ; MM32:         not16   $3, $5
+
+  ; MM64:         daddiu  $[[T0:[0-9]+]], $zero, -1
+  ; MM64:         xor     $2, $4, $[[T0]]
+
+  %r = xor i64 %a, -1
+  ret i64 %r
+}
+
+define signext i128 @not_i128(i128 signext %a) {
+entry:
+; ALL-LABEL: not_i128:
+
+  ; GP32:         not     $2, $4
+  ; GP32:         not     $3, $5
+  ; GP32:         not     $4, $6
+  ; GP32:         not     $5, $7
+
+  ; GP64:         daddiu  $[[T0:[0-9]+]], $zero, -1
+  ; GP64:         xor     $2, $4, $[[T0]]
+  ; GP64:         xor     $3, $5, $[[T0]]
+
+  ; MM32:         not16   $2, $4
+  ; MM32:         not16   $3, $5
+  ; MM32:         not16   $4, $6
+  ; MM32:         not16   $5, $7
+
+  ; MM64:         daddiu  $[[T0:[0-9]+]], $zero, -1
+  ; MM64:         xor     $2, $4, $[[T0]]
+  ; MM64:         xor     $3, $5, $[[T0]]
+
+  %r = xor i128 %a, -1
+  ret i128 %r
+}
+
+define signext i1 @nor_i1(i1 signext %a, i1 signext %b) {
+entry:
+; ALL-LABEL: nor_i1:
+
+  ; ALL:          nor     $2, $5, $4
+
+  %or = or i1 %b, %a
+  %r = xor i1 %or, -1
+  ret i1 %r
+}
+
+define signext i8 @nor_i8(i8 signext %a, i8 signext %b) {
+entry:
+; ALL-LABEL: nor_i8:
+
+  ; ALL:          nor     $2, $5, $4
+
+  %or = or i8 %b, %a
+  %r = xor i8 %or, -1
+  ret i8 %r
+}
+
+define signext i16 @nor_i16(i16 signext %a, i16 signext %b) {
+entry:
+; ALL-LABEL: nor_i16:
+
+  ; ALL:          nor     $2, $5, $4
+
+  %or = or i16 %b, %a
+  %r = xor i16 %or, -1
+  ret i16 %r
+}
+
+define signext i32 @nor_i32(i32 signext %a, i32 signext %b) {
+entry:
+; ALL-LABEL: nor_i32:
+
+  ; GP32:         nor     $2, $5, $4
+
+  ; GP64:         or      $[[T0:[0-9]+]], $5, $4
+  ; GP64:         sll     $[[T1:[0-9]+]], $[[T0]], 0
+  ; GP64:         not     $2, $[[T1]]
+
+  ; MM32:         nor     $2, $5, $4
+
+  ; MM64:         or      $[[T0:[0-9]+]], $5, $4
+  ; MM64:         sll     $[[T1:[0-9]+]], $[[T0]], 0
+  ; MM64:         not16   $2, $[[T1]]
+
+  %or = or i32 %b, %a
+  %r = xor i32 %or, -1
+  ret i32 %r
+}
+
+
+define signext i64 @nor_i64(i64 signext %a, i64 signext %b) {
+entry:
+; ALL-LABEL: nor_i64:
+
+  ; GP32:         nor     $2, $6, $4
+  ; GP32:         nor     $3, $7, $5
+
+  ; GP64:         nor     $2, $5, $4
+
+  ; MM32:         nor     $2, $6, $4
+  ; MM32:         nor     $3, $7, $5
+
+  ; MM64:         nor     $2, $5, $4
+
+  %or = or i64 %b, %a
+  %r = xor i64 %or, -1
+  ret i64 %r
+}
+
+define signext i128 @nor_i128(i128 signext %a, i128 signext %b) {
+entry:
+; ALL-LABEL: nor_i128:
+
+  ; GP32:         lw      $[[T0:[0-9]+]], 24($sp)
+  ; GP32:         lw      $[[T1:[0-9]+]], 20($sp)
+  ; GP32:         lw      $[[T2:[0-9]+]], 16($sp)
+  ; GP32:         nor     $2, $[[T2]], $4
+  ; GP32:         nor     $3, $[[T1]], $5
+  ; GP32:         nor     $4, $[[T0]], $6
+  ; GP32:         lw      $[[T3:[0-9]+]], 28($sp)
+  ; GP32:         nor     $5, $[[T3]], $7
+
+  ; GP64:         nor     $2, $6, $4
+  ; GP64:         nor     $3, $7, $5
+
+  ; MM32:         lw      $[[T0:[0-9]+]], 20($sp)
+  ; MM32:         lw      $[[T1:[0-9]+]], 16($sp)
+  ; MM32:         nor     $2, $[[T1]], $4
+  ; MM32:         nor     $3, $[[T0]], $5
+  ; MM32:         lw      $[[T2:[0-9]+]], 24($sp)
+  ; MM32:         nor     $4, $[[T2]], $6
+  ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
+  ; MM32:         nor     $5, $[[T3]], $7
+
+  ; MM64:         nor     $2, $6, $4
+  ; MM64:         nor     $3, $7, $5
+
+  %or = or i128 %b, %a
+  %r = xor i128 %or, -1
+  ret i128 %r
+}

llvm/trunk/test/CodeGen/Mips/llvm-ir/or.ll

 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MM32
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MM32
+; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MM64
 
 define signext i1 @or_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: or_i1:
 
-  ; ALL:          or     $2, $4, $5
+  ; GP32:         or      $2, $4, $5
+
+  ; GP64:         or      $2, $4, $5
+
+  ; MM:           or16    $[[T0:[0-9]+]], $5
+  ; MM:           move    $2, $[[T0]]
 
   %r = or i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @or_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: or_i8:
 
-  ; ALL:          or     $2, $4, $5
+  ; GP32:         or      $2, $4, $5
+
+  ; GP64:         or      $2, $4, $5
+
+  ; MM:           or16    $[[T0:[0-9]+]], $5
+  ; MM:           move    $2, $[[T0]]
 
   %r = or i8 %a, %b
   ret i8 %r
 }
 
 define signext i16 @or_i16(i16 signext %a, i16 signext %b) {
 entry:
 ; ALL-LABEL: or_i16:
 
-  ; ALL:          or     $2, $4, $5
+  ; GP32:         or      $2, $4, $5
+
+  ; GP64:         or      $2, $4, $5
+
+  ; MM:           or16    $[[T0:[0-9]+]], $5
+  ; MM:           move    $2, $[[T0]]
 
   %r = or i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @or_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: or_i32:
 
-  ; GP32:         or     $2, $4, $5
+  ; GP32:         or      $2, $4, $5
 
-  ; GP64:         or     $[[T0:[0-9]+]], $4, $5
+  ; GP64:         or      $[[T0:[0-9]+]], $4, $5
   ; FIXME: The sll instruction below is redundant.
   ; GP64:         sll     $2, $[[T0]], 0
 
+  ; MM32:         or16    $[[T0:[0-9]+]], $5
+  ; MM32:         move    $2, $[[T0]]
+
+  ; MM64:         or      $[[T0:[0-9]+]], $4, $5
+  ; MM64:         sll     $2, $[[T0]], 0
+
   %r = or i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @or_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: or_i64:
 
-  ; GP32:         or     $2, $4, $6
-  ; GP32:         or     $3, $5, $7
+  ; GP32:         or      $2, $4, $6
+  ; GP32:         or      $3, $5, $7
 
-  ; GP64:         or     $2, $4, $5
+  ; GP64:         or      $2, $4, $5
 
+  ; MM32:         or16    $[[T0:[0-9]+]], $6
+  ; MM32:         or16    $[[T1:[0-9]+]], $7
+  ; MM32:         move    $2, $[[T0]]
+  ; MM32:         move    $3, $[[T1]]
+
+  ; MM64:         or      $2, $4, $5
+
   %r = or i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @or_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: or_i128:
 
-  ; GP32:         lw     $[[T0:[0-9]+]], 24($sp)
-  ; GP32:         lw     $[[T1:[0-9]+]], 20($sp)
-  ; GP32:         lw     $[[T2:[0-9]+]], 16($sp)
-  ; GP32:         or     $2, $4, $[[T2]]
-  ; GP32:         or     $3, $5, $[[T1]]
-  ; GP32:         or     $4, $6, $[[T0]]
-  ; GP32:         lw     $[[T3:[0-9]+]], 28($sp)
-  ; GP32:         or     $5, $7, $[[T3]]
+  ; GP32:         lw      $[[T0:[0-9]+]], 24($sp)
+  ; GP32:         lw      $[[T1:[0-9]+]], 20($sp)
+  ; GP32:         lw      $[[T2:[0-9]+]], 16($sp)
+  ; GP32:         or      $2, $4, $[[T2]]
+  ; GP32:         or      $3, $5, $[[T1]]
+  ; GP32:         or      $4, $6, $[[T0]]
+  ; GP32:         lw      $[[T3:[0-9]+]], 28($sp)
+  ; GP32:         or      $5, $7, $[[T3]]
 
-  ; GP64:         or     $2, $4, $6
-  ; GP64:         or     $3, $5, $7
+  ; GP64:         or      $2, $4, $6
+  ; GP64:         or      $3, $5, $7
 
+  ; MM32:         lw      $[[T0:[0-9]+]], 20($sp)
+  ; MM32:         lw      $[[T1:[0-9]+]], 16($sp)
+  ; MM32:         or16    $[[T1]], $4
+  ; MM32:         or16    $[[T0]], $5
+  ; MM32:         lw      $[[T2:[0-9]+]], 24($sp)
+  ; MM32:         or16    $[[T2]], $6
+  ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
+  ; MM32:         or16    $[[T3]], $7
+
+  ; MM64:         or      $2, $4, $6
+  ; MM64:         or      $3, $5, $7
+
   %r = or i128 %a, %b
   ret i128 %r
 }
+
+define signext i1 @or_i1_4(i1 signext %b) {
+entry:
+; ALL-LABEL: or_i1_4:
+
+  ; ALL:          move    $2, $4
+
+  %r = or i1 4, %b
+  ret i1 %r
+}
+
+define signext i8 @or_i8_4(i8 signext %b) {
+entry:
+; ALL-LABEL: or_i8_4:
+
+  ; ALL:          ori     $2, $4, 4
+
+  %r = or i8 4, %b
+  ret i8 %r
+}
+
+define signext i16 @or_i16_4(i16 signext %b) {
+entry:
+; ALL-LABEL: or_i16_4:
+
+  ; ALL:          ori     $2, $4, 4
+
+  %r = or i16 4, %b
+  ret i16 %r
+}
+
+define signext i32 @or_i32_4(i32 signext %b) {
+entry:
+; ALL-LABEL: or_i32_4:
+
+  ; ALL:          ori     $2, $4, 4
+
+  %r = or i32 4, %b
+  ret i32 %r
+}
+
+define signext i64 @or_i64_4(i64 signext %b) {
+entry:
+; ALL-LABEL: or_i64_4:
+
+  ; GP32:         ori     $3, $5, 4
+  ; GP32:         move    $2, $4
+
+  ; GP64:         ori     $2, $4, 4
+
+  ; MM32:         ori     $3, $5, 4
+  ; MM32:         move    $2, $4
+
+  ; MM64:         ori     $2, $4, 4
+
+  %r = or i64 4, %b
+  ret i64 %r
+}
+
+define signext i128 @or_i128_4(i128 signext %b) {
+entry:
+; ALL-LABEL: or_i128_4:
+
+  ; GP32:         ori     $[[T0:[0-9]+]], $7, 4
+  ; GP32:         move    $2, $4
+  ; GP32:         move    $3, $5
+  ; GP32:         move    $4, $6
+  ; GP32:         move    $5, $[[T0]]
+
+  ; GP64:         ori     $3, $5, 4
+  ; GP64:         move    $2, $4
+
+  ; MM32:         ori     $[[T0:[0-9]+]], $7, 4
+  ; MM32:         move    $2, $4
+  ; MM32:         move    $3, $5
+  ; MM32:         move    $4, $6
+  ; MM32:         move    $5, $[[T0]]
+
+  ; MM64:         ori     $3, $5, 4
+  ; MM64:         move    $2, $4
+
+  %r = or i128 4, %b
+  ret i128 %r
+}
+
+define signext i1 @or_i1_31(i1 signext %b) {
+entry:
+; ALL-LABEL: or_i1_31:
+
+  ; GP32:         addiu   $2, $zero, -1
+
+  ; GP64:         addiu   $2, $zero, -1
+
+  ; MM:           li16    $2, -1
+
+  %r = or i1 31, %b
+  ret i1 %r
+}
+
+define signext i8 @or_i8_31(i8 signext %b) {
+entry:
+; ALL-LABEL: or_i8_31:
+
+  ; ALL:          ori     $2, $4, 31
+
+  %r = or i8 31, %b
+  ret i8 %r
+}
+
+define signext i16 @or_i16_31(i16 signext %b) {
+entry:
+; ALL-LABEL: or_i16_31:
+
+  ; ALL:          ori     $2, $4, 31
+
+  %r = or i16 31, %b
+  ret i16 %r
+}
+
+define signext i32 @or_i32_31(i32 signext %b) {
+entry:
+; ALL-LABEL: or_i32_31:
+
+  ; ALL:          ori     $2, $4, 31
+
+  %r = or i32 31, %b
+  ret i32 %r
+}
+
+define signext i64 @or_i64_31(i64 signext %b) {
+entry:
+; ALL-LABEL: or_i64_31:
+
+  ; GP32:         ori     $3, $5, 31
+  ; GP32:         move    $2, $4
+
+  ; GP64:         ori     $2, $4, 31
+
+  ; MM32:         ori     $3, $5, 31
+  ; MM32:         move    $2, $4
+
+  ; MM64:         ori     $2, $4, 31
+
+  %r = or i64 31, %b
+  ret i64 %r
+}
+
+define signext i128 @or_i128_31(i128 signext %b) {
+entry:
+; ALL-LABEL: or_i128_31:
+
+  ; GP32:         ori     $[[T0:[0-9]+]], $7, 31
+  ; GP32:         move    $2, $4
+  ; GP32:         move    $3, $5
+  ; GP32:         move    $4, $6
+  ; GP32:         move    $5, $[[T0]]
+
+  ; GP64:         ori     $3, $5, 31
+  ; GP64:         move    $2, $4
+
+  ; MM32:         ori     $[[T0:[0-9]+]], $7, 31
+  ; MM32:         move    $2, $4
+  ; MM32:         move    $3, $5
+  ; MM32:         move    $4, $6
+  ; MM32:         move    $5, $[[T0]]
+
+  ; MM64:         ori     $3, $5, 31
+  ; MM64:         move    $2, $4
+
+  %r = or i128 31, %b
+  ret i128 %r
+}
+
+define signext i1 @or_i1_255(i1 signext %b) {
+entry:
+; ALL-LABEL: or_i1_255:
+
+  ; GP32:         addiu   $2, $zero, -1
+
+  ; GP64:         addiu   $2, $zero, -1
+
+  ; MM:           li16    $2, -1
+
+  %r = or i1 255, %b
+  ret i1 %r
+}
+
+define signext i8 @or_i8_255(i8 signext %b) {
+entry:
+; ALL-LABEL: or_i8_255:
+
+  ; GP32:         addiu   $2, $zero, -1
+
+  ; GP64:         addiu   $2, $zero, -1
+
+  ; MM:           li16    $2, -1
+
+  %r = or i8 255, %b
+  ret i8 %r
+}
+
+define signext i16 @or_i16_255(i16 signext %b) {
+entry:
+; ALL-LABEL: or_i16_255:
+
+  ; ALL:          ori     $2, $4, 255
+
+  %r = or i16 255, %b
+  ret i16 %r
+}
+
+define signext i32 @or_i32_255(i32 signext %b) {
+entry:
+; ALL-LABEL: or_i32_255:
+
+  ; ALL:          ori     $2, $4, 255
+
+  %r = or i32 255, %b
+  ret i32 %r
+}
+
+define signext i64 @or_i64_255(i64 signext %b) {
+entry:
+; ALL-LABEL: or_i64_255:
+
+  ; GP32:         ori     $3, $5, 255
+  ; GP32:         move    $2, $4
+
+  ; GP64:         ori     $2, $4, 255
+
+  ; MM32:         ori     $3, $5, 255
+  ; MM32:         move    $2, $4
+
+  ; MM64:         ori     $2, $4, 255
+
+  %r = or i64 255, %b
+  ret i64 %r
+}
+
+define signext i128 @or_i128_255(i128 signext %b) {
+entry:
+; ALL-LABEL: or_i128_255:
+
+  ; GP32:         ori     $[[T0:[0-9]+]], $7, 255
+  ; GP32:         move    $2, $4
+  ; GP32:         move    $3, $5
+  ; GP32:         move    $4, $6
+  ; GP32:         move    $5, $[[T0]]
+
+  ; GP64:         ori     $3, $5, 255
+  ; GP64:         move    $2, $4
+
+  ; MM32:         ori     $[[T0:[0-9]+]], $7, 255
+  ; MM32:         move    $2, $4
+  ; MM32:         move    $3, $5
+  ; MM32:         move    $4, $6
+  ; MM32:         move    $5, $[[T0]]
+
+  ; MM64:         ori     $3, $5, 255
+  ; MM64:         move    $2, $4
+
+  %r = or i128 255, %b
+  ret i128 %r
+}
+
+define signext i1 @or_i1_32768(i1 signext %b) {
+entry:
+; ALL-LABEL: or_i1_32768:
+
+  ; ALL:          move    $2, $4
+
+  %r = or i1 32768, %b
+  ret i1 %r
+}
+
+define signext i8 @or_i8_32768(i8 signext %b) {
+entry:
+; ALL-LABEL: or_i8_32768:
+
+  ; ALL:          move    $2, $4
+
+  %r = or i8 32768, %b
+  ret i8 %r
+}
+
+define signext i16 @or_i16_32768(i16 signext %b) {
+entry:
+; ALL-LABEL: or_i16_32768:
+
+  ; GP32:         addiu   $[[T0:[0-9]+]], $zero, -32768
+  ; GP32:         or      $2, $4, $[[T0]]
+
+  ; GP64:         addiu   $[[T0:[0-9]+]], $zero, -32768
+  ; GP64:         or      $2, $4, $[[T0]]
+
+  ; MM:           addiu   $2, $zero, -32768
+  ; MM:           or16    $2, $4
+
+  %r = or i16 32768, %b
+  ret i16 %r
+}
+
+define signext i32 @or_i32_32768(i32 signext %b) {
+entry:
+; ALL-LABEL: or_i32_32768:
+
+  ; ALL:          ori     $2, $4, 32768
+
+  %r = or i32 32768, %b
+  ret i32 %r
+}
+
+define signext i64 @or_i64_32768(i64 signext %b) {
+entry:
+; ALL-LABEL: or_i64_32768:
+
+  ; GP32:         ori     $3, $5, 32768
+  ; GP32:         move    $2, $4
+
+  ; GP64:         ori     $2, $4, 32768
+
+  ; MM32:         ori     $3, $5, 32768
+  ; MM32:         move    $2, $4
+
+  ; MM64:         ori     $2, $4, 32768
+
+  %r = or i64 32768, %b
+  ret i64 %r
+}
+
+define signext i128 @or_i128_32768(i128 signext %b) {
+entry:
+; ALL-LABEL: or_i128_32768:
+
+  ; GP32:         ori     $[[T0:[0-9]+]], $7, 32768
+  ; GP32:         move    $2, $4
+  ; GP32:         move    $3, $5
+  ; GP32:         move    $4, $6
+  ; GP32:         move    $5, $[[T0]]
+
+  ; GP64:         ori     $3, $5, 32768
+  ; GP64:         move    $2, $4
+
+  ; MM32:         ori     $[[T0:[0-9]+]], $7, 32768
+  ; MM32:         move    $2, $4
+  ; MM32:         move    $3, $5
+  ; MM32:         move    $4, $6
+  ; MM32:         move    $5, $[[T0]]
+
+  ; MM64:         ori     $3, $5, 32768
+  ; MM64:         move    $2, $4
+
+  %r = or i128 32768, %b
+  ret i128 %r
+}
+
+define signext i1 @or_i1_65(i1 signext %b) {
+entry:
+; ALL-LABEL: or_i1_65:
+
+  ; GP32:         addiu   $2, $zero, -1
+
+  ; GP64:         addiu   $2, $zero, -1
+
+  ; MM:           li16    $2, -1
+
+  %r = or i1 65, %b
+  ret i1 %r
+}
+
+define signext i8 @or_i8_65(i8 signext %b) {
+entry:
+; ALL-LABEL: or_i8_65:
+
+  ; ALL:          ori     $2, $4, 65
+
+  %r = or i8 65, %b
+  ret i8 %r
+}
+
+define signext i16 @or_i16_65(i16 signext %b) {
+entry:
+; ALL-LABEL: or_i16_65:
+
+  ; ALL:          ori     $2, $4, 65
+
+  %r = or i16 65, %b
+  ret i16 %r
+}
+
+define signext i32 @or_i32_65(i32 signext %b) {
+entry:
+; ALL-LABEL: or_i32_65:
+
+  ; ALL:          ori     $2, $4, 65
+
+  %r = or i32 65, %b
+  ret i32 %r
+}
+
+define signext i64 @or_i64_65(i64 signext %b) {
+entry:
+; ALL-LABEL: or_i64_65:
+
+  ; GP32:         ori     $3, $5, 65
+  ; GP32:         move    $2, $4
+
+  ; GP64:         ori     $2, $4, 65
+
+  ; MM32:         ori     $3, $5, 65
+  ; MM32:         move    $2, $4
+
+  ; MM64:         ori     $2, $4, 65
+
+  %r = or i64 65, %b
+  ret i64 %r
+}
+
+define signext i128 @or_i128_65(i128 signext %b) {
+entry:
+; ALL-LABEL: or_i128_65:
+
+  ; GP32:         ori     $[[T0:[0-9]+]], $7, 65
+  ; GP32:         move    $2, $4
+  ; GP32:         move    $3, $5
+  ; GP32:         move    $4, $6
+  ; GP32:         move    $5, $[[T0]]
+
+  ; GP64:         ori     $3, $5, 65
+  ; GP64:         move    $2, $4
+
+  ; MM32:         ori     $[[T0:[0-9]+]], $7, 65
+  ; MM32:         move    $2, $4
+  ; MM32:         move    $3, $5
+  ; MM32:         move    $4, $6
+  ; MM32:         move    $5, $[[T0]]
+
+  ; MM64:         ori     $3, $5, 65
+  ; MM64:         move    $2, $4
+
+  %r = or i128 65, %b
+  ret i128 %r
+}
+
+define signext i1 @or_i1_256(i1 signext %b) {
+entry:
+; ALL-LABEL: or_i1_256:
+
+  ; ALL:          move    $2, $4
+
+  %r = or i1 256, %b
+  ret i1 %r
+}
+
+define signext i8 @or_i8_256(i8 signext %b) {
+entry:
+; ALL-LABEL: or_i8_256:
+
+  ; ALL:          move    $2, $4
+
+  %r = or i8 256, %b
+  ret i8 %r
+}
+
+define signext i16 @or_i16_256(i16 signext %b) {
+entry:
+; ALL-LABEL: or_i16_256:
+
+  ; ALL:          ori     $2, $4, 256
+
+  %r = or i16 256, %b
+  ret i16 %r
+}
+
+define signext i32 @or_i32_256(i32 signext %b) {
+entry:
+; ALL-LABEL: or_i32_256:
+
+  ; ALL:          ori     $2, $4, 256
+
+  %r = or i32 256, %b
+  ret i32 %r
+}
+
+define signext i64 @or_i64_256(i64 signext %b) {
+entry:
+; ALL-LABEL: or_i64_256:
+
+  ; GP32:         ori     $3, $5, 256
+  ; GP32:         move    $2, $4
+
+  ; GP64:         ori     $2, $4, 256
+
+  ; MM32:         ori     $3, $5, 256
+  ; MM32:         move    $2, $4
+
+  ; MM64:         ori     $2, $4, 256
+
+  %r = or i64 256, %b
+  ret i64 %r
+}
+
+define signext i128 @or_i128_256(i128 signext %b) {
+entry:
+; ALL-LABEL: or_i128_256:
+
+  ; GP32:         ori     $[[T0:[0-9]+]], $7, 256
+  ; GP32:         move    $2, $4
+  ; GP32:         move    $3, $5
+  ; GP32:         move    $4, $6
+  ; GP32:         move    $5, $[[T0]]
+
+  ; GP64:         ori     $3, $5, 256
+  ; GP64:         move    $2, $4
+
+  ; MM32:         ori     $[[T0:[0-9]+]], $7, 256
+  ; MM32:         move    $2, $4
+  ; MM32:         move    $3, $5
+  ; MM32:         move    $4, $6
+  ; MM32:         move    $5, $[[T0]]
+
+  ; MM64:         ori     $3, $5, 256
+  ; MM64:         move    $2, $4
+
+  %r = or i128 256, %b
+  ret i128 %r
+}

llvm/trunk/test/CodeGen/Mips/llvm-ir/select-dbl.ll

entry:
   ; M2-M3:      mov.d     $f0, $f12
 
   ; CMOV-32:    c.ueq.d   $f12, $f14
   ; CMOV-32:    movf.d    $f14, $f12, $fcc0
   ; CMOV-32:    mov.d     $f0, $f14
 
   ; SEL-32:     cmp.ueq.d $f0, $f12, $f14
   ; SEL-32:     mfc1      $[[T0:[0-9]+]], $f0
-  ; 32R6:       not       $[[T0]], $[[T0]]
-  ; MM32R6:     nor       $[[T0]], $[[T0]], $zero
+  ; SEL-32:     not       $[[T0]], $[[T0]]
   ; SEL-32:     mtc1      $[[T0:[0-9]+]], $f0
   ; SEL-32:     sel.d     $f0, $f14, $f12
 
   ; CMOV-64:    c.ueq.d   $f12, $f13
   ; CMOV-64:    movf.d    $f13, $f12, $fcc0
   ; CMOV-64:    mov.d     $f0, $f13
 
   ; SEL-64:     cmp.ueq.d $f0, $f12, $f13

llvm/trunk/test/CodeGen/Mips/llvm-ir/select-flt.ll

entry:
   ; M2-M3:      mov.s     $f0, $f12
 
   ; CMOV-32:    c.ueq.s   $f12, $f14
   ; CMOV-32:    movf.s    $f14, $f12, $fcc0
   ; CMOV-32:    mov.s     $f0, $f14
 
   ; SEL-32:     cmp.ueq.s $f0, $f12, $f14
   ; SEL-32:     mfc1      $[[T0:[0-9]+]], $f0
-  ; 32R6:       not       $[[T0]], $[[T0]]
-  ; MM32R6:     nor       $[[T0]], $[[T0]], $zero
+  ; SEL-32:     not       $[[T0]], $[[T0]]
   ; SEL-32:     mtc1      $[[T0:[0-9]+]], $f0
   ; SEL-32:     sel.s     $f0, $f14, $f12
 
   ; CMOV-64:    c.ueq.s   $f12, $f13
   ; CMOV-64:    movf.s    $f13, $f12, $fcc0
   ; CMOV-64:    mov.s     $f0, $f13
 
   ; SEL-64:     cmp.ueq.s $f0, $f12, $f13

llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll

; ALL-LABEL: shl_i64:
   ; MMR3:       or16      $[[T4:[0-9]+]], $[[T0]]
   ; MMR3:       sllv      $[[T5:[0-9]+]], $5, $7
   ; MMR3:       andi16    $[[T6:[0-9]+]], $7, 32
   ; MMR3:       movn      $[[T7:[0-9]+]], $[[T5]], $[[T6]]
   ; MMR3:       lui       $[[T8:[0-9]+]], 0
   ; MMR3:       movn      $3, $[[T8]], $[[T6]]
 
   ; MMR6:       sllv      $[[T0:[0-9]+]], $4, $7
-  ; MMR6:       not       $[[T1:[0-9]+]], $7
-  ; MMR6:       srl16     $[[T2:[0-9]+]], $5, 1
-  ; MMR6:       srlv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+  ; MMR6:       srl16     $[[T1:[0-9]+]], $5, 1
+  ; MMR6:       not16     $[[T2:[0-9]+]], $7
+  ; MMR6:       srlv      $[[T3:[0-9]+]], $[[T1]], $[[T2]]
   ; MMR6:       or16      $[[T4:[0-9]+]], $[[T0]]
   ; MMR6:       andi16    $[[T5:[0-9]+]], $7, 32
   ; MMR6:       seleqz    $[[T6:[0-9]+]], $[[T4]], $[[T5]]
   ; MMR6:       sllv      $[[T7:[0-9]+]], $5, $7
   ; MMR6:       selnez    $[[T8:[0-9]+]], $[[T7]], $[[T5]]
   ; MMR6:       or        $2, $[[T8]], $[[T6]]
   ; MMR6:       seleqz    $3, $[[T7]], $[[T5]]
 

llvm/trunk/test/CodeGen/Mips/llvm-ir/xor.ll

 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MM32
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MM32
+; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MM64
 
 define signext i1 @xor_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: xor_i1:
 
-  ; ALL:          xor     $2, $4, $5
+  ; GP32:         xor     $2, $4, $5
+
+  ; GP64:         xor     $2, $4, $5
+
+  ; MM:           xor16   $[[T0:[0-9]+]], $5
+  ; MM:           move    $2, $[[T0]]
 
   %r = xor i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @xor_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: xor_i8:
 
-  ; ALL:          xor     $2, $4, $5
+  ; GP32:         xor     $2, $4, $5
+
+  ; GP64:         xor     $2, $4, $5
+
+  ; MM:           xor16   $[[T0:[0-9]+]], $5
+  ; MM:           move    $2, $[[T0]]
 
   %r = xor i8 %a, %b
   ret i8 %r
 }
 
 define signext i16 @xor_i16(i16 signext %a, i16 signext %b) {
 entry:
 ; ALL-LABEL: xor_i16:
 
-  ; ALL:          xor     $2, $4, $5
+  ; GP32:         xor     $2, $4, $5
+
+  ; GP64:         xor     $2, $4, $5
+
+  ; MM:           xor16   $[[T0:[0-9]+]], $5
+  ; MM:           move    $2, $[[T0]]
 
   %r = xor i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @xor_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: xor_i32:
 
   ; GP32:         xor     $2, $4, $5
 
   ; GP64:         xor     $[[T0:[0-9]+]], $4, $5
   ; GP64:         sll     $2, $[[T0]], 0
 
+  ; MM32:         xor16   $[[T0:[0-9]+]], $5
+  ; MM32:         move    $2, $[[T0]]
+
+  ; MM64:         xor     $[[T0:[0-9]+]], $4, $5
+  ; MM64:         sll     $2, $[[T0]], 0
+
   %r = xor i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @xor_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: xor_i64:
 
   ; GP32:         xor     $2, $4, $6
   ; GP32:         xor     $3, $5, $7
 
   ; GP64:         xor     $2, $4, $5
 
+  ; MM32:         xor16   $[[T0:[0-9]+]], $6
+  ; MM32:         xor16   $[[T1:[0-9]+]], $7
+  ; MM32:         move    $2, $[[T0]]
+  ; MM32:         move    $3, $[[T1]]
+
+  ; MM64:         xor     $2, $4, $5
+
   %r = xor i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @xor_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: xor_i128:
 
   ; GP32:         lw      $[[T0:[0-9]+]], 24($sp)
   ; GP32:         lw      $[[T1:[0-9]+]], 20($sp)
   ; GP32:         lw      $[[T2:[0-9]+]], 16($sp)
   ; GP32:         xor     $2, $4, $[[T2]]
   ; GP32:         xor     $3, $5, $[[T1]]
   ; GP32:         xor     $4, $6, $[[T0]]
   ; GP32:         lw      $[[T3:[0-9]+]], 28($sp)
   ; GP32:         xor     $5, $7, $[[T3]]
 
   ; GP64:         xor     $2, $4, $6
   ; GP64:         xor     $3, $5, $7
 
+  ; MM32:         lw      $[[T0:[0-9]+]], 20($sp)
+  ; MM32:         lw      $[[T1:[0-9]+]], 16($sp)
+  ; MM32:         xor16   $[[T1]], $4
+  ; MM32:         xor16   $[[T0]], $5
+  ; MM32:         lw      $[[T2:[0-9]+]], 24($sp)
+  ; MM32:         xor16   $[[T2]], $6
+  ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
+  ; MM32:         xor16   $[[T3]], $7
+
+  ; MM64:         xor     $2, $4, $6
+  ; MM64:         xor     $3, $5, $7
+
   %r = xor i128 %a, %b
   ret i128 %r
 }
+
+define signext i1 @xor_i1_4(i1 signext %b) {
+entry:
+; ALL-LABEL: xor_i1_4:
+
+  ; ALL:          move    $2, $4
+
+  %r = xor i1 4, %b
+  ret i1 %r
+}
+
+define signext i8 @xor_i8_4(i8 signext %b) {
+entry:
+; ALL-LABEL: xor_i8_4:
+
+  ; ALL:          xori    $2, $4, 4
+
+  %r = xor i8 4, %b
+  ret i8 %r
+}
+
+define signext i16 @xor_i16_4(i16 signext %b) {
+entry:
+; ALL-LABEL: xor_i16_4:
+
+  ; ALL:          xori    $2, $4, 4
+
+  %r = xor i16 4, %b
+  ret i16 %r
+}
+
+define signext i32 @xor_i32_4(i32 signext %b) {
+entry:
+; ALL-LABEL: xor_i32_4:
+
+  ; ALL:          xori    $2, $4, 4
+
+  %r = xor i32 4, %b
+  ret i32 %r
+}
+
+define signext i64 @xor_i64_4(i64 signext %b) {
+entry:
+; ALL-LABEL: xor_i64_4:
+
+  ; GP32:         xori    $3, $5, 4
+  ; GP32:         move    $2, $4
+
+  ; GP64:         xori    $2, $4, 4
+
+  ; MM32:         xori    $3, $5, 4
+  ; MM32:         move    $2, $4
+
+  ; MM64:         xori    $2, $4, 4
+
+  %r = xor i64 4, %b
+  ret i64 %r
+}
+
+define signext i128 @xor_i128_4(i128 signext %b) {
+entry:
+; ALL-LABEL: xor_i128_4:
+
+  ; GP32:         xori    $[[T0:[0-9]+]], $7, 4
+  ; GP32:         move    $2, $4
+  ; GP32:         move    $3, $5
+  ; GP32:         move    $4, $6
+  ; GP32:         move    $5, $[[T0]]
+
+  ; GP64:         xori    $3, $5, 4
+  ; GP64:         move    $2, $4
+
+  ; MM32:         xori    $[[T0:[0-9]+]], $7, 4
+  ; MM32:         move    $2, $4
+  ; MM32:         move    $3, $5
+  ; MM32:         move    $4, $6
+  ; MM32:         move    $5, $[[T0]]
+
+  ; MM64:         xori    $3, $5, 4
+  ; MM64:         move    $2, $4
+
+  %r = xor i128 4, %b
+  ret i128 %r
+}

llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt

 0xa3 0x00 0x50 0x1b # CHECK: slt $3, $3, $5
 0x63 0x90 0x67 0x00 # CHECK: slti $3, $3, 103
 0x63 0x90 0x67 0x00 # CHECK: slti $3, $3, 103
 0x63 0xb0 0x67 0x00 # CHECK: sltiu $3, $3, 103
 0xa3 0x00 0x90 0x1b # CHECK: sltu $3, $3, $5
 0xa9 0x41 0x67 0x45 # CHECK: lui $9, 17767
 0xe6 0x00 0x50 0x4a # CHECK: and $9, $6, $7
 0x26 0xd1 0x67 0x45 # CHECK: andi $9, $6, 17767
-0x26 0xd1 0x67 0x45 # CHECK: andi $9, $6, 17767
 0xa4 0x00 0x90 0x1a # CHECK: or $3, $4, $5
 0x26 0x51 0x67 0x45 # CHECK: ori $9, $6, 17767
 0xa3 0x00 0x10 0x1b # CHECK: xor $3, $3, $5
 0x26 0x71 0x67 0x45 # CHECK: xori $9, $6, 17767
-0x26 0x71 0x67 0x45 # CHECK: xori $9, $6, 17767
 0xe6 0x00 0xd0 0x4a # CHECK: nor $9, $6, $7
 0x08 0x00 0xd0 0x3a # CHECK: not $7, $8
 0xe6 0x00 0x10 0x4a # CHECK: mul $9, $6, $7
 0xe9 0x00 0x3c 0x8b # CHECK: mult $9, $7
 0xe9 0x00 0x3c 0x9b # CHECK: multu $9, $7
 0xe9 0x00 0x3c 0xab # CHECK: div $zero, $9, $7
 0xe9 0x00 0x3c 0xbb # CHECK: divu $zero, $9, $7
 0x83 0x00 0x00 0x38 # CHECK: sll $4, $3, 7

llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt

 0x00 0xa3 0x1b 0x50 # CHECK: slt $3, $3, $5
 0x90 0x63 0x00 0x67 # CHECK: slti $3, $3, 103
 0x90 0x63 0x00 0x67 # CHECK: slti $3, $3, 103
 0xb0 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103
 0x00 0xa3 0x1b 0x90 # CHECK: sltu $3, $3, $5
 0x41 0xa9 0x45 0x67 # CHECK: lui $9, 17767
 0x00 0xe6 0x4a 0x50 # CHECK: and $9, $6, $7
 0xd1 0x26 0x45 0x67 # CHECK: andi $9, $6, 17767
-0xd1 0x26 0x45 0x67 # CHECK: andi $9, $6, 17767
 0x00 0xa4 0x1a 0x90 # CHECK: or $3, $4, $5
 0x51 0x26 0x45 0x67 # CHECK: ori $9, $6, 17767
 0x00 0xa3 0x1b 0x10 # CHECK: xor $3, $3, $5
 0x71 0x26 0x45 0x67 # CHECK: xori $9, $6, 17767
-0x71 0x26 0x45 0x67 # CHECK: xori $9, $6, 17767
 0x00 0xe6 0x4a 0xd0 # CHECK: nor $9, $6, $7
 0x00 0x08 0x3a 0xd0 # CHECK: not $7, $8
 0x00 0xe6 0x4a 0x10 # CHECK: mul $9, $6, $7
 0x00 0xe9 0x8b 0x3c # CHECK: mult $9, $7
 0x00 0xe9 0x9b 0x3c # CHECK: multu $9, $7
 0x00 0xe9 0xab 0x3c # CHECK: div $zero, $9, $7
 0x00 0xe9 0xbb 0x3c # CHECK: divu $zero, $9, $7
 0x00 0x83 0x38 0x00 # CHECK: sll $4, $3, 7

llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt

 0x01 0x07 0xfc 0x3c # CHECK: tne $7, $8, 15
 0x65 0x88 # CHECK: lw $3, 32($gp)
 0x48 0x66 # CHECK: lw $3, 24($sp)
 0x6a 0x12 # CHECK: lw16 $4, 8($17)
 0x29 0x82 # CHECK: lhu16 $3, 4($16)
 0x09 0x94 # CHECK: lbu16 $3, 4($17)
 0x09 0x9f # CHECK: lbu16 $3, -1($17)
 0x04 0xcc # CHECK: addu16 $6, $17, $4
-0x44 0x21 # CHECK: and16 $16, $2
-0x2e 0x56 # CHECK: andi16 $4, $5, 8
-0x46 0x70 # CHECK: not16 $4, $7
-0x45 0xf9 # CHECK: or16 $3, $7
 0x25 0xe0 # CHECK: sll16 $3, $6, 8
 0x25 0xe1 # CHECK: srl16 $3, $6, 8
 0x46 0x1B # CHECK: break16 8
 0xed 0xff # CHECK: li16 $3, -1
 0x0c 0x65 # CHECK: move16 $3, $5
 0x46 0x3b # CHECK: sdbbp16 8
 0x04 0x3b # CHECK: subu16 $5, $16, $3
 0x44 0xd8 # CHECK: xor16 $17, $5

 0x41 0x5f 0x00 0x04 # CHECK: bc2eqzc $31, 8
 0x41 0x7f 0x00 0x04 # CHECK: bc2nezc $31, 8
 0x01 0x26 0x30 0xec # CHECK: ext $9, $6, 3, 7
 0x01 0x26 0x48 0xcc # CHECK: ins $9, $6, 3, 7
 0x00 0x85 0x0f 0x3c # CHECK: jalrc $4, $5
 0x03 0xe5 0x0f 0x3c # CHECK: jalrc $5
 0x74 0x44 0x00 0x0c # CHECK: bovc $2, $4, 24
 0x7c 0x44 0x00 0x0c # CHECK: bnvc $2, $4, 24
+0xd0 0x64 0x00 0x05 # CHECK: andi $3, $4, 5
+0x50 0x64 0x00 0x05 # CHECK: ori $3, $4, 5
+0x70 0x64 0x00 0x05 # CHECK: xori $3, $4, 5
+0x00 0x04 0x1a 0xd0 # CHECK: not $3, $4

llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt

 # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips64r6 -mattr=micromips | FileCheck %s
 
 0x6f 0x83 # CHECK: addiur1sp $7, 4
 0x6f 0x7e # CHECK: addiur2 $6, $7, -1
 0x6f 0x76 # CHECK: addiur2 $6, $7, 12
 0x4c 0xfc # CHECK: addius5 $7, -2
 0x4f 0xff # CHECK: addiusp -1028
 0x4f 0xfd # CHECK: addiusp -1032
 0x4c 0x01 # CHECK: addiusp 1024
 0x4c 0x03 # CHECK: addiusp 1028
 0x4f 0xf9 # CHECK: addiusp -16
+0x44 0x21 # CHECK: and16 $16, $2
+0x2e 0x56 # CHECK: andi16 $4, $5, 8
 0xcc 0x42 # CHECK: bc16 132
 0x8f 0x0a # CHECK: beqzc16 $6, 20
 0xaf 0x0a # CHECK: bnezc16 $6, 20
 0x65 0x88 # CHECK: lw $3, 32($gp)
 0x48 0x66 # CHECK: lw $3, 24($sp)
 0x6a 0x12 # CHECK: lw16 $4, 8($17)
 0x29 0x82 # CHECK: lhu16 $3, 4($16)
 0x09 0x94 # CHECK: lbu16 $3, 4($17)
 0x09 0x9f # CHECK: lbu16 $3, -1($17)
 0x45 0x2b # CHECK: jalr $9
 0x45 0x23 # CHECK: jrc16 $9
 0x44 0xb3 # CHECK: jrcaddiusp 20
 0x84 0x34 # CHECK: movep $5, $6, $2, $3
+0x45 0xf9 # CHECK: or16 $3, $7
 0x60 0x44 0x30 0x08 # CHECK: ll $2, 8($4)
 0x20 0x44 0x50 0x08 # CHECK: lwm32 $16, $17, 8($4)
 0x21 0x3b 0x59 0x84 # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, -1660($27)
 0x01 0x26 0x38 0xc0 # CHECK: rotr $9, $6, 7
 0x00 0xc7 0x48 0xd0 # CHECK: rotrv $9, $6, $7
 0x60 0x44 0xb0 0x08 # CHECK: sc $2, 8($4)
 0x20 0x44 0xd0 0x08 # CHECK: swm32 $16, $17, 8($4)
 0x00 0x00 0x8b 0x7c # CHECK: syscall

 0x58 0x64 0x28 0x08 # CHECK: dsll32 $3, $4, 5
 0x58 0xa6 0x20 0x10 # CHECK: dsllv $4, $5, $6
 0x58 0x85 0x28 0x80 # CHECK: dsra $4, $5, 5
 0x58 0xa6 0x20 0x90 # CHECK: dsrav $4, $5, $6
 0x41 0x1f 0x00 0x02 # CHECK: bc1eqzc $f31, 4
 0x41 0x3f 0x00 0x02 # CHECK: bc1nezc $f31, 4
 0x41 0x5f 0x00 0x04 # CHECK: bc2eqzc $31, 8
 0x41 0x7f 0x00 0x04 # CHECK: bc2nezc $31, 8
+0x00 0xa4 0x1a 0x50 # CHECK: and $3, $4, $5
+0xd0 0x64 0x04 0xd2 # CHECK: andi $3, $4, 1234
+0x00 0xa4 0x1a 0x90 # CHECK: or $3, $4, $5
+0x50 0x64 0x04 0xd2 # CHECK: ori $3, $4, 1234
+0x00 0xa4 0x1b 0x10 # CHECK: xor $3, $4, $5
+0x70 0x64 0x04 0xd2 # CHECK: xori $3, $4, 1234
+0x00 0xa4 0x1a 0xd0 # CHECK: nor $3, $4, $5
+0x00 0x04 0x1a 0xd0 # CHECK: not $3, $4

llvm/trunk/test/MC/Mips/micromips-alu-instructions.s

 # CHECK-EL: mul    $9, $6, $7     # encoding: [0xe6,0x00,0x10,0x4a]
 # CHECK-EL: mult   $9, $7         # encoding: [0xe9,0x00,0x3c,0x8b]
 # CHECK-EL: multu  $9, $7         # encoding: [0xe9,0x00,0x3c,0x9b]
 # CHECK-EL: div    $zero, $9, $7  # encoding: [0xe9,0x00,0x3c,0xab]
 # CHECK-EL: divu   $zero, $9, $7  # encoding: [0xe9,0x00,0x3c,0xbb]
 # CHECK-EL: addiupc $2, 20        # encoding: [0x00,0x79,0x05,0x00]
 # CHECK-EL: addiupc $7, 16777212  # encoding: [0xbf,0x7b,0xff,0xff]
 # CHECK-EL: addiupc $7, -16777216 # encoding: [0xc0,0x7b,0x00,0x00]
+# CHECK-EL: andi $3, $3, 5        # encoding: [0x63,0xd0,0x05,0x00]
+# CHECK-EL: ori $3, $4, 5         # encoding: [0x64,0x50,0x05,0x00]
+# CHECK-EL: ori $3, $3, 5         # encoding: [0x63,0x50,0x05,0x00]
+# CHECK-EL: xori $3, $3, 5        # encoding: [0x63,0x70,0x05,0x00]
+# CHECK-EL: not $3, $4            # encoding: [0x04,0x00,0xd0,0x1a]
+
 #------------------------------------------------------------------------------
 # Big endian
 #------------------------------------------------------------------------------
 # CHECK-EB: add $9, $6, $7        # encoding: [0x00,0xe6,0x49,0x10]
 # CHECK-EB: addi  $9, $6, 17767   # encoding: [0x11,0x26,0x45,0x67]
 # CHECK-EB: addiu $9, $6, -15001  # encoding: [0x31,0x26,0xc5,0x67]
 # CHECK-EB: addi  $9, $6, 17767   # encoding: [0x11,0x26,0x45,0x67]
 # CHECK-EB: addiu $9, $6, -15001  # encoding: [0x31,0x26,0xc5,0x67]

 # CHECK-EB:  mul $9, $6, $7       # encoding: [0x00,0xe6,0x4a,0x10]
 # CHECK-EB:  mult  $9, $7         # encoding: [0x00,0xe9,0x8b,0x3c]
 # CHECK-EB:  multu $9, $7         # encoding: [0x00,0xe9,0x9b,0x3c]
 # CHECK-EB: div  $zero, $9, $7    # encoding: [0x00,0xe9,0xab,0x3c]
 # CHECK-EB: divu $zero, $9, $7    # encoding: [0x00,0xe9,0xbb,0x3c]
 # CHECK-EB: addiupc $2, 20        # encoding: [0x79,0x00,0x00,0x05]
 # CHECK-EB: addiupc $7, 16777212  # encoding: [0x7b,0xbf,0xff,0xff]
 # CHECK-EB: addiupc $7, -16777216 # encoding: [0x7b,0xc0,0x00,0x00]
+# CHECK-EB: andi $3, $3, 5        # encoding: [0xd0,0x63,0x00,0x05]
+# CHECK-EB: ori $3, $4, 5         # encoding: [0x50,0x64,0x00,0x05]
+# CHECK-EB: ori $3, $3, 5         # encoding: [0x50,0x63,0x00,0x05]
+# CHECK-EB: xori $3, $3, 5        # encoding: [0x70,0x63,0x00,0x05]
+# CHECK-EB: not $3, $4            # encoding: [0x00,0x04,0x1a,0xd0]
+
     add    $9, $6, $7
     add    $9, $6, 17767
     addu   $9, $6, -15001
     addi   $9, $6, 17767
     addiu  $9, $6,-15001
     addu   $9, $6, $7
     sub    $9, $6, $7
     subu   $4, $3, $5
# CHECK-EB: not $3, $4            # encoding: [0x00,0x04,0x1a,0xd0]
     mul    $9, $6, $7
     mult   $9, $7
     multu  $9, $7
     div    $0, $9, $7
     divu   $0, $9, $7
     addiupc $2, 20
     addiupc $7, 16777212
     addiupc $7, -16777216
+    and    $3, 5
+    or     $3, $4, 5
+    or     $3, 5
+    xor    $3, 5
+    not    $3, $4

llvm/trunk/test/MC/Mips/micromips/invalid.s

# RUN: FileCheck %s < %t1
   lwp $31, 8($4)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
                       # FIXME: This ought to point at the $34 but memory is treated as one operand.
   lwp $16, 8($34)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
   lwp $16, 4096($4)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
   lwp $16, 8($16)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
   swp $31, 8($4)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swp $16, 8($34)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
   swp $16, 4096($4)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
+  andi $3, $4, -1     # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate
+  andi $3, $4, 65536  # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate
+  andi $3, -1         # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
+  andi $3, 65536      # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
+  ori $3, $4, -1      # CHECK: :[[@LINE]]:15: error: expected 16-bit unsigned immediate
+  ori $3, $4, 65536   # CHECK: :[[@LINE]]:15: error: expected 16-bit unsigned immediate
+  ori $3, -1          # CHECK: :[[@LINE]]:11: error: expected 16-bit unsigned immediate
+  ori $3, 65536       # CHECK: :[[@LINE]]:11: error: expected 16-bit unsigned immediate
+  xori $3, $4, -1     # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate
+  xori $3, $4, 65536  # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate
+  xori $3, -1         # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
+  xori $3, 65536      # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
+  not $3, 4           # CHECK: :[[@LINE]]:11: error: invalid operand for instruction

llvm/trunk/test/MC/Mips/micromips32r6/invalid.s

# RUN: FileCheck %s < %t1
   bc2eqzc $31, 65536       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
   bc2nezc $32, 4           # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
   bc2nezc $31, -65535      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
   bc2nezc $31, -65537      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
   bc2nezc $31, 65535       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
   bc2nezc $31, 65536       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
   jalrc $31                # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
   jalrc $31, $31           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
+  andi $3, $4, -1          # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate
+  andi $3, $4, 65536       # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate
+  andi $3, -1              # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
+  andi $3, 65536           # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
+  ori $3, $4, -1           # CHECK: :[[@LINE]]:15: error: expected 16-bit unsigned immediate
+  ori $3, $4, 65536        # CHECK: :[[@LINE]]:15: error: expected 16-bit unsigned immediate
+  ori $3, -1               # CHECK: :[[@LINE]]:11: error: expected 16-bit unsigned immediate
+  ori $3, 65536            # CHECK: :[[@LINE]]:11: error: expected 16-bit unsigned immediate
+  xori $3, $4, -1          # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate
+  xori $3, $4, 65536       # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate
+  xori $3, -1              # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
+  xori $3, 65536           # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
+  not $3, 4                # CHECK: :[[@LINE]]:11: error: invalid operand for instruction

llvm/trunk/test/MC/Mips/micromips32r6/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
   ins $9, $6, 3, 7         # CHECK: ins $9, $6, 3, 7       # encoding: [0x01,0x26,0x48,0xcc]
   jalrc $4, $5             # CHECK: jalrc $4, $5           # encoding: [0x00,0x85,0x0f,0x3c]
   jalrc $5                 # CHECK: jalrc $5               # encoding: [0x03,0xe5,0x0f,0x3c]
   ext $9, $6, 3, 7         # CHECK: ext $9, $6, 3, 7       # encoding: [0x01,0x26,0x30,0xec]
   bovc $2, $4, 24          # CHECK: bovc $2, $4, 24        # encoding: [0x74,0x44,0x00,0x0c]
   bovc $4, $2, 24          # CHECK: bovc $4, $2, 24        # encoding: [0x74,0x44,0x00,0x0c]
   bnvc $2, $4, 24          # CHECK: bnvc $2, $4, 24        # encoding: [0x7c,0x44,0x00,0x0c]
   bnvc $4, $2, 24          # CHECK: bnvc $4, $2, 24        # encoding: [0x7c,0x44,0x00,0x0c]
+  and $3, 5                # CHECK: andi $3, $3, 5         # encoding: [0xd0,0x63,0x00,0x05]
+  and $3, $4, 5            # CHECK: andi $3, $4, 5         # encoding: [0xd0,0x64,0x00,0x05]
+  not $3, $4               # CHECK: not $3, $4             # encoding: [0x00,0x04,0x1a,0xd0]
+  or $3, 5                 # CHECK: ori $3, $3, 5          # encoding: [0x50,0x63,0x00,0x05]
+  or $3, $4, 5             # CHECK: ori $3, $4, 5          # encoding: [0x50,0x64,0x00,0x05]
+  xor $3, 5                # CHECK: xori $3, $3, 5         # encoding: [0x70,0x63,0x00,0x05]
+  xor $3, $4, 5            # CHECK: xori $3, $4, 5         # encoding: [0x70,0x64,0x00,0x05]

llvm/trunk/test/MC/Mips/micromips64r6/invalid.s

# RUN: FileCheck %s < %t1
   bc2eqzc $31, -65537          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
   bc2eqzc $31, 65535           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
   bc2eqzc $31, 65536           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
   bc2nezc $32, 4               # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
   bc2nezc $31, -65535          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
   bc2nezc $31, -65537          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
   bc2nezc $31, 65535           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
   bc2nezc $31, 65536           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
+  andi $3, $4, -1              # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate
+  andi $3, $4, 65536           # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate
+  andi $3, -1                  # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
+  andi $3, 65536               # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
+  ori $3, $4, -1               # CHECK: :[[@LINE]]:15: error: expected 16-bit unsigned immediate
+  ori $3, $4, 65536            # CHECK: :[[@LINE]]:15: error: expected 16-bit unsigned immediate
+  ori $3, -1                   # CHECK: :[[@LINE]]:11: error: expected 16-bit unsigned immediate
+  ori $3, 65536                # CHECK: :[[@LINE]]:11: error: expected 16-bit unsigned immediate
+  xori $3, $4, -1              # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate
+  xori $3, $4, 65536           # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate
+  xori $3, -1                  # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
+  xori $3, 65536               # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
+  not $3, 4                    # CHECK: :[[@LINE]]:11: error: invalid operand for instruction

llvm/trunk/test/MC/Mips/micromips64r6/valid.s

 # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 -mattr=micromips | FileCheck %s
 a:
         .set noat
         addiur1sp $7, 4          # CHECK: addiur1sp $7, 4     # encoding: [0x6f,0x83]
         addiur2 $6, $7, -1       # CHECK: addiur2 $6, $7, -1  # encoding: [0x6f,0x7e]
         addiur2 $6, $7, 12       # CHECK: addiur2 $6, $7, 12  # encoding: [0x6f,0x76]
         addius5 $7, -2           # CHECK: addius5 $7, -2      # encoding: [0x4c,0xfc]
         addiusp -1028            # CHECK: addiusp -1028       # encoding: [0x4f,0xff]
         addiusp -1032            # CHECK: addiusp -1032       # encoding: [0x4f,0xfd]
         addiusp 1024             # CHECK: addiusp 1024        # encoding: [0x4c,0x01]
         addiusp 1028             # CHECK: addiusp 1028        # encoding: [0x4c,0x03]
         addiusp -16              # CHECK: addiusp -16         # encoding: [0x4f,0xf9]
+        and16 $16, $2            # CHECK: and16 $16, $2       # encoding: [0x44,0x21]
+        andi16 $4, $5, 8         # CHECK: andi16 $4, $5, 8    # encoding: [0x2e,0x56]
         b 132                    # CHECK: bc16 132            # encoding: [0xcc,0x42]
         bc16 132                 # CHECK: bc16 132            # encoding: [0xcc,0x42]
         beqzc16 $6, 20           # CHECK: beqzc16 $6, 20      # encoding: [0x8f,0x0a]
         bnezc16 $6, 20           # CHECK: bnezc16 $6, 20      # encoding: [0xaf,0x0a]
         daui $3, $4, 5           # CHECK: daui $3, $4, 5      # encoding: [0xf0,0x64,0x00,0x05]
         dahi $3, 4               # CHECK: dahi $3, 4          # encoding: [0x42,0x23,0x00,0x04]
         dati $3, 4               # CHECK: dati $3, 4          # encoding: [0x42,0x03,0x00,0x04]
         dext $9, $6, 3, 7        # CHECK: dext $9, $6, 3, 7   # encoding: [0x59,0x26,0x30,0xec]
         dextm $9, $6, 3, 39      # CHECK: dextm $9, $6, 3, 39 # encoding: [0x59,0x26,0x30,0xe4]
         dextu $9, $6, 35, 7      # CHECK: dextu $9, $6, 35, 7  # encoding: [0x59,0x26,0x30,0xd4]
         dalign $4, $2, $3, 5     # CHECK: dalign $4, $2, $3, 5  # encoding: [0x58,0x43,0x25,0x1c]
         ldpc $2, 16              # CHECK: ldpc $2, 16           # encoding: [0x78,0x58,0x00,0x02]
         lw $3, 32($gp)           # CHECK: lw $3, 32($gp)        # encoding: [0x65,0x88]
         lw $3, 24($sp)           # CHECK: lw $3, 24($sp)        # encoding: [0x48,0x66]
         lw16 $4, 8($17)          # CHECK: lw16 $4, 8($17)       # encoding: [0x6a,0x12]
         lhu16 $3, 4($16)         # CHECK: lhu16 $3, 4($16)      # encoding: [0x29,0x82]
         lbu16 $3, 4($17)         # CHECK: lbu16 $3, 4($17)      # encoding: [0x09,0x94]
         lbu16 $3, -1($17)        # CHECK: lbu16 $3, -1($17)     # encoding: [0x09,0x9f]
         movep $5, $6, $2, $3     # CHECK: movep $5, $6, $2, $3  # encoding: [0x84,0x34]
+        not16 $4, $7             # CHECK: not16 $4, $7          # encoding: [0x46,0x70]
+        or16 $3, $7              # CHECK: or16 $3, $7           # encoding: [0x45,0xf9]
         ll $2, 8($4)                    # CHECK: ll $2, 8($4)                    # encoding: [0x60,0x44,0x30,0x08]
         lwm32 $16, $17, 8($4)           # CHECK: lwm32 $16, $17, 8($4)           # encoding: [0x20,0x44,0x50,0x08]
         lwm32 $16, $17, 8($sp)          # CHECK: lwm32 $16, $17, 8($sp)          # encoding: [0x20,0x5d,0x50,0x08]
         lwm32 $16, $17, $ra, 8($4)      # CHECK: lwm32 $16, $17, $ra, 8($4)      # encoding: [0x22,0x44,0x50,0x08]
         lwm32 $16, $17, $ra, 64($sp)    # CHECK: lwm32 $16, $17, $ra, 64($sp)    # encoding: [0x22,0x5d,0x50,0x40]
         lwm32 $16, $17, $18, $19, 8($4) # CHECK: lwm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0x50,0x08]
         lwm32 $16, $17, $18, $19, $ra, 8($4)                          # CHECK: lwm32 $16, $17, $18, $19, $ra, 8($4)                          # encoding: [0x22,0x84,0x50,0x08]
         lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4)      # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4)      # encoding: [0x21,0x24,0x50,0x08]
a:
         dsllv $4, $5, $6         # CHECK: dsllv $4, $5, $6        # encoding: [0x58,0xa6,0x20,0x10]
         dsra $4, $5, 5           # CHECK: dsra $4, $5, 5          # encoding: [0x58,0x85,0x28,0x80]
         dsra32 $4, $5, 5         # CHECK: dsra32 $4, $5, 5        # encoding: [0x58,0x85,0x28,0x84]
         dsrav $4, $5, $6         # CHECK: dsrav $4, $5, $6        # encoding: [0x58,0xa6,0x20,0x90]
         bc1eqzc $f31, 4          # CHECK: bc1eqzc $f31, 4         # encoding: [0x41,0x1f,0x00,0x02]
         bc1nezc $f31, 4          # CHECK: bc1nezc $f31, 4         # encoding: [0x41,0x3f,0x00,0x02]
         bc2eqzc $31, 8           # CHECK: bc2eqzc $31, 8          # encoding: [0x41,0x5f,0x00,0x04]
         bc2nezc $31, 8           # CHECK: bc2nezc $31, 8          # encoding: [0x41,0x7f,0x00,0x04]
+        and $3, 5                # CHECK: andi $3, $3, 5          # encoding: [0xd0,0x63,0x00,0x05]
+        and $3, $4, 5            # CHECK: andi $3, $4, 5          # encoding: [0xd0,0x64,0x00,0x05]
+        and $3, $4, $5           # CHECK: and $3, $4, $5          # encoding: [0x00,0xa4,0x1a,0x50]
+        andi $3, $4, 1234        # CHECK: andi $3, $4, 1234       # encoding: [0xd0,0x64,0x04,0xd2]
+        nor $3, $4, $5           # CHECK: nor $3, $4, $5          # encoding: [0x00,0xa4,0x1a,0xd0]
+        not $3, $4               # CHECK: not $3, $4              # encoding: [0x00,0x04,0x1a,0xd0]
+        or $3, 5                 # CHECK: ori $3, $3, 5           # encoding: [0x50,0x63,0x00,0x05]
+        or $3, $4, 5             # CHECK: ori $3, $4, 5           # encoding: [0x50,0x64,0x00,0x05]
+        or $3, $4, $5            # CHECK: or $3, $4, $5           # encoding: [0x00,0xa4,0x1a,0x90]
+        ori $3, $4, 1234         # CHECK: ori $3, $4, 1234        # encoding: [0x50,0x64,0x04,0xd2]
+        xor $3, 5                # CHECK: xori $3, $3, 5          # encoding: [0x70,0x63,0x00,0x05]
+        xor $3, $4, 5            # CHECK: xori $3, $4, 5          # encoding: [0x70,0x64,0x00,0x05]
+        xor $3, $4, $5           # CHECK: xor $3, $4, $5          # encoding: [0x00,0xa4,0x1b,0x10]
+        xori $3, $4, 1234        # CHECK: xori $3, $4, 1234       # encoding: [0x70,0x64,0x04,0xd2]
 
 1: