llvm-mc. Enables eip-relative addressing.

[jpp]

Summary

Enables eip-based addressing, e.g.,

lea constant(%eip), %rax
lea constant(%eip), %eax

in llvm-mc, which is used in x32. EIP-base addressing is also valid in x86_64,
it is left enabled for that architecture as well.

[dschuff]

+llvm-commits

[dschuff]

Could you add a little bit more detail to the commit description (e.g. this is used for x32, it still requires x86-64 codegen, etc)

[dschuff]

LGTM

[jpp]

Adding EIP to GR32 introduces regressions in other llvm components. This patch reverts that change, and then it adds a check to Is32BitMemOperand.

This patch was tested with

ninja check-llvm.

Let me know if any other tests are needed.

[dschuff]

Looks better, thanks. I'll leave it up for a bit more in case there are more comments, and land it soon.

llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) {
   const MCOperand &BaseReg  = MI.getOperand(Op+X86::AddrBaseReg);
   const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
 
   if ((BaseReg.getReg() != 0 &&
        X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
       (IndexReg.getReg() != 0 &&
        X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
     return true;
+  if (BaseReg.getReg() == X86::EIP) {
+    assert(IndexReg.getReg() == 0 && "Invalid eip-based address.");
+    return true;
+  }
   return false;
 }
 
 /// Is64BitMemOperand - Return true if the specified instruction has
 /// a 64-bit memory operand. Op specifies the operand # of the memoperand.
 #ifndef NDEBUG
 static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) {
   const MCOperand &BaseReg  = MI.getOperand(Op+X86::AddrBaseReg);
void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
   const MCOperand &Disp     = MI.getOperand(Op+X86::AddrDisp);
   const MCOperand &Base     = MI.getOperand(Op+X86::AddrBaseReg);
   const MCOperand &Scale    = MI.getOperand(Op+X86::AddrScaleAmt);
   const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
   unsigned BaseReg = Base.getReg();
   bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX;
 
   // Handle %rip relative addressing.
-  if (BaseReg == X86::RIP) {    // [disp32+RIP] in X86-64 mode
+  if (BaseReg == X86::RIP ||
+      BaseReg == X86::EIP) {    // [disp32+rIP] in X86-64 mode
     assert(is64BitMode(STI) && "Rip-relative addressing requires 64-bit mode");
     assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
     EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
 
     unsigned FixupKind = X86::reloc_riprel_4byte;
 
     // movq loads are handled with a special relocation form which allows the
     // linker to eliminate some loads for GOT references which end up in the

llvm/trunk/test/MC/X86/x86-64.s

 // CHECK: encoding: [0xc7,0x05,A,A,A,A,0x0c,0x00,0x00,0x00]
 // CHECK:    fixup A - offset: 2, value: foo-8, kind: reloc_riprel_4byte
 
 movq  $12, foo(%rip)
 // CHECK:  movq $12, foo(%rip)
 // CHECK: encoding: [0x48,0xc7,0x05,A,A,A,A,0x0c,0x00,0x00,0x00]
 // CHECK:    fixup A - offset: 3, value: foo-8, kind: reloc_riprel_4byte
 
+movl  foo(%eip), %eax
+// CHECK: movl  foo(%eip), %eax
+// CHECK: encoding: [0x67,0x8b,0x05,A,A,A,A]
+// CHECK: fixup A - offset: 3, value: foo-4, kind: reloc_riprel_4byte
+
+movb  $12, foo(%eip)
+// CHECK: movb  $12, foo(%eip)
+// CHECK: encoding: [0x67,0xc6,0x05,A,A,A,A,0x0c]
+// CHECK:    fixup A - offset: 3, value: foo-5, kind: reloc_riprel_4byte
+
+movw  $12, foo(%eip)
+// CHECK: movw  $12, foo(%eip)
+// CHECK: encoding: [0x67,0x66,0xc7,0x05,A,A,A,A,0x0c,0x00]
+// CHECK:    fixup A - offset: 4, value: foo-6, kind: reloc_riprel_4byte
+
+movl  $12, foo(%eip)
+// CHECK: movl  $12, foo(%eip)
+// CHECK: encoding: [0x67,0xc7,0x05,A,A,A,A,0x0c,0x00,0x00,0x00]
+// CHECK:    fixup A - offset: 3, value: foo-8, kind: reloc_riprel_4byte
+
+movq  $12, foo(%eip)
+// CHECK:  movq $12, foo(%eip)
+// CHECK: encoding: [0x67,0x48,0xc7,0x05,A,A,A,A,0x0c,0x00,0x00,0x00]
+// CHECK:    fixup A - offset: 4, value: foo-8, kind: reloc_riprel_4byte
+
 // CHECK: addq  $-424, %rax
 // CHECK: encoding: [0x48,0x05,0x58,0xfe,0xff,0xff]
 addq $-424, %rax
 
 
 // CHECK: movq  _foo@GOTPCREL(%rip), %rax
 // CHECK:  encoding: [0x48,0x8b,0x05,A,A,A,A]
 // CHECK:  fixup A - offset: 3, value: _foo@GOTPCREL-4, kind: reloc_riprel_4byte_movq_load
 movq _foo@GOTPCREL(%rip), %rax
 
 // CHECK: movq  _foo@GOTPCREL(%rip), %r14
 // CHECK:  encoding: [0x4c,0x8b,0x35,A,A,A,A]
 // CHECK:  fixup A - offset: 3, value: _foo@GOTPCREL-4, kind: reloc_riprel_4byte_movq_load
 movq _foo@GOTPCREL(%rip), %r14
 
+// CHECK: movq  _foo@GOTPCREL(%eip), %rax
+// CHECK:  encoding: [0x67,0x48,0x8b,0x05,A,A,A,A]
+// CHECK:  fixup A - offset: 4, value: _foo@GOTPCREL-4, kind: reloc_riprel_4byte_movq_load
+movq _foo@GOTPCREL(%eip), %rax
+
+// CHECK: movq  _foo@GOTPCREL(%eip), %r14
+// CHECK:  encoding: [0x67,0x4c,0x8b,0x35,A,A,A,A]
+// CHECK:  fixup A - offset: 4, value: _foo@GOTPCREL-4, kind: reloc_riprel_4byte_movq_load
+movq _foo@GOTPCREL(%eip), %r14
 
 // CHECK: movq  (%r13,%rax,8), %r13
 // CHECK:  encoding: [0x4d,0x8b,0x6c,0xc5,0x00]
 movq 0x00(%r13,%rax,8),%r13
 
 // CHECK: testq %rax, %rbx
 // CHECK:  encoding: [0x48,0x85,0xc3]
 testq %rax, %rbx