[mips][microMIPS] Implement DBITSWAP, DLSA and LWUPC and add tests for AUI instructions

[mamidzic]

Summary

The patch implements microMIPS64r6 DBITSWAP, DLSA, LWUPC and adds tests for AUI instructions.

[sdardis]

The LLX/SCX family of instructions are being changed, so they can be dropped from this patch.

You should retitle this patch to reflect that you're adding tests for aui, rather than implementing it.

Can you rebase and repost?

lib/Target/Mips/MicroMips64r6InstrInfo.td

111 ↗

(On Diff #45654)

Needs MayLoad = 1.

125 ↗

(On Diff #45654)

Needs mayLoad = 1

lib/Target/Mips/Mips64r6InstrInfo.td

96 ↗

(On Diff #45654)

DLSA also needs to have the NotInMicroMips predicate.

[hvarga]

Updated according to the comments from sdardis.

[sdardis]

Some small nits.

Thanks,
Simon

lib/Target/Mips/MicroMips64r6InstrFormats.td

169–170 ↗

(On Diff #56665)

Nit, bits 25-21 encode rt, 20-16 encode rs.

178–184 ↗

(On Diff #56665)

Nit: rs should be rt here.

lib/Target/Mips/MicroMips64r6InstrInfo.td

188–190 ↗

(On Diff #56665)

Nit, rs -> rt.

194–202 ↗

(On Diff #56665)

I believe this is redundant, I'm not seeing anything use this.

test/MC/Mips/micromips64r6/invalid.s

233 ↗

(On Diff #56665)

Check that a signed immediate offset > 19 bits is rejected for lwupc.
Check that a signed immediate > 16 bits is rejected for aui.

[hvarga]

Updated according to the comments from sdardis.

[sdardis]

Some small nits. There's only one significant change required for the predicate for lwupc. We need to see if we can evaluate it as something relocatable and that the constant part is scaled too.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

1110–1116 ↗

(On Diff #59036)

This almost correct. We need to check for constants, symbols and symbols + offsets. The offset then has to be in the scaled form. I've given this an attempt with:

if (isConstantImm() && isShiftedInt<Bits, ShiftLeftAmount>(getConstantImm()))                                      
  return true; 
// Operand can also be a symbol or symbol plus offset in case of relocations.
if (Kind != k_Immediate)
  return false;
MCValue Res;
bool Success = getImm()->evaluateAsRelocatable(Res, nullptr, nullptr);
return Success && isShiftedInt<Bits, ShiftLeftAmount>(Res.getConstant());

Which also checks the offset. The code would also need to check that it's an immediate.

lib/Target/Mips/MicroMips64r6InstrFormats.td

189 ↗

(On Diff #59036)

This should be called POOL32S_DBITSWAP_FM_MMR6, as it's in pool32s.

207–215 ↗

(On Diff #59036)

'imm' should be 'sa' to match the documentation

lib/Target/Mips/MicroMips64r6InstrInfo.td

257–258 ↗

(On Diff #59036)

Nit: imm should be sa.

262–267 ↗

(On Diff #59036)

Needs MayLoad = 1.

lib/Target/Mips/Mips32r6InstrInfo.td

769–772 ↗

(On Diff #59036)

Join these "let AdditionalPredicates =" blocks together.

lib/Target/Mips/MipsInstrInfo.td

409 ↗

(On Diff #59036)

I think this should have a different name, as lwupc doesn't jump.

test/MC/Mips/micromips64r6/invalid.s

282 ↗

(On Diff #59036)

Check that symbol + offset where the offset is not a multiple of 4 is rejected as well and that register + register is rejected as well.

test/MC/Mips/micromips64r6/valid.s

283 ↗

(On Diff #59036)

Also check that a symbol and symbol + offset where the offset is a multiple of 4 is also accepted for lwupc.

[sdardis]

Also, the patch summary needs to be updated.

[hvarga]

isScaledSimm code replaced with the code you suggested.
Changed FM classes so that they inherit from MipsR6Inst and MMR6Arch.
Changed DESC classes so that they don't inherit from MipsR6Inst and MMR6Arch.
Changed name of MipsJumpTargetAsmOperandClass to MipsSimmAsmOperandClass.
Added DBITSWAP, LWUPC and DLCA to instruction mapping tables.
Added valid and invalid tests for LWUPC with symbols.

Note: Didn't set the MayLoad flag to 1 in LWUPC DESC class, because with it, LWUPC tests with symbols cause an assertion fail: "Assertion `isReg() && "This is not a register operand!"' failed.". I didn't find a way around that.

[sdardis]

Note: Didn't set the MayLoad flag to 1 in LWUPC DESC class, because with it, LWUPC tests with symbols cause an assertion fail: "Assertion `isReg() && "This is not a register operand!"' failed.". I didn't find a way around that.

Yes, when an instruction with mayLoad/myStore is processed in MipsAsmParser::expandLoadInst assumes that all load instructions have both a source and destination register. lwupc however doesn't have a source register, merely an enlarged offset or symbol.

Tablegen has inferred that lwupc doesn't load, and so doesn't mark it as a load, the symbol 'bar' gets handled with a relocation. This leads to a correct result but it has a mis-defined instruction.

You can fix this easily enough by making some fairly simple changes. Extend the MipsInst class to have a "isPCRelativeLoad" member in MipsInstrFormats.td, make the corresponding change in MipsInstrInfo.h, then only check normal load/store instructions for expansion in processInstruction. Look at isCTI for an example.

I have some more comments inline.

Thanks

lib/Target/Mips/MicroMips64r6InstrInfo.td

319 ↗

(On Diff #64109)

This requires the instruction itinerary, II_DBITSWAP.

325 ↗

(On Diff #64109)

This requires the instruction itinerary, II_DLSA.

lib/Target/Mips/MipsInstrInfo.td

416–424 ↗

(On Diff #64109)

Calll this SimmLslAsmOperandClass instead, change the Name to reflect the class and remove the ParserMethod, the generic parser can handle the necessary cases.

631–632 ↗

(On Diff #64109)

Drop the 'Mips' from the names here.

[mamidzic]

Added instruction itineraries to DBITSWAP and DLSA instructions.
Changed to MipsSimmAsmOperandClass to SimmLslAsmOperandClass, removed the parser method and changed the Name.
Changed MipsSimm19Lsl2AsmOperand to Simm19Lsl2AsmOperand.
Added isPCRelativeLoad flag to TSFlags.
Added mayLoad and is PCRelativeLoad to LWUPC instruction.
Added isPCRelativeLoad check to processInstruction.

[sdardis]

LGTM. Add the relevant disassembler tests when you commit.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

1848 ↗

(On Diff #69560)

Add a space before this line for vertical separation, so it's clear the the following code is unrelated to the block above.

lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h

124–126 ↗

(On Diff #69560)

Nit: Style, capitalize the first letter in IsPCRelativeLoad.

A better description is 'A Load instruction with implicit source register ($pc) with explicit offset and destination register'.

lib/Target/Mips/MipsInstrFormats.td

101 ↗

(On Diff #69560)

See my comment about IsPCRelativeLoad in MipsBaseInfo.h

llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "MCTargetDesc/MipsABIInfo.h"
 #include "MCTargetDesc/MipsMCExpr.h"
 #include "MCTargetDesc/MipsMCTargetDesc.h"
 #include "MipsRegisterInfo.h"
 #include "MipsTargetObjectFile.h"
 #include "MipsTargetStreamer.h"
+#include "MCTargetDesc/MipsBaseInfo.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstBuilder.h"
 #include "llvm/MC/MCParser/MCAsmLexer.h"
 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
public:
   }
   template <unsigned Bits, unsigned ShiftLeftAmount>
   bool isScaledUImm() const {
     return isConstantImm() &&
            isShiftedUInt<Bits, ShiftLeftAmount>(getConstantImm());
   }
   template <unsigned Bits, unsigned ShiftLeftAmount>
   bool isScaledSImm() const {
-    return isConstantImm() &&
-           isShiftedInt<Bits, ShiftLeftAmount>(getConstantImm());
+    if (isConstantImm() && isShiftedInt<Bits, ShiftLeftAmount>(getConstantImm()))
+      return true;
+    // Operand can also be a symbol or symbol plus offset in case of relocations.
+    if (Kind != k_Immediate)
+      return false;
+    MCValue Res;
+    bool Success = getImm()->evaluateAsRelocatable(Res, nullptr, nullptr);
+    return Success && isShiftedInt<Bits, ShiftLeftAmount>(Res.getConstant());
   }
   bool isRegList16() const {
     if (!isRegList())
       return false;
 
     int Size = RegList.List->size();
     if (Size < 2 || Size > 5)
       return false;
if ((Inst.getOpcode() == Mips::JAL || Inst.getOpcode() == Mips::JAL_MM) &&
     // FIXME: Add an R_(MICRO)MIPS_JALR relocation after the JALR.
     // This relocation is supposed to be an optimization hint for the linker
     // and is not necessary for correctness.
 
     Inst = JalrInst;
     ExpandedJalSym = true;
   }
 
-  if (MCID.mayLoad() || MCID.mayStore()) {
+  bool IsPCRelativeLoad = (MCID.TSFlags & MipsII::IsPCRelativeLoad) != 0;
+  if ((MCID.mayLoad() || MCID.mayStore()) && !IsPCRelativeLoad) {
     // Check the offset of memory operand, if it is a symbol
     // reference or immediate we may have to expand instructions.
     for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
       const MCOperandInfo &OpInfo = MCID.OpInfo[i];
       if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) ||
           (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
         MCOperand &Op = Inst.getOperand(i);
         if (Op.isImm()) {
bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_UImm16:
   case Match_UImm16_Relaxed:
     return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
                  "expected 16-bit unsigned immediate");
   case Match_SImm16:
   case Match_SImm16_Relaxed:
     return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
                  "expected 16-bit signed immediate");
+  case Match_SImm19_Lsl2:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+                 "expected both 19-bit signed immediate and multiple of 4");
   case Match_UImm20_0:
     return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
                  "expected 20-bit unsigned immediate");
   case Match_UImm26_0:
     return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
                  "expected 26-bit unsigned immediate");
   case Match_SImm32:
   case Match_SImm32_Relaxed:

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h

enum {
     FrmFI = 5,
     /// FrmOther - This form is for instructions that have no specific format.
     FrmOther = 6,
 
     FormMask = 15,
     /// IsCTI - Instruction is a Control Transfer Instruction.
     IsCTI = 1 << 4,
     /// HasForbiddenSlot - Instruction has a forbidden slot.
-    HasForbiddenSlot = 1 << 5
+    HasForbiddenSlot = 1 << 5,
+    /// IsPCRelativeLoad - A Load instruction with implicit source register
+    ///                    ($pc) with explicit offset and destination register
+    IsPCRelativeLoad = 1 << 6
 
   };
 }
 }
 
 #endif

llvm/trunk/lib/Target/Mips/MicroMips64r6InstrFormats.td

class POOL32S_3R_FM_MMR6<string instr_asm, bits<9> funct>
 
   let Inst{31-26} = 0b010110;
   let Inst{25-21} = rt;
   let Inst{20-16} = rs;
   let Inst{15-11} = rd;
   let Inst{10-9}  = 0b00;
   let Inst{8-0}   = funct;
 }
+
+class POOL32S_DBITSWAP_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm>,
+      MipsR6Inst {
+  bits<5> rt;
+  bits<5> rd;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b010110;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rd;
+  let Inst{15-12}  = 0b0000;
+  let Inst{11-6}  = 0b101100;
+  let Inst{5-0}   = 0b111100;
+}
+
+class POOL32S_3RSA_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm>,
+      MipsR6Inst {
+  bits<5> rt;
+  bits<5> rs;
+  bits<5> rd;
+  bits<2> sa;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b010110;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rs;
+  let Inst{15-11} = rd;
+  let Inst{10-9} = sa;
+  let Inst{8-6} = 0b100;
+  let Inst{5-0} = 0b000100;
+}
+
+class PCREL_1ROFFSET19_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm>,
+      MipsR6Inst {
+  bits<5> rt;
+  bits<19> offset;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b011110;
+  let Inst{25-21} = rt;
+  let Inst{20-19} = 0b10;
+  let Inst{18-0} = offset;
+}

llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td

 class DROTRV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"drotrv", 0b011010000>;
 class LD_MM64R6_ENC : LD_SD_32_2R_OFFSET16_FM_MMR6<"ld", 0b110111>;
 class LLD_MM64R6_ENC : POOL32C_2R_OFFSET12_FM_MMR6<"lld", 0b0111>;
 class LWU_MM64R6_ENC : POOL32C_2R_OFFSET12_FM_MMR6<"lwu", 0b1110>;
 class SD_MM64R6_ENC : LD_SD_32_2R_OFFSET16_FM_MMR6<"sd", 0b110110>;
 class DSRL_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsrl", 0b001000000>;
 class DSRL32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsrl32", 0b001001000>;
 class DSRLV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"dsrlv", 0b001010000>;
+class DBITSWAP_MM64R6_ENC : POOL32S_DBITSWAP_FM_MMR6<"dbitswap">;
+class DLSA_MM64R6_ENC : POOL32S_3RSA_FM_MMR6<"dlsa">;
+class LWUPC_MM64R6_ENC : PCREL_1ROFFSET19_FM_MMR6<"lwupc">;
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Descriptions
 //
 //===----------------------------------------------------------------------===//
 
 class DAUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
class SD_MM64R6_DESC {
   list<dag> Pattern = [(store GPR64Opnd:$rt, addr:$addr)];
   InstrItinClass Itinerary = II_SD;
   Format Form = FrmI;
   bit mayStore = 1;
   string BaseOpcode = "sd";
   string DecoderMethod = "DecodeMemMMImm16";
 }
 
+class DBITSWAP_MM64R6_DESC {
+  dag OutOperandList = (outs GPR64Opnd:$rd);
+  dag InOperandList = (ins GPR64Opnd:$rt);
+  string AsmString = !strconcat("dbitswap", "\t$rd, $rt");
+  list<dag> Pattern = [];
+  InstrItinClass Itinerary = II_DBITSWAP;
+}
+
+class DLSA_MM64R6_DESC {
+  dag OutOperandList = (outs GPR64Opnd:$rd);
+  dag InOperandList = (ins GPR64Opnd:$rt, GPR64Opnd:$rs, uimm2_plus1:$sa);
+  string AsmString = "dlsa\t$rt, $rs, $rd, $sa";
+  list<dag> Pattern = [];
+  InstrItinClass Itinerary = II_DLSA;
+}
+
+class LWUPC_MM64R6_DESC {
+  dag OutOperandList = (outs GPR64Opnd:$rt);
+  dag InOperandList = (ins simm19_lsl2:$offset);
+  string AsmString = "lwupc\t$rt, $offset";
+  list<dag> Pattern = [];
+  InstrItinClass Itinerary = II_LWUPC;
+  bit mayLoad = 1;
+  bit IsPCRelativeLoad = 1;
+}
+
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
 //
 //===----------------------------------------------------------------------===//
 
 let DecoderNamespace = "MicroMipsR6" in {
   def DAUI_MM64R6 : StdMMR6Rel, DAUI_MMR6_DESC, DAUI_MMR6_ENC, ISA_MICROMIPS64R6;
let DecoderNamespace = "MicroMipsR6" in {
   def SD_MM64R6 : StdMMR6Rel, SD_MM64R6_ENC, SD_MM64R6_DESC,
                   ISA_MICROMIPS64R6;
   def DSRL_MM64R6 : StdMMR6Rel, DSRL_MM64R6_ENC, DSRL_MM64R6_DESC,
                     ISA_MICROMIPS64R6;
   def DSRL32_MM64R6 : StdMMR6Rel, DSRL32_MM64R6_ENC, DSRL32_MM64R6_DESC,
                       ISA_MICROMIPS64R6;
   def DSRLV_MM64R6 : StdMMR6Rel, DSRLV_MM64R6_ENC, DSRLV_MM64R6_DESC,
                      ISA_MICROMIPS64R6;
+  def DBITSWAP_MM64R6 : R6MMR6Rel, DBITSWAP_MM64R6_ENC, DBITSWAP_MM64R6_DESC,
+                        ISA_MICROMIPS64R6;
+  def DLSA_MM64R6 : R6MMR6Rel, DLSA_MM64R6_ENC, DLSA_MM64R6_DESC,
+                    ISA_MICROMIPS64R6;
+  def LWUPC_MM64R6 : R6MMR6Rel, LWUPC_MM64R6_ENC, LWUPC_MM64R6_DESC,
+                     ISA_MICROMIPS64R6;
 }
 
 let AdditionalPredicates = [InMicroMips] in
 defm : MaterializeImms<i64, ZERO_64, DADDIU_MM64R6, LUi64, ORi64>;
 
 //===----------------------------------------------------------------------===//
 //
 // Arbitrary patterns that map to one or more instructions

llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td

let AdditionalPredicates = [NotInMicroMips] in {
   def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6;
   def LL_R6 : LL_R6_ENC, LL_R6_DESC, PTR_32, ISA_MIPS32R6;
 }
 def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6;
 let AdditionalPredicates = [NotInMicroMips] in {
   def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6;
 }
 def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
-def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
 let AdditionalPredicates = [NotInMicroMips] in {
+  def LWUPC : R6MMR6Rel, LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
   def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6, HARDFLOAT;

llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td

 //
 //===----------------------------------------------------------------------===//
 
 let AdditionalPredicates = [NotInMicroMips] in {
   def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
   def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
   def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
   def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
-}
-def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
-let AdditionalPredicates = [NotInMicroMips] in {
+  def DBITSWAP : R6MMR6Rel, DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
   def DCLO_R6 : R6MMR6Rel, DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
   def DCLZ_R6 : R6MMR6Rel, DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
   def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
   def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
   def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
   def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
-}
-def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;
-let AdditionalPredicates = [NotInMicroMips] in {
+  def DLSA_R6 : R6MMR6Rel, DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;
   def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
   def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
   def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
   def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
   def LLD_R6 : R6MMR6Rel, LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS64R6;
 }
 def LDPC: R6MMR6Rel, LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
 def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;

llvm/trunk/lib/Target/Mips/MipsInstrFormats.td

class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
 
   //
   // Attributes specific to Mips instructions...
   //
   bits<4> FormBits     = Form.Value;
   bit isCTI            = 0; // Any form of Control Transfer Instruction.
                             // Required for MIPSR6
   bit hasForbiddenSlot = 0; // Instruction has a forbidden slot.
+  bit IsPCRelativeLoad = 0; // Load instruction with implicit source register
+                            // ($pc) and with explicit offset and destination
+                            // register
 
   // TSFlags layout should be kept in sync with MipsInstrInfo.h.
   let TSFlags{3-0}   = FormBits;
   let TSFlags{4}     = isCTI;
   let TSFlags{5}     = hasForbiddenSlot;
+  let TSFlags{6}     = IsPCRelativeLoad;
 
   let DecoderNamespace = "Mips";
 
   field bits<32> SoftFail = 0;
 }
 
 // Mips32/64 Instruction Format
 class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

class ConstantSImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = [],
                                   int Offset = 0> : AsmOperandClass {
   let Name = "ConstantSImm" # Bits # "_" # Offset;
   let RenderMethod = "addConstantSImmOperands<" # Bits # ", " # Offset # ">";
   let PredicateMethod = "isConstantSImm<" # Bits # ", " # Offset # ">";
   let SuperClasses = Supers;
   let DiagnosticType = "SImm" # Bits # "_" # Offset;
 }
 
+class SimmLslAsmOperandClass<int Bits, list<AsmOperandClass> Supers = [],
+                                  int Shift = 0> : AsmOperandClass {
+  let Name = "Simm" # Bits # "_Lsl" # Shift;
+  let RenderMethod = "addImmOperands";
+  let PredicateMethod = "isScaledSImm<" # Bits # ", " # Shift # ">";
+  let SuperClasses = Supers;
+  let DiagnosticType = "SImm" # Bits # "_Lsl" # Shift;
+}
+
 class ConstantUImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = [],
                                   int Offset = 0> : AsmOperandClass {
   let Name = "ConstantUImm" # Bits # "_" # Offset;
   let RenderMethod = "addConstantUImmOperands<" # Bits # ", " # Offset # ">";
   let PredicateMethod = "isConstantUImm<" # Bits # ", " # Offset # ">";
   let SuperClasses = Supers;
   let DiagnosticType = "UImm" # Bits # "_" # Offset;
 }
def SImm32RelaxedAsmOperandClass
   let DiagnosticType = "SImm32_Relaxed";
 }
 def SImm32AsmOperandClass
     : SImmAsmOperandClass<32, [SImm32RelaxedAsmOperandClass]>;
 def ConstantUImm26AsmOperandClass
     : ConstantUImmAsmOperandClass<26, [SImm32AsmOperandClass]>;
 def ConstantUImm20AsmOperandClass
     : ConstantUImmAsmOperandClass<20, [ConstantUImm26AsmOperandClass]>;
+def ConstantSImm19Lsl2AsmOperandClass : AsmOperandClass {
+  let Name = "SImm19Lsl2";
+  let RenderMethod = "addImmOperands";
+  let PredicateMethod = "isScaledSImm<19, 2>";
+  let SuperClasses = [ConstantUImm20AsmOperandClass];
+  let DiagnosticType = "SImm19_Lsl2";
+}
 def UImm16RelaxedAsmOperandClass
     : UImmAsmOperandClass<16, [ConstantUImm20AsmOperandClass]> {
   let Name = "UImm16_Relaxed";
   let PredicateMethod = "isAnyImm<16>";
   let DiagnosticType = "UImm16_Relaxed";
 }
 def UImm16AsmOperandClass
     : UImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]>;

 def ConstantImmzAsmOperandClass : AsmOperandClass {
   let Name = "ConstantImmz";
   let RenderMethod = "addConstantUImmOperands<1>";
   let PredicateMethod = "isConstantImmz";
   let SuperClasses = [ConstantUImm1AsmOperandClass];
   let DiagnosticType = "Immz";
 }
 
+def Simm19Lsl2AsmOperand
+    : SimmLslAsmOperandClass<19, [], 2>;
+
 def MipsJumpTargetAsmOperand : AsmOperandClass {
   let Name = "JumpTarget";
   let ParserMethod = "parseJumpTarget";
   let PredicateMethod = "isImm";
   let RenderMethod = "addImmOperands";
 }
 
 // Instruction operand types
def calltarget  : Operand<iPTR> {
   let ParserMatchClass = MipsJumpTargetAsmOperand;
 }
 
 def imm64: Operand<i64>;
 
 def simm19_lsl2 : Operand<i32> {
   let EncoderMethod = "getSimm19Lsl2Encoding";
   let DecoderMethod = "DecodeSimm19Lsl2";
-  let ParserMatchClass = MipsJumpTargetAsmOperand;
+  let ParserMatchClass = Simm19Lsl2AsmOperand;
 }
 
 def simm18_lsl3 : Operand<i32> {
   let EncoderMethod = "getSimm18Lsl3Encoding";
   let DecoderMethod = "DecodeSimm18Lsl3";
   let ParserMatchClass = MipsJumpTargetAsmOperand;
 }
 

llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt

 0x54 0x22 0x10 0x3b # CHECK: cfc1 $1, $2
 0x00 0x64 0xcd 0x3c # CHECK: cfc2 $3, $4
 0x54 0xa6 0x18 0x3b # CHECK: ctc1 $5, $6
 0x00 0xe8 0xdd 0x3c # CHECK: ctc2 $7, $8
 0xd4 0xc6 0x00 0x20 # CHECK: bltzc $6, 132
 0xf4 0x40 0x00 0x40 # CHECK: blezc $2, 260
 0xf6 0x10 0x00 0x80 # CHECK: bgezc $16, 516
 0xd5 0x80 0x01 0x00 # CHECK: bgtzc $12, 1028
+0x10 0x64 0x01 0x00 # CHECK: aui $3, $4, 256
+0x58 0x83 0x0b 0x3c # CHECK: dbitswap $3, $4
+0x58 0x64 0x2d 0x04 # CHECK: dlsa $3, $4, $5, 3
+0x78 0x50 0x00 0x43 # CHECK: lwupc $2, 268

llvm/trunk/test/MC/Mips/micromips64r6/invalid.s

# RUN: FileCheck %s < %t1
   beqzc $2, -4194303       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
   beqzc $2, 4194304        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
   beqzc $2, 4194303        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
   bnezc $0, 12             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
   bnezc $2, -4194308       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
   bnezc $2, -4194303       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
   bnezc $2, 4194304        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
   bnezc $2, 4194303        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
+  dlsa $3, $4, $5, 5           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected immediate in range 1 .. 4
+  dlsa $3, $4, $5, -1          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected immediate in range 1 .. 4
+  dlsa $3, $4, $5, 0           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected immediate in range 1 .. 4
+  lwupc $2, 262145             # CHECK: :[[@LINE]]:13: error: expected both 19-bit signed immediate and multiple of 4
+  lwupc $2, 5                  # CHECK: :[[@LINE]]:13: error: expected both 19-bit signed immediate and multiple of 4
+  lwupc $2, -262145            # CHECK: :[[@LINE]]:13: error: expected both 19-bit signed immediate and multiple of 4
+  lwupc $2, $2                 # CHECK: :[[@LINE]]:13: error: expected both 19-bit signed immediate and multiple of 4
+  lwupc $2, bar+267            # CHECK: :[[@LINE]]:13: error: expected both 19-bit signed immediate and multiple of 4
+  aui $3, $4, 32768            # CHECK: :[[@LINE]]:15: error: expected 16-bit signed immediate
+  aui $3, $4, -32769           # CHECK: :[[@LINE]]:15: error: expected 16-bit signed immediate

llvm/trunk/test/MC/Mips/micromips64r6/valid.s

a:
         cfc1 $1, $2              # CHECK: cfc1 $1, $2             # encoding: [0x54,0x22,0x10,0x3b]
         cfc2 $3, $4              # CHECK: cfc2 $3, $4             # encoding: [0x00,0x64,0xcd,0x3c]
         ctc1 $5, $6              # CHECK: ctc1 $5, $6             # encoding: [0x54,0xa6,0x18,0x3b]
         ctc2 $7, $8              # CHECK: ctc2 $7, $8             # encoding: [0x00,0xe8,0xdd,0x3c]
         bltzc $6, 128            # CHECK: bltzc $6, 128           # encoding: [0xd4,0xc6,0x00,0x20]
         blezc $2, 256            # CHECK: blezc $2, 256           # encoding: [0xf4,0x40,0x00,0x40]
         bgezc $16, 512           # CHECK: bgezc $16, 512          # encoding: [0xf6,0x10,0x00,0x80]
         bgtzc $12, 1024          # CHECK: bgtzc $12, 1024         # encoding: [0xd5,0x80,0x01,0x00]
+        aui $3, $4, 256          # CHECK: aui $3, $4, 256         # encoding: [0x10,0x64,0x01,0x00]
+        dbitswap $3, $4          # CHECK: dbitswap $3, $4         # encoding: [0x58,0x83,0x0b,0x3c]
+        dlsa $3, $4, $5, 3       # CHECK: dlsa $3, $4, $5, 3      # encoding: [0x58,0x64,0x2d,0x04]
+        lwupc $2, 268            # CHECK: lwupc $2, 268           # encoding: [0x78,0x50,0x00,0x43]
+        lwupc $2, bar            # CHECK: lwupc $2, bar           # encoding: [0x78,0b01010AAA,A,A]
+        lwupc $2, bar+268        # CHECK: lwupc $2, bar+268       # encoding: [0x78,0b01010AAA,A,A]
 
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