[X86][AVX512] add encoding and intrinsics for Multishift

[AsafBadouh]

Summary

multishift is part of VBMI feature.

[AsafBadouh]

This comment was removed by AsafBadouh.

[AsafBadouh]

ping

[delena]

E:/Work/LLVM/llvm/include/llvm/IR/IntrinsicsX86.td

2514 ↗

(On Diff #45506)

The types you wrote here don't match GCC
return (m512i) builtin_ia32_vpmultishiftqb512_mask ((v64qi) X,

(__v64qi) __Y,
(__v64qi) __W,
(__mmask64) __M);

[AsafBadouh]

change types to be align with GCC builtins

[delena]

E:/Work/LLVM/llvm/lib/Target/X86/X86InstrAVX512.td

3433 ↗

(On Diff #46486)

broadcast is the same for all cases, you don't need to pass it

[AsafBadouh]

changes according to Elena's comment.

[AsafBadouh]

ping

[delena]

LGTM

llvm/trunk/include/llvm/IR/IntrinsicsX86.td

def int_x86_avx512_mask_psrl_qi_128: GCCBuiltin<"__builtin_ia32_psrlqi128_mask">,
         Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty,
                    llvm_i8_ty, llvm_v2i64_ty,  llvm_i8_ty], [IntrNoMem]>;
   def int_x86_avx512_mask_psrl_qi_256: GCCBuiltin<"__builtin_ia32_psrlqi256_mask">,
         Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
                    llvm_i8_ty, llvm_v4i64_ty,  llvm_i8_ty], [IntrNoMem]>;
   def int_x86_avx512_mask_psrl_qi_512: GCCBuiltin<"__builtin_ia32_psrlqi512_mask">,
         Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty, 
                    llvm_i8_ty, llvm_v8i64_ty,  llvm_i8_ty], [IntrNoMem]>;
+  def int_x86_avx512_mask_pmultishift_qb_128:
+        GCCBuiltin<"__builtin_ia32_vpmultishiftqb128_mask">,
+        Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, 
+                   llvm_v16i8_ty, llvm_v16i8_ty, llvm_i16_ty], [IntrNoMem]>;
+  def int_x86_avx512_mask_pmultishift_qb_256: 
+        GCCBuiltin<"__builtin_ia32_vpmultishiftqb256_mask">,
+        Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty, 
+                   llvm_v32i8_ty, llvm_v32i8_ty, llvm_i32_ty], [IntrNoMem]>;
+  def int_x86_avx512_mask_pmultishift_qb_512:
+        GCCBuiltin<"__builtin_ia32_vpmultishiftqb512_mask">,
+        Intrinsic<[llvm_v64i8_ty], [llvm_v64i8_ty, 
+                   llvm_v64i8_ty, llvm_v64i8_ty, llvm_i64_ty], [IntrNoMem]>;
 }
 // Permute
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_avx512_mask_perm_df_256 : GCCBuiltin<"__builtin_ia32_permdf256_mask">,
               Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty,
                         llvm_i8_ty, llvm_v4f64_ty, llvm_i8_ty], [IntrNoMem]>;
   def int_x86_avx512_mask_perm_df_512 : GCCBuiltin<"__builtin_ia32_permdf512_mask">,
               Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty,

llvm/trunk/lib/Target/X86/X86ISelLowering.h

enum NodeType : unsigned {
       // Vector packed double/float comparison.
       CMPP,
 
       // Vector integer comparisons.
       PCMPEQ, PCMPGT,
       // Vector integer comparisons, the result is in a mask vector.
       PCMPEQM, PCMPGTM,
 
+      MULTISHIFT,
+
       /// Vector comparison generating mask bits for fp and
       /// integer signed and unsigned data types.
       CMPM,
       CMPMU,
       // Vector comparison with rounding mode for FP values
       CMPM_RND,
 
       // Arithmetic operations with FLAGS results.

llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
   case X86ISD::AVG:                return "X86ISD::AVG";
   case X86ISD::MULHRS:             return "X86ISD::MULHRS";
   case X86ISD::SINT_TO_FP_RND:     return "X86ISD::SINT_TO_FP_RND";
   case X86ISD::UINT_TO_FP_RND:     return "X86ISD::UINT_TO_FP_RND";
   case X86ISD::FP_TO_SINT_RND:     return "X86ISD::FP_TO_SINT_RND";
   case X86ISD::FP_TO_UINT_RND:     return "X86ISD::FP_TO_UINT_RND";
   case X86ISD::VFPCLASS:           return "X86ISD::VFPCLASS";
   case X86ISD::VFPCLASSS:          return "X86ISD::VFPCLASSS";
+  case X86ISD::MULTISHIFT:         return "X86ISD::MULTISHIFT";
   }
   return nullptr;
 }
 
 // isLegalAddressingMode - Return true if the addressing mode represented
 // by AM is legal for this target, for a load/store of the specified type.
 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
                                               const AddrMode &AM, Type *Ty,

llvm/trunk/lib/Target/X86/X86InstrAVX512.td

multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
   defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
                                     itins, HasAVX512, IsCommutable>,
               avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
                                     itins, HasBWI, IsCommutable>;
 }
 
 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
                             SDNode OpNode,X86VectorVTInfo _Src,
-                            X86VectorVTInfo _Dst, bit IsCommutable = 0> {
+                            X86VectorVTInfo _Dst, X86VectorVTInfo _Brdct,
+                            bit IsCommutable = 0> {
   defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
                             (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
                             "$src2, $src1","$src1, $src2",
                             (_Dst.VT (OpNode
                                          (_Src.VT _Src.RC:$src1),
                                          (_Src.VT _Src.RC:$src2))),
                             itins.rr, IsCommutable>,
                             AVX512BIBase, EVEX_4V;
   let mayLoad = 1 in {
       defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
                             (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
                             "$src2, $src1", "$src1, $src2",
                             (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
                                           (bitconvert (_Src.LdFrag addr:$src2)))),
                             itins.rm>,
                             AVX512BIBase, EVEX_4V;
 
       defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
                         (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
                         OpcodeStr,
-                        "${src2}"##_Dst.BroadcastStr##", $src1",
+                        "${src2}"##_Brdct.BroadcastStr##", $src1",
                          "$src1, ${src2}"##_Dst.BroadcastStr,
                         (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
-                                     (_Dst.VT (X86VBroadcast
-                                              (_Dst.ScalarLdFrag addr:$src2)))))),
+                                     (_Brdct.VT (X86VBroadcast
+                                              (_Brdct.ScalarLdFrag addr:$src2)))))),
                         itins.rm>,
                         AVX512BIBase, EVEX_4V, EVEX_B;
   }
 }
 
 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
                                     SSE_INTALU_ITINS_P, 1>;
 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
defm VPMULHW : avx512_binop_rm_vl_w<0xE5, "vpmulhw", mulhs, SSE_INTALU_ITINS_P,
                                     HasBWI, 1>;
 defm VPMULHUW : avx512_binop_rm_vl_w<0xE4, "vpmulhuw", mulhu, SSE_INTMUL_ITINS_P,
                                      HasBWI, 1>;
 defm VPMULHRSW : avx512_binop_rm_vl_w<0x0B, "vpmulhrsw", X86mulhrs, SSE_INTMUL_ITINS_P,
                                       HasBWI, 1>, T8PD;
 defm VPAVG : avx512_binop_rm_vl_bw<0xE0, 0xE3, "vpavg", X86avg,
                                    SSE_INTALU_ITINS_P, HasBWI, 1>;
 
-multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
-                            SDNode OpNode, bit IsCommutable = 0> {
-
+multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins, 
+                            AVX512VLVectorVTInfo _SrcVTInfo, AVX512VLVectorVTInfo _DstVTInfo,
+                            SDNode OpNode, Predicate prd,  bit IsCommutable = 0> {
+  let Predicates = [prd] in
     defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
-                                 v16i32_info, v8i64_info, IsCommutable>,
+                                 _SrcVTInfo.info512, _DstVTInfo.info512,
+                                 v8i64_info, IsCommutable>,
                                   EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
-  let Predicates = [HasVLX] in {
+  let Predicates = [HasVLX, prd] in {
     defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
-                                      v8i32x_info, v4i64x_info, IsCommutable>,
+                                      _SrcVTInfo.info256, _DstVTInfo.info256, 
+                                      v4i64x_info, IsCommutable>,
                                       EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
     defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
-                                      v4i32x_info, v2i64x_info, IsCommutable>,
+                                      _SrcVTInfo.info128, _DstVTInfo.info128, 
+                                      v2i64x_info, IsCommutable>,
                                      EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
   }
 }
 
 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
-                   X86pmuldq, 1>,T8PD;
-defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
-                   X86pmuludq, 1>;
+                                avx512vl_i32_info, avx512vl_i64_info,
+                                X86pmuldq, HasAVX512, 1>,T8PD;
+defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P, 
+                                avx512vl_i32_info, avx512vl_i64_info,
+                                X86pmuludq, HasAVX512, 1>;
+defm VPMULTISHIFTQB : avx512_binop_all<0x83, "vpmultishiftqb", SSE_INTALU_ITINS_P,
+                                avx512vl_i8_info, avx512vl_i8_info,
+                                X86multishift, HasVBMI, 0>, T8PD;
 
 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
                             X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
   let mayLoad = 1 in {
       defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
                         (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
                         OpcodeStr,
                         "${src2}"##_Src.BroadcastStr##", $src1",

llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td

 def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW",
                   SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i16>,
                                        SDTCVecEltisVT<1, i8>,
                                        SDTCisSameSizeAs<0,1>,
                                        SDTCisSameAs<1,2>, SDTCisInt<3>]>>;
 def X86andnp   : SDNode<"X86ISD::ANDNP",
                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
                                       SDTCisSameAs<0,2>]>>;
+def X86multishift   : SDNode<"X86ISD::MULTISHIFT",
+                 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
+                                      SDTCisSameAs<1,2>]>>;
 def X86psign   : SDNode<"X86ISD::PSIGN",
                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
                                       SDTCisSameAs<0,2>]>>;
 def X86pextrb  : SDNode<"X86ISD::PEXTRB",
                  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v16i8>,
                                       SDTCisPtrTy<2>]>>;
 def X86pextrw  : SDNode<"X86ISD::PEXTRW",
                  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v8i16>,

llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h

   X86_INTRINSIC_DATA(avx512_mask_pmull_d_256, INTR_TYPE_2OP_MASK, ISD::MUL, 0),
   X86_INTRINSIC_DATA(avx512_mask_pmull_d_512, INTR_TYPE_2OP_MASK, ISD::MUL, 0),
   X86_INTRINSIC_DATA(avx512_mask_pmull_q_128, INTR_TYPE_2OP_MASK, ISD::MUL, 0),
   X86_INTRINSIC_DATA(avx512_mask_pmull_q_256, INTR_TYPE_2OP_MASK, ISD::MUL, 0),
   X86_INTRINSIC_DATA(avx512_mask_pmull_q_512, INTR_TYPE_2OP_MASK, ISD::MUL, 0),
   X86_INTRINSIC_DATA(avx512_mask_pmull_w_128, INTR_TYPE_2OP_MASK, ISD::MUL, 0),
   X86_INTRINSIC_DATA(avx512_mask_pmull_w_256, INTR_TYPE_2OP_MASK, ISD::MUL, 0),
   X86_INTRINSIC_DATA(avx512_mask_pmull_w_512, INTR_TYPE_2OP_MASK, ISD::MUL, 0),
+  X86_INTRINSIC_DATA(avx512_mask_pmultishift_qb_128, INTR_TYPE_2OP_MASK,
+                     X86ISD::MULTISHIFT, 0),
+  X86_INTRINSIC_DATA(avx512_mask_pmultishift_qb_256, INTR_TYPE_2OP_MASK,
+                     X86ISD::MULTISHIFT, 0),
+  X86_INTRINSIC_DATA(avx512_mask_pmultishift_qb_512, INTR_TYPE_2OP_MASK, 
+                     X86ISD::MULTISHIFT, 0),
   X86_INTRINSIC_DATA(avx512_mask_pmulu_dq_128, INTR_TYPE_2OP_MASK,
                      X86ISD::PMULUDQ, 0),
   X86_INTRINSIC_DATA(avx512_mask_pmulu_dq_256, INTR_TYPE_2OP_MASK,
                      X86ISD::PMULUDQ, 0),
   X86_INTRINSIC_DATA(avx512_mask_pmulu_dq_512, INTR_TYPE_2OP_MASK,
                      X86ISD::PMULUDQ, 0),
   X86_INTRINSIC_DATA(avx512_mask_por_d_128, INTR_TYPE_2OP_MASK, ISD::OR, 0),
   X86_INTRINSIC_DATA(avx512_mask_por_d_256, INTR_TYPE_2OP_MASK, ISD::OR, 0),

llvm/trunk/test/CodeGen/X86/avx512vbmi-intrinsics.ll

-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx  -mattr=+avx512vbmi --show-mc-encoding| FileCheck %s
-declare <64 x i8> @llvm.x86.avx512.mask.permvar.qi.512(<64 x i8>, <64 x i8>, <64 x i8>, i64)
-
-define <64 x i8>@test_int_x86_avx512_mask_permvar_qi_512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3) {
-; CHECK-LABEL: test_int_x86_avx512_mask_permvar_qi_512:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    kmovq %rdi, %k1 
-; CHECK-NEXT:    vpermb %zmm1, %zmm0, %zmm2 {%k1} 
-; CHECK-NEXT:    vpermb %zmm1, %zmm0, %zmm3 {%k1} {z} 
-; CHECK-NEXT:    vpermb %zmm1, %zmm0, %zmm0 
-; CHECK-NEXT:    vpaddb %zmm3, %zmm2, %zmm1 
-; CHECK-NEXT:    vpaddb %zmm0, %zmm1, %zmm0 
-; CHECK-NEXT:    retq 
- %res = call <64 x i8> @llvm.x86.avx512.mask.permvar.qi.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3)
- %res1 = call <64 x i8> @llvm.x86.avx512.mask.permvar.qi.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> zeroinitializer, i64 %x3)
- %res2 = call <64 x i8> @llvm.x86.avx512.mask.permvar.qi.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 -1)
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx  -mattr=+avx512vbmi --show-mc-encoding| FileCheck %s
+declare <64 x i8> @llvm.x86.avx512.mask.permvar.qi.512(<64 x i8>, <64 x i8>, <64 x i8>, i64)
+
+define <64 x i8>@test_int_x86_avx512_mask_permvar_qi_512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3) {
+; CHECK-LABEL: test_int_x86_avx512_mask_permvar_qi_512:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    kmovq %rdi, %k1 
+; CHECK-NEXT:    vpermb %zmm1, %zmm0, %zmm2 {%k1} 
+; CHECK-NEXT:    vpermb %zmm1, %zmm0, %zmm3 {%k1} {z} 
+; CHECK-NEXT:    vpermb %zmm1, %zmm0, %zmm0 
+; CHECK-NEXT:    vpaddb %zmm3, %zmm2, %zmm1 
+; CHECK-NEXT:    vpaddb %zmm0, %zmm1, %zmm0 
+; CHECK-NEXT:    retq 
+ %res = call <64 x i8> @llvm.x86.avx512.mask.permvar.qi.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3)
+ %res1 = call <64 x i8> @llvm.x86.avx512.mask.permvar.qi.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> zeroinitializer, i64 %x3)
+ %res2 = call <64 x i8> @llvm.x86.avx512.mask.permvar.qi.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 -1)
+ %res3 = add <64 x i8> %res, %res1
+ %res4 = add <64 x i8> %res3, %res2
+ ret <64 x i8> %res4
+}
+
+declare <64 x i8> @llvm.x86.avx512.mask.pmultishift.qb.512(<64 x i8>, <64 x i8>, <64 x i8>, i64)
+
+define <64 x i8>@test_int_x86_avx512_mask_pmultishift_qb_512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3) {
+; CHECK-LABEL: test_int_x86_avx512_mask_pmultishift_qb_512:
+; CHECK: vpmultishiftqb  %zmm1, %zmm0, %zmm2 {%k1}
+; CHECK: vpmultishiftqb  %zmm1, %zmm0, %zmm3 {%k1} {z}
+; CHECK: vpmultishiftqb  %zmm1, %zmm0, %zmm0
+; CHECK: vpaddb  %zmm3, %zmm2, %zmm1
+; CHECK: vpaddb  %zmm0, %zmm1, %zmm0
+  %res = call <64 x i8> @llvm.x86.avx512.mask.pmultishift.qb.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3)
+  %res1 = call <64 x i8> @llvm.x86.avx512.mask.pmultishift.qb.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> zeroinitializer, i64 %x3)
+  %res2 = call <64 x i8> @llvm.x86.avx512.mask.pmultishift.qb.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 -1)
   %res3 = add <64 x i8> %res, %res1
   %res4 = add <64 x i8> %res3, %res2
   ret <64 x i8> %res4
 }
 
 declare <64 x i8> @llvm.x86.avx512.mask.vpermi2var.qi.512(<64 x i8>, <64 x i8>, <64 x i8>, i64)
 
 define <64 x i8>@test_int_x86_avx512_mask_vpermi2var_qi_512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3) {
 ; CHECK-LABEL: test_int_x86_avx512_mask_vpermi2var_qi_512:
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    kmovq %rdi, %k1 

llvm/trunk/test/CodeGen/X86/avx512vbmivl-intrinsics.ll

-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx -mattr=+avx512vl -mattr=+avx512vbmi --show-mc-encoding| FileCheck %s
-declare <16 x i8> @llvm.x86.avx512.mask.permvar.qi.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)
-
-define <16 x i8>@test_int_x86_avx512_mask_permvar_qi_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %x3) {
-; CHECK-LABEL: test_int_x86_avx512_mask_permvar_qi_128:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    kmovw %edi, %k1 
-; CHECK-NEXT:    vpermb %xmm1, %xmm0, %xmm2 {%k1} 
-; CHECK-NEXT:    vpermb %xmm1, %xmm0, %xmm3 {%k1} {z} 
-; CHECK-NEXT:    vpermb %xmm1, %xmm0, %xmm0 
-; CHECK-NEXT:    vpaddb %xmm3, %xmm2, %xmm1 
-; CHECK-NEXT:    vpaddb %xmm0, %xmm1, %xmm0 
-; CHECK-NEXT:    retq 
-  %res = call <16 x i8> @llvm.x86.avx512.mask.permvar.qi.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %x3)
-  %res1 = call <16 x i8> @llvm.x86.avx512.mask.permvar.qi.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> zeroinitializer, i16 %x3)
-  %res2 = call <16 x i8> @llvm.x86.avx512.mask.permvar.qi.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 -1)
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx -mattr=+avx512vl -mattr=+avx512vbmi --show-mc-encoding| FileCheck %s
+declare <16 x i8> @llvm.x86.avx512.mask.permvar.qi.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)
+
+define <16 x i8>@test_int_x86_avx512_mask_permvar_qi_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %x3) {
+; CHECK-LABEL: test_int_x86_avx512_mask_permvar_qi_128:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    kmovw %edi, %k1 
+; CHECK-NEXT:    vpermb %xmm1, %xmm0, %xmm2 {%k1} 
+; CHECK-NEXT:    vpermb %xmm1, %xmm0, %xmm3 {%k1} {z} 
+; CHECK-NEXT:    vpermb %xmm1, %xmm0, %xmm0 
+; CHECK-NEXT:    vpaddb %xmm3, %xmm2, %xmm1 
+; CHECK-NEXT:    vpaddb %xmm0, %xmm1, %xmm0 
+; CHECK-NEXT:    retq 
+  %res = call <16 x i8> @llvm.x86.avx512.mask.permvar.qi.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %x3)
+  %res1 = call <16 x i8> @llvm.x86.avx512.mask.permvar.qi.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> zeroinitializer, i16 %x3)
+  %res2 = call <16 x i8> @llvm.x86.avx512.mask.permvar.qi.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 -1)
+  %res3 = add <16 x i8> %res, %res1
+  %res4 = add <16 x i8> %res3, %res2
+  ret <16 x i8> %res4
+}
+
+declare <32 x i8> @llvm.x86.avx512.mask.permvar.qi.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)
+
+define <32 x i8>@test_int_x86_avx512_mask_permvar_qi_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3) {
+; CHECK-LABEL: test_int_x86_avx512_mask_permvar_qi_256:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    kmovd %edi, %k1 
+; CHECK-NEXT:    vpermb %ymm1, %ymm0, %ymm2 {%k1} 
+; CHECK-NEXT:    vpermb %ymm1, %ymm0, %ymm3 {%k1} {z} 
+; CHECK-NEXT:    vpermb %ymm1, %ymm0, %ymm0 
+; CHECK-NEXT:    vpaddb %ymm3, %ymm2, %ymm1 
+; CHECK-NEXT:    vpaddb %ymm0, %ymm1, %ymm0 
+; CHECK-NEXT:    retq 
+  %res = call <32 x i8> @llvm.x86.avx512.mask.permvar.qi.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3)
+  %res1 = call <32 x i8> @llvm.x86.avx512.mask.permvar.qi.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> zeroinitializer, i32 %x3)
+  %res2 = call <32 x i8> @llvm.x86.avx512.mask.permvar.qi.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 -1)
+  %res3 = add <32 x i8> %res, %res1
+  %res4 = add <32 x i8> %res3, %res2
+  ret <32 x i8> %res4
+}
+
+declare <16 x i8> @llvm.x86.avx512.mask.pmultishift.qb.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)
+
+define <16 x i8>@test_int_x86_avx512_mask_pmultishift_qb_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %x3) {
+; CHECK-LABEL: test_int_x86_avx512_mask_pmultishift_qb_128:
+; CHECK: vpmultishiftqb  %xmm1, %xmm0, %xmm2 {%k1}
+; CHECK: vpmultishiftqb  %xmm1, %xmm0, %xmm3 {%k1} {z}
+; CHECK: vpmultishiftqb  %xmm1, %xmm0, %xmm0
+; CHECK: vpaddb  %xmm3, %xmm2, %xmm1
+; CHECK: vpaddb  %xmm0, %xmm1, %xmm0
+  %res = call <16 x i8> @llvm.x86.avx512.mask.pmultishift.qb.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %x3)
+  %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmultishift.qb.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> zeroinitializer, i16 %x3)
+  %res2 = call <16 x i8> @llvm.x86.avx512.mask.pmultishift.qb.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 -1)
   %res3 = add <16 x i8> %res, %res1
   %res4 = add <16 x i8> %res3, %res2
   ret <16 x i8> %res4
 }
 
-declare <32 x i8> @llvm.x86.avx512.mask.permvar.qi.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)
+declare <32 x i8> @llvm.x86.avx512.mask.pmultishift.qb.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)
 
-define <32 x i8>@test_int_x86_avx512_mask_permvar_qi_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3) {
-; CHECK-LABEL: test_int_x86_avx512_mask_permvar_qi_256:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    kmovd %edi, %k1 
-; CHECK-NEXT:    vpermb %ymm1, %ymm0, %ymm2 {%k1} 
-; CHECK-NEXT:    vpermb %ymm1, %ymm0, %ymm3 {%k1} {z} 
-; CHECK-NEXT:    vpermb %ymm1, %ymm0, %ymm0 
-; CHECK-NEXT:    vpaddb %ymm3, %ymm2, %ymm1 
-; CHECK-NEXT:    vpaddb %ymm0, %ymm1, %ymm0 
-; CHECK-NEXT:    retq 
-  %res = call <32 x i8> @llvm.x86.avx512.mask.permvar.qi.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3)
-  %res1 = call <32 x i8> @llvm.x86.avx512.mask.permvar.qi.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> zeroinitializer, i32 %x3)
-  %res2 = call <32 x i8> @llvm.x86.avx512.mask.permvar.qi.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 -1)
+define <32 x i8>@test_int_x86_avx512_mask_pmultishift_qb_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3) {
+; CHECK-LABEL: test_int_x86_avx512_mask_pmultishift_qb_256:
+; CHECK: vpmultishiftqb  %ymm1, %ymm0, %ymm2 {%k1}
+; CHECK: vpmultishiftqb  %ymm1, %ymm0, %ymm3 {%k1} {z}
+; CHECK: vpmultishiftqb  %ymm1, %ymm0, %ymm0
+; CHECK: vpaddb  %ymm3, %ymm2, %ymm1
+; CHECK: vpaddb  %ymm0, %ymm1, %ymm0
+  %res = call <32 x i8> @llvm.x86.avx512.mask.pmultishift.qb.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3)
+  %res1 = call <32 x i8> @llvm.x86.avx512.mask.pmultishift.qb.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> zeroinitializer, i32 %x3)
+  %res2 = call <32 x i8> @llvm.x86.avx512.mask.pmultishift.qb.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 -1)
   %res3 = add <32 x i8> %res, %res1
   %res4 = add <32 x i8> %res3, %res2
   ret <32 x i8> %res4
 }
 
 declare <16 x i8> @llvm.x86.avx512.mask.vpermi2var.qi.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)
 
 define <16 x i8>@test_int_x86_avx512_mask_vpermi2var_qi_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %x3) {

llvm/trunk/test/MC/X86/avx512vbmi-encoding.s

//CHECK: encoding: [0x62,0x62,0x15,0x40,0x75,0x72,0x80]
      vpermi2b -0x2040(%rdx), %zmm29, %zmm30
 //CHECK: vpermi2b -8256(%rdx), %zmm29, %zmm30
 //CHECK: encoding: [0x62,0x62,0x15,0x40,0x75,0xb2,0xc0,0xdf,0xff,0xff]
 
      vpermi2b 0x1234(%rax,%r14,8), %zmm29, %zmm30
 //CHECK: vpermi2b 4660(%rax,%r14,8), %zmm29, %zmm30
 //CHECK: encoding: [0x62,0x22,0x15,0x40,0x75,0xb4,0xf0,0x34,0x12,0x00,0x00]
 
+  vpmultishiftqb %xmm28, %xmm29, %xmm30
+//CHECK: vpmultishiftqb %xmm28, %xmm29, %xmm30
+//CHECK: encoding: [0x62,0x02,0x95,0x00,0x83,0xf4]
+
+  vpmultishiftqb %xmm28, %xmm29, %xmm30 {%k7}
+//CHECK: vpmultishiftqb %xmm28, %xmm29, %xmm30 {%k7}
+//CHECK: encoding: [0x62,0x02,0x95,0x07,0x83,0xf4]
+
+  vpmultishiftqb %xmm28, %xmm29, %xmm30 {%k7} {z}
+//CHECK: vpmultishiftqb %xmm28, %xmm29, %xmm30 {%k7} {z}
+//CHECK: encoding: [0x62,0x02,0x95,0x87,0x83,0xf4]
+
+  vpmultishiftqb (%rcx), %xmm29, %xmm30
+//CHECK: vpmultishiftqb (%rcx), %xmm29, %xmm30
+//CHECK: encoding: [0x62,0x62,0x95,0x00,0x83,0x31]
+
+  vpmultishiftqb 0x123(%rax,%r14,8), %xmm29, %xmm30
+//CHECK: vpmultishiftqb 291(%rax,%r14,8), %xmm29, %xmm30
+//CHECK: encoding: [0x62,0x22,0x95,0x00,0x83,0xb4,0xf0,0x23,0x01,0x00,0x00]
+
+  vpmultishiftqb (%rcx){1to2}, %xmm29, %xmm30
+//CHECK: vpmultishiftqb (%rcx){1to2}, %xmm29, %xmm30
+
+//CHECK: encoding: [0x62,0x62,0x95,0x10,0x83,0x31]
+
+  vpmultishiftqb 0x7f0(%rdx), %xmm29, %xmm30
+//CHECK: vpmultishiftqb 2032(%rdx), %xmm29, %xmm30
+//CHECK: encoding: [0x62,0x62,0x95,0x00,0x83,0x72,0x7f]
+
+  vpmultishiftqb 0x800(%rdx), %xmm29, %xmm30
+//CHECK: vpmultishiftqb 2048(%rdx), %xmm29, %xmm30
+//CHECK: encoding: [0x62,0x62,0x95,0x00,0x83,0xb2,0x00,0x08,0x00,0x00]
+
+  vpmultishiftqb -0x800(%rdx), %xmm29, %xmm30
+//CHECK: vpmultishiftqb -2048(%rdx), %xmm29, %xmm30
+//CHECK: encoding: [0x62,0x62,0x95,0x00,0x83,0x72,0x80]
+
+  vpmultishiftqb -0x810(%rdx), %xmm29, %xmm30
+//CHECK: vpmultishiftqb -2064(%rdx), %xmm29, %xmm30
+//CHECK: encoding: [0x62,0x62,0x95,0x00,0x83,0xb2,0xf0,0xf7,0xff,0xff]
+
+  vpmultishiftqb 0x3f8(%rdx){1to2}, %xmm29, %xmm30
+//CHECK: vpmultishiftqb 1016(%rdx){1to2}, %xmm29, %xmm30
+//CHECK: encoding: [0x62,0x62,0x95,0x10,0x83,0x72,0x7f]
+
+  vpmultishiftqb 0x400(%rdx){1to2}, %xmm29, %xmm30
+//CHECK: vpmultishiftqb 1024(%rdx){1to2}, %xmm29, %xmm30
+//CHECK: encoding: [0x62,0x62,0x95,0x10,0x83,0xb2,0x00,0x04,0x00,0x00]
+
+  vpmultishiftqb -0x400(%rdx){1to2}, %xmm29, %xmm30
+//CHECK: vpmultishiftqb -1024(%rdx){1to2}, %xmm29, %xmm30
+//CHECK: encoding: [0x62,0x62,0x95,0x10,0x83,0x72,0x80]
+
+  vpmultishiftqb -0x408(%rdx){1to2}, %xmm29, %xmm30
+//CHECK: vpmultishiftqb -1032(%rdx){1to2}, %xmm29, %xmm30
+//CHECK: encoding: [0x62,0x62,0x95,0x10,0x83,0xb2,0xf8,0xfb,0xff,0xff]
+
+  vpmultishiftqb %ymm28, %ymm29, %ymm30
+//CHECK: vpmultishiftqb %ymm28, %ymm29, %ymm30
+//CHECK: encoding: [0x62,0x02,0x95,0x20,0x83,0xf4]
+
+  vpmultishiftqb %ymm28, %ymm29, %ymm30 {%k7}
+//CHECK: vpmultishiftqb %ymm28, %ymm29, %ymm30 {%k7}
+//CHECK: encoding: [0x62,0x02,0x95,0x27,0x83,0xf4]
+
+  vpmultishiftqb %ymm28, %ymm29, %ymm30 {%k7} {z}
+//CHECK: vpmultishiftqb %ymm28, %ymm29, %ymm30 {%k7} {z}
+//CHECK: encoding: [0x62,0x02,0x95,0xa7,0x83,0xf4]
+
+  vpmultishiftqb (%rcx), %ymm29, %ymm30
+//CHECK: vpmultishiftqb (%rcx), %ymm29, %ymm30
+//CHECK: encoding: [0x62,0x62,0x95,0x20,0x83,0x31]
+
+  vpmultishiftqb 0x123(%rax,%r14,8), %ymm29, %ymm30
+//CHECK: vpmultishiftqb 291(%rax,%r14,8), %ymm29, %ymm30
+//CHECK: encoding: [0x62,0x22,0x95,0x20,0x83,0xb4,0xf0,0x23,0x01,0x00,0x00]
+
+  vpmultishiftqb (%rcx){1to4}, %ymm29, %ymm30
+//CHECK: vpmultishiftqb (%rcx){1to4}, %ymm29, %ymm30
+//CHECK: encoding: [0x62,0x62,0x95,0x30,0x83,0x31]
+
+  vpmultishiftqb 0xfe0(%rdx), %ymm29, %ymm30
+//CHECK: vpmultishiftqb 4064(%rdx), %ymm29, %ymm30
+//CHECK: encoding: [0x62,0x62,0x95,0x20,0x83,0x72,0x7f]
+
+  vpmultishiftqb 0x1000(%rdx), %ymm29, %ymm30
+//CHECK: vpmultishiftqb 4096(%rdx), %ymm29, %ymm30
+//CHECK: encoding: [0x62,0x62,0x95,0x20,0x83,0xb2,0x00,0x10,0x00,0x00]
+
+  vpmultishiftqb -0x1000(%rdx), %ymm29, %ymm30
+//CHECK: vpmultishiftqb -4096(%rdx), %ymm29, %ymm30
+//CHECK: encoding: [0x62,0x62,0x95,0x20,0x83,0x72,0x80]
+
+  vpmultishiftqb -0x1020(%rdx), %ymm29, %ymm30
+//CHECK: vpmultishiftqb -4128(%rdx), %ymm29, %ymm30
+//CHECK: encoding: [0x62,0x62,0x95,0x20,0x83,0xb2,0xe0,0xef,0xff,0xff]
+
+  vpmultishiftqb 0x3f8(%rdx){1to4}, %ymm29, %ymm30
+//CHECK: vpmultishiftqb 1016(%rdx){1to4}, %ymm29, %ymm30
+//CHECK: encoding: [0x62,0x62,0x95,0x30,0x83,0x72,0x7f]
+
+  vpmultishiftqb 0x400(%rdx){1to4}, %ymm29, %ymm30
+//CHECK: vpmultishiftqb 1024(%rdx){1to4}, %ymm29, %ymm30
+//CHECK: encoding: [0x62,0x62,0x95,0x30,0x83,0xb2,0x00,0x04,0x00,0x00]
+
+  vpmultishiftqb -0x400(%rdx){1to4}, %ymm29, %ymm30
+//CHECK: vpmultishiftqb -1024(%rdx){1to4}, %ymm29, %ymm30
+//CHECK: encoding: [0x62,0x62,0x95,0x30,0x83,0x72,0x80]
+
+  vpmultishiftqb -0x408(%rdx){1to4}, %ymm29, %ymm30
+//CHECK: vpmultishiftqb -1032(%rdx){1to4}, %ymm29, %ymm30
+//CHECK: encoding: [0x62,0x62,0x95,0x30,0x83,0xb2,0xf8,0xfb,0xff,0xff]
+
+  vpmultishiftqb 0x1234(%rax,%r14,8), %xmm29, %xmm30
+//CHECK: vpmultishiftqb 4660(%rax,%r14,8), %xmm29, %xmm30
+//CHECK: encoding: [0x62,0x22,0x95,0x00,0x83,0xb4,0xf0,0x34,0x12,0x00,0x00]
+
+  vpmultishiftqb 0x1234(%rax,%r14,8), %ymm29, %ymm30
+//CHECK: vpmultishiftqb 4660(%rax,%r14,8), %ymm29, %ymm30
+//CHECK: encoding: [0x62,0x22,0x95,0x20,0x83,0xb4,0xf0,0x34,0x12,0x00,0x00]
+
+  vpmultishiftqb %zmm28, %zmm29, %zmm30
+//CHECK: vpmultishiftqb %zmm28, %zmm29, %zmm30
+//CHECK: encoding: [0x62,0x02,0x95,0x40,0x83,0xf4]
+
+  vpmultishiftqb %zmm28, %zmm29, %zmm30 {%k7}
+//CHECK: vpmultishiftqb %zmm28, %zmm29, %zmm30 {%k7}
+//CHECK: encoding: [0x62,0x02,0x95,0x47,0x83,0xf4]
+
+  vpmultishiftqb %zmm28, %zmm29, %zmm30 {%k7} {z}
+//CHECK: vpmultishiftqb %zmm28, %zmm29, %zmm30 {%k7} {z}
+//CHECK: encoding: [0x62,0x02,0x95,0xc7,0x83,0xf4]
+
+  vpmultishiftqb (%rcx), %zmm29, %zmm30
+//CHECK: vpmultishiftqb (%rcx), %zmm29, %zmm30
+//CHECK: encoding: [0x62,0x62,0x95,0x40,0x83,0x31]
+
+  vpmultishiftqb 0x123(%rax,%r14,8), %zmm29, %zmm30
+//CHECK: vpmultishiftqb 291(%rax,%r14,8), %zmm29, %zmm30
+//CHECK: encoding: [0x62,0x22,0x95,0x40,0x83,0xb4,0xf0,0x23,0x01,0x00,0x00]
+
+  vpmultishiftqb (%rcx){1to8}, %zmm29, %zmm30
+//CHECK: vpmultishiftqb (%rcx){1to8}, %zmm29, %zmm30
+//CHECK: encoding: [0x62,0x62,0x95,0x50,0x83,0x31]
+
+  vpmultishiftqb 0x1fc0(%rdx), %zmm29, %zmm30
+//CHECK: vpmultishiftqb 8128(%rdx), %zmm29, %zmm30
+//CHECK: encoding: [0x62,0x62,0x95,0x40,0x83,0x72,0x7f]
+
+  vpmultishiftqb 0x2000(%rdx), %zmm29, %zmm30
+//CHECK: vpmultishiftqb 8192(%rdx), %zmm29, %zmm30
+//CHECK: encoding: [0x62,0x62,0x95,0x40,0x83,0xb2,0x00,0x20,0x00,0x00]
+
+  vpmultishiftqb -0x2000(%rdx), %zmm29, %zmm30
+//CHECK: vpmultishiftqb -8192(%rdx), %zmm29, %zmm30
+//CHECK: encoding: [0x62,0x62,0x95,0x40,0x83,0x72,0x80]
+
+  vpmultishiftqb -0x2040(%rdx), %zmm29, %zmm30
+//CHECK: vpmultishiftqb -8256(%rdx), %zmm29, %zmm30
+//CHECK: encoding: [0x62,0x62,0x95,0x40,0x83,0xb2,0xc0,0xdf,0xff,0xff]
+
+  vpmultishiftqb 0x3f8(%rdx){1to8}, %zmm29, %zmm30
+//CHECK: vpmultishiftqb 1016(%rdx){1to8}, %zmm29, %zmm30
+//CHECK: encoding: [0x62,0x62,0x95,0x50,0x83,0x72,0x7f]
+
+  vpmultishiftqb 0x400(%rdx){1to8}, %zmm29, %zmm30
+//CHECK: vpmultishiftqb 1024(%rdx){1to8}, %zmm29, %zmm30
+//CHECK: encoding: [0x62,0x62,0x95,0x50,0x83,0xb2,0x00,0x04,0x00,0x00]
+
+  vpmultishiftqb -0x400(%rdx){1to8}, %zmm29, %zmm30
+//CHECK: vpmultishiftqb -1024(%rdx){1to8}, %zmm29, %zmm30
+//CHECK: encoding: [0x62,0x62,0x95,0x50,0x83,0x72,0x80]
+
+  vpmultishiftqb -0x408(%rdx){1to8}, %zmm29, %zmm30
+//CHECK: vpmultishiftqb -1032(%rdx){1to8}, %zmm29, %zmm30
+//CHECK: encoding: [0x62,0x62,0x95,0x50,0x83,0xb2,0xf8,0xfb,0xff,0xff]
+
+  vpmultishiftqb 0x1234(%rax,%r14,8), %zmm29, %zmm30
+//CHECK: vpmultishiftqb 4660(%rax,%r14,8), %zmm29, %zmm30
+//CHECK: encoding: [0x62,0x22,0x95,0x40,0x83,0xb4,0xf0,0x34,0x12,0x00,0x00]
+