[mips] Absolute value macro expansion

[obucina]

Summary

Add support for absolute value macro expansion

[dsanders]

LGTM with a couple changes

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

3537 ↗

(On Diff #45276)

This should be a nop when both registers are the same. Assembling

a: abs $2, $3
b: abs $2, $2
c:

gives:

00000000 <a>:
   0:	04610002 	bgez	v1,c <b>
   4:	00601021 	move	v0,v1
   8:	00031022 	neg	v0,v1

0000000c <b>:
   c:	04410002 	bgez	v0,18 <c>
  10:	00000000 	nop
  14:	00021022 	neg	v0,v0

00000018 <c>:
	...

3539 ↗

(On Diff #45276)

This nop should be deleted. Assuming you tested this the same way I did (by assembling then disassembling) then the nop you saw was padding to round off the section size.

lib/Target/Mips/MipsInstrInfo.td

1811–1812 ↗

(On Diff #45276)

Just a spelling nit: Could you make it obvious that it's a macro in the name? I'm thinking ABSMacro or ABSPseudo.

We ought to tidy up the existing names at some point but that's for another patch.

test/MC/Mips/macro-abs.s

5–9 ↗

(On Diff #45276)

Could you test 'abs $4, $4' too?

[obucina]

New diff contains suggested changes

[dsanders]

LGTM

llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

bool expandRotation(MCInst &Inst, SMLoc IDLoc,
                       SmallVectorImpl<MCInst> &Instructions);
   bool expandRotationImm(MCInst &Inst, SMLoc IDLoc,
                          SmallVectorImpl<MCInst> &Instructions);
   bool expandDRotation(MCInst &Inst, SMLoc IDLoc,
                        SmallVectorImpl<MCInst> &Instructions);
   bool expandDRotationImm(MCInst &Inst, SMLoc IDLoc,
                           SmallVectorImpl<MCInst> &Instructions);
 
+  bool expandAbs(MCInst &Inst, SMLoc IDLoc,
+                 SmallVectorImpl<MCInst> &Instructions);
+
   void createNop(bool hasShortDelaySlot, SMLoc IDLoc,
                  SmallVectorImpl<MCInst> &Instructions);
 
   void createAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg,
                   bool Is64Bit, SmallVectorImpl<MCInst> &Instructions);
 
   void createCpRestoreMemOp(bool IsLoad, int StackOffset, SMLoc IDLoc,
                             SmallVectorImpl<MCInst> &Instructions);
MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc,
   case Mips::DROL:
   case Mips::DROR:
     return expandDRotation(Inst, IDLoc, Instructions) ? MER_Fail
                                                       : MER_Success;
   case Mips::DROLImm:
   case Mips::DRORImm:
     return expandDRotationImm(Inst, IDLoc, Instructions) ? MER_Fail
                                                          : MER_Success;
+  case Mips::ABSMacro:
+    return expandAbs(Inst, IDLoc, Instructions) ? MER_Fail
+                                                : MER_Success;
   }
 }
 
 bool MipsAsmParser::expandJalWithRegs(MCInst &Inst, SMLoc IDLoc,
                                       SmallVectorImpl<MCInst> &Instructions) {
   // Create a JALR instruction which is going to replace the pseudo-JAL.
   MCInst JalrInst;
   JalrInst.setLoc(IDLoc);
if (hasMips64()) {
     emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), Instructions);
 
     return false;
   }
 
   return true;
 }
 
+bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc,
+                              SmallVectorImpl<MCInst> &Instructions) {
+
+  unsigned FirstRegOp = Inst.getOperand(0).getReg();
+  unsigned SecondRegOp = Inst.getOperand(1).getReg();
+
+  emitRI(Mips::BGEZ, SecondRegOp, 8, IDLoc, Instructions);
+  if (FirstRegOp != SecondRegOp)
+    emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, Instructions);
+  else
+    createNop(false, IDLoc, Instructions);
+  emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, Instructions);
+
+  return false;
+}
+
 void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc,
                               SmallVectorImpl<MCInst> &Instructions) {
   if (hasShortDelaySlot)
     emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, Instructions);
   else
     emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, Instructions);
 }
 

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

 def DRORImm : MipsAsmPseudoInst<(outs),
                                 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
                                 "dror\t$rs, $rt, $imm">, ISA_MIPS64;
 def : MipsInstAlias<"dror $rd, $rs",
                     (DROR GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>, ISA_MIPS64;
 def : MipsInstAlias<"dror $rd, $imm",
                     (DRORImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>, ISA_MIPS64;
 
+def ABSMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
+                                 "abs\t$rd, $rs">;
+
 //===----------------------------------------------------------------------===//
 // Instruction aliases
 //===----------------------------------------------------------------------===//
 def : MipsInstAlias<"move $dst, $src",
                     (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
       GPR_32 {
   let AdditionalPredicates = [NotInMicroMips];
 }

llvm/trunk/test/MC/Mips/macro-abs.s

+# RUN: llvm-mc -triple mips-unknown-linux -show-encoding %s | FileCheck %s
+
+.text
+# CHECK:    .text
+  abs $4, $4
+# CHECK:    bgez    $4, 8       # encoding: [0x04,0x81,0x00,0x02]
+# CHECK:    nop                 # encoding: [0x00,0x00,0x00,0x00]
+# CHECK:    neg     $4, $4      # encoding: [0x00,0x04,0x20,0x22]
+  abs $4, $5
+# CHECK:    bgez    $5, 8       # encoding: [0x04,0xa1,0x00,0x02]
+# CHECK:    move    $4, $5      # encoding: [0x00,0xa0,0x20,0x21]
+# CHECK:    neg     $4, $5      # encoding: [0x00,0x05,0x20,0x22]