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Differential D16287

AVX512 : change v8i1 bitconvert GR8 pattern.
ClosedPublic

Authored by igorb on Jan 18 2016, 3:17 AM.

Details

Reviewers
delena
Commits
rGdd6522c65318: AVX512 : Change v8i1 bitconvert GR8 pattern, remove unnecessary movzbl…
rL258045: AVX512 : Change v8i1 bitconvert GR8 pattern, remove unnecessary movzbl…
Summary

AVX512 : Change v8i1 bitconvert GR8 pattern, remove unnecessary movzbl instruction.
code example , previous implementation.

movzbl  %dil, %eax
kmovw  %eax, %k0

new code

kmovw  %edi, %k0

Diff Detail

Repository
rL LLVM

Event Timeline

igorb updated this revision to Diff 45158.Jan 18 2016, 3:17 AM
igorb retitled this revision from to AVX512 : change v8i1 bitconvert GR8 pattern..
igorb updated this object.
igorb added a reviewer: delena.
igorb set the repository for this revision to rL LLVM.
igorb added a subscriber: llvm-commits.
delena accepted this revision.Jan 18 2016, 3:50 AM
delena edited edge metadata.

LGTM

This revision is now accepted and ready to land.Jan 18 2016, 3:50 AM
Closed by commit rL258045: AVX512 : Change v8i1 bitconvert GR8 pattern, remove unnecessary movzbl… (authored by ibreger). · Explain WhyJan 18 2016, 4:06 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

Diff 45165

llvm/trunk/lib/Target/X86/X86InstrAVX512.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,166 Lines • ▼ Show 20 Linesdef : Pat<(v64i1 (scalar_to_vector VK1:$src)),
(COPY_TO_REGCLASS VK1:$src, VK64)>; (COPY_TO_REGCLASS VK1:$src, VK64)>;
// With AVX-512 only, 8-bit mask is promoted to 16-bit mask. // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
let Predicates = [HasAVX512, NoDQI] in { let Predicates = [HasAVX512, NoDQI] in {
// GR from/to 8-bit mask without native support // GR from/to 8-bit mask without native support
def : Pat<(v8i1 (bitconvert (i8 GR8:$src))), def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
(COPY_TO_REGCLASS (COPY_TO_REGCLASS
(KMOVWkr (MOVZX32rr8 GR8 :$src)), VK8)>; (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)), VK8)>;
def : Pat<(i8 (bitconvert (v8i1 VK8:$src))), def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
(EXTRACT_SUBREG (EXTRACT_SUBREG
(KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)), (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
sub_8bit)>; sub_8bit)>;
} }
let Predicates = [HasAVX512] in { let Predicates = [HasAVX512] in {
def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))), def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
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llvm/trunk/test/CodeGen/X86/avx512-calling-conv.ll

Show First 20 Lines • Show All 271 Lines • ▼ Show 20 Lines
; KNL-NEXT: Ltmp3: ; KNL-NEXT: Ltmp3:
; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0 ; KNL-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
; KNL-NEXT: vpmovdw %zmm0, %ymm0 ; KNL-NEXT: vpmovdw %zmm0, %ymm0
; KNL-NEXT: callq _func8xi1 ; KNL-NEXT: callq _func8xi1
; KNL-NEXT: vpmovsxwq %xmm0, %zmm0 ; KNL-NEXT: vpmovsxwq %xmm0, %zmm0
; KNL-NEXT: vpsllq $63, %zmm0, %zmm0 ; KNL-NEXT: vpsllq $63, %zmm0, %zmm0
; KNL-NEXT: movb $85, %al ; KNL-NEXT: movb $85, %al
; KNL-NEXT: movzbl %al, %eax
; KNL-NEXT: kmovw %eax, %k1 ; KNL-NEXT: kmovw %eax, %k1
; KNL-NEXT: vptestmq %zmm0, %zmm0, %k1 {%k1} ; KNL-NEXT: vptestmq %zmm0, %zmm0, %k1 {%k1}
; KNL-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z} ; KNL-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z}
; KNL-NEXT: vpmovqw %zmm0, %xmm0 ; KNL-NEXT: vpmovqw %zmm0, %xmm0
; KNL-NEXT: popq %rax ; KNL-NEXT: popq %rax
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test7a: ; SKX-LABEL: test7a:
Show All 19 Lines
; KNL_X32-NEXT: Ltmp3: ; KNL_X32-NEXT: Ltmp3:
; KNL_X32-NEXT: .cfi_def_cfa_offset 16 ; KNL_X32-NEXT: .cfi_def_cfa_offset 16
; KNL_X32-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0 ; KNL_X32-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
; KNL_X32-NEXT: vpmovdw %zmm0, %ymm0 ; KNL_X32-NEXT: vpmovdw %zmm0, %ymm0
; KNL_X32-NEXT: calll L_func8xi1$stub ; KNL_X32-NEXT: calll L_func8xi1$stub
; KNL_X32-NEXT: vpmovsxwq %xmm0, %zmm0 ; KNL_X32-NEXT: vpmovsxwq %xmm0, %zmm0
; KNL_X32-NEXT: vpsllvq LCPI7_0, %zmm0, %zmm0 ; KNL_X32-NEXT: vpsllvq LCPI7_0, %zmm0, %zmm0
; KNL_X32-NEXT: movb $85, %al ; KNL_X32-NEXT: movb $85, %al
; KNL_X32-NEXT: movzbl %al, %eax
; KNL_X32-NEXT: kmovw %eax, %k1 ; KNL_X32-NEXT: kmovw %eax, %k1
; KNL_X32-NEXT: vptestmq %zmm0, %zmm0, %k1 {%k1} ; KNL_X32-NEXT: vptestmq %zmm0, %zmm0, %k1 {%k1}
; KNL_X32-NEXT: vpbroadcastd LCPI7_1, %zmm0 ; KNL_X32-NEXT: vpbroadcastd LCPI7_1, %zmm0
; KNL_X32-NEXT: vmovdqu64 %zmm0, %zmm0 {%k1} {z} ; KNL_X32-NEXT: vmovdqu64 %zmm0, %zmm0 {%k1} {z}
; KNL_X32-NEXT: vpmovqw %zmm0, %xmm0 ; KNL_X32-NEXT: vpmovqw %zmm0, %xmm0
; KNL_X32-NEXT: addl $12, %esp ; KNL_X32-NEXT: addl $12, %esp
; KNL_X32-NEXT: retl ; KNL_X32-NEXT: retl
%cmpRes = icmp sgt <8 x i32>%a, %b %cmpRes = icmp sgt <8 x i32>%a, %b
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llvm/trunk/test/CodeGen/X86/avx512-ext.ll

Show First 20 Lines • Show All 1,306 Lines • ▼ Show 20 Lines; ALL-NEXT: retq
%a = bitcast i16 %b to <16 x i1> %a = bitcast i16 %b to <16 x i1>
%c = zext <16 x i1> %a to <16 x i32> %c = zext <16 x i1> %a to <16 x i32>
ret <16 x i32> %c ret <16 x i32> %c
} }
define <8 x i64> @zext_8i1_to_8xi64(i8 %b) { define <8 x i64> @zext_8i1_to_8xi64(i8 %b) {
; KNL-LABEL: zext_8i1_to_8xi64: ; KNL-LABEL: zext_8i1_to_8xi64:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: movzbl %dil, %eax ; KNL-NEXT: kmovw %edi, %k1
; KNL-NEXT: kmovw %eax, %k1
; KNL-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z} ; KNL-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z}
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: zext_8i1_to_8xi64: ; SKX-LABEL: zext_8i1_to_8xi64:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: kmovb %edi, %k1 ; SKX-NEXT: kmovb %edi, %k1
; SKX-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z} ; SKX-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z}
; SKX-NEXT: retq ; SKX-NEXT: retq
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llvm/trunk/test/CodeGen/X86/avx512-fma-intrinsics.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f --show-mc-encoding | FileCheck %s ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f | FileCheck %s
declare <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) declare <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32)
declare <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) declare <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32)
define <16 x float> @test_x86_vfnmadd_ps_z(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) { define <16 x float> @test_x86_vfnmadd_ps_z(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
; CHECK-LABEL: test_x86_vfnmadd_ps_z ; CHECK-LABEL: test_x86_vfnmadd_ps_z:
; CHECK: vfnmadd213ps %zmm ; CHECK: ## BB#0:
; CHECK-NEXT: vfnmadd213ps %zmm2, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = call <16 x float> @llvm.x86.avx512.mask.vfnmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 4) nounwind %res = call <16 x float> @llvm.x86.avx512.mask.vfnmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 4) nounwind
ret <16 x float> %res ret <16 x float> %res
} }
declare <16 x float> @llvm.x86.avx512.mask.vfnmadd.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) nounwind readnone declare <16 x float> @llvm.x86.avx512.mask.vfnmadd.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) nounwind readnone
define <16 x float> @test_mask_vfnmadd_ps(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) { define <16 x float> @test_mask_vfnmadd_ps(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) {
; CHECK-LABEL: test_mask_vfnmadd_ps ; CHECK-LABEL: test_mask_vfnmadd_ps:
; CHECK: vfnmadd213ps %zmm ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vfnmadd213ps %zmm2, %zmm1, %zmm0 {%k1}
; CHECK-NEXT: retq
%res = call <16 x float> @llvm.x86.avx512.mask.vfnmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 4) nounwind %res = call <16 x float> @llvm.x86.avx512.mask.vfnmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 4) nounwind
ret <16 x float> %res ret <16 x float> %res
} }
define <8 x double> @test_x86_vfnmadd_pd_z(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { define <8 x double> @test_x86_vfnmadd_pd_z(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
; CHECK-LABEL: test_x86_vfnmadd_pd_z ; CHECK-LABEL: test_x86_vfnmadd_pd_z:
; CHECK: vfnmadd213pd %zmm ; CHECK: ## BB#0:
; CHECK-NEXT: vfnmadd213pd %zmm2, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfnmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 4) nounwind %res = call <8 x double> @llvm.x86.avx512.mask.vfnmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 4) nounwind
ret <8 x double> %res ret <8 x double> %res
} }
declare <8 x double> @llvm.x86.avx512.mask.vfnmadd.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) nounwind readnone declare <8 x double> @llvm.x86.avx512.mask.vfnmadd.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) nounwind readnone
define <8 x double> @test_mask_vfnmadd_pd(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { define <8 x double> @test_mask_vfnmadd_pd(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_vfnmadd_pd ; CHECK-LABEL: test_mask_vfnmadd_pd:
; CHECK: vfnmadd213pd %zmm ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vfnmadd213pd %zmm2, %zmm1, %zmm0 {%k1}
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfnmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 4) nounwind %res = call <8 x double> @llvm.x86.avx512.mask.vfnmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 4) nounwind
ret <8 x double> %res ret <8 x double> %res
} }
define <16 x float> @test_x86_vfnmsubps_z(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) { define <16 x float> @test_x86_vfnmsubps_z(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
; CHECK-LABEL: test_x86_vfnmsubps_z ; CHECK-LABEL: test_x86_vfnmsubps_z:
; CHECK: vfnmsub213ps %zmm ; CHECK: ## BB#0:
; CHECK-NEXT: vfnmsub213ps %zmm2, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = call <16 x float> @llvm.x86.avx512.mask.vfnmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 4) nounwind %res = call <16 x float> @llvm.x86.avx512.mask.vfnmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 4) nounwind
ret <16 x float> %res ret <16 x float> %res
} }
declare <16 x float> @llvm.x86.avx512.mask.vfnmsub.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) nounwind readnone declare <16 x float> @llvm.x86.avx512.mask.vfnmsub.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) nounwind readnone
define <16 x float> @test_mask_vfnmsub_ps(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) { define <16 x float> @test_mask_vfnmsub_ps(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) {
; CHECK-LABEL: test_mask_vfnmsub_ps ; CHECK-LABEL: test_mask_vfnmsub_ps:
; CHECK: vfnmsub213ps %zmm ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vfnmsub213ps %zmm2, %zmm1, %zmm0 {%k1}
; CHECK-NEXT: retq
%res = call <16 x float> @llvm.x86.avx512.mask.vfnmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 4) nounwind %res = call <16 x float> @llvm.x86.avx512.mask.vfnmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 4) nounwind
ret <16 x float> %res ret <16 x float> %res
} }
define <8 x double> @test_x86_vfnmsubpd_z(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { define <8 x double> @test_x86_vfnmsubpd_z(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
; CHECK-LABEL: test_x86_vfnmsubpd_z ; CHECK-LABEL: test_x86_vfnmsubpd_z:
; CHECK: vfnmsub213pd %zmm ; CHECK: ## BB#0:
; CHECK-NEXT: vfnmsub213pd %zmm2, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 4) nounwind %res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 4) nounwind
ret <8 x double> %res ret <8 x double> %res
} }
declare <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) nounwind readnone declare <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) nounwind readnone
define <8 x double> @test_mask_vfnmsub_pd(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { define <8 x double> @test_mask_vfnmsub_pd(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_vfnmsub_pd ; CHECK-LABEL: test_mask_vfnmsub_pd:
; CHECK: vfnmsub213pd %zmm ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vfnmsub213pd %zmm2, %zmm1, %zmm0 {%k1}
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 4) nounwind %res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 4) nounwind
ret <8 x double> %res ret <8 x double> %res
} }
define <16 x float> @test_x86_vfmaddsubps_z(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) { define <16 x float> @test_x86_vfmaddsubps_z(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
; CHECK-LABEL: test_x86_vfmaddsubps_z ; CHECK-LABEL: test_x86_vfmaddsubps_z:
; CHECK: vfmaddsub213ps %zmm ; CHECK: ## BB#0:
; CHECK-NEXT: vfmaddsub213ps %zmm2, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = call <16 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 4) nounwind %res = call <16 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 4) nounwind
ret <16 x float> %res ret <16 x float> %res
} }
define <16 x float> @test_mask_fmaddsub_ps(<16 x float> %a, <16 x float> %b, <16 x float> %c, i16 %mask) { define <16 x float> @test_mask_fmaddsub_ps(<16 x float> %a, <16 x float> %b, <16 x float> %c, i16 %mask) {
; CHECK-LABEL: test_mask_fmaddsub_ps: ; CHECK-LABEL: test_mask_fmaddsub_ps:
; CHECK: vfmaddsub213ps %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x49,0xa6,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vfmaddsub213ps %zmm2, %zmm1, %zmm0 {%k1}
; CHECK-NEXT: retq
%res = call <16 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> %c, i16 %mask, i32 4) %res = call <16 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> %c, i16 %mask, i32 4)
ret <16 x float> %res ret <16 x float> %res
} }
declare <16 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) nounwind readnone declare <16 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) nounwind readnone
define <8 x double> @test_x86_vfmaddsubpd_z(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { define <8 x double> @test_x86_vfmaddsubpd_z(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
; CHECK-LABEL: test_x86_vfmaddsubpd_z ; CHECK-LABEL: test_x86_vfmaddsubpd_z:
; CHECK: vfmaddsub213pd %zmm ; CHECK: ## BB#0:
; CHECK-NEXT: vfmaddsub213pd %zmm2, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 4) nounwind %res = call <8 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 4) nounwind
ret <8 x double> %res ret <8 x double> %res
} }
declare <8 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) nounwind readnone declare <8 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) nounwind readnone
define <8 x double> @test_mask_vfmaddsub_pd(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { define <8 x double> @test_mask_vfmaddsub_pd(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_vfmaddsub_pd ; CHECK-LABEL: test_mask_vfmaddsub_pd:
; CHECK: vfmaddsub213pd %zmm ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vfmaddsub213pd %zmm2, %zmm1, %zmm0 {%k1}
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 4) nounwind %res = call <8 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 4) nounwind
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double>@test_int_x86_avx512_mask_vfmaddsub_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){ define <8 x double>@test_int_x86_avx512_mask_vfmaddsub_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){
; CHECK-LABEL: test_int_x86_avx512_mask_vfmaddsub_pd_512: ; CHECK-LABEL: test_int_x86_avx512_mask_vfmaddsub_pd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfmaddsub213pd %zmm2, %zmm1, %zmm3 {%k1} ; CHECK-NEXT: vfmaddsub213pd %zmm2, %zmm1, %zmm3 {%k1}
; CHECK-NEXT: vfmaddsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0 ; CHECK-NEXT: vfmaddsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0
; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4) %res = call <8 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4)
%res1 = call <8 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0) %res1 = call <8 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0)
%res2 = fadd <8 x double> %res, %res1 %res2 = fadd <8 x double> %res, %res1
ret <8 x double> %res2 ret <8 x double> %res2
} }
declare <8 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) declare <8 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32)
define <8 x double>@test_int_x86_avx512_mask3_vfmaddsub_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){ define <8 x double>@test_int_x86_avx512_mask3_vfmaddsub_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){
; CHECK-LABEL: test_int_x86_avx512_mask3_vfmaddsub_pd_512: ; CHECK-LABEL: test_int_x86_avx512_mask3_vfmaddsub_pd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm2, %zmm3 ; CHECK-NEXT: vmovaps %zmm2, %zmm3
; CHECK-NEXT: vfmaddsub231pd %zmm1, %zmm0, %zmm3 {%k1} ; CHECK-NEXT: vfmaddsub231pd %zmm1, %zmm0, %zmm3 {%k1}
; CHECK-NEXT: vfmaddsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0 ; CHECK-NEXT: vfmaddsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0
; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4) %res = call <8 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4)
%res1 = call <8 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0) %res1 = call <8 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0)
%res2 = fadd <8 x double> %res, %res1 %res2 = fadd <8 x double> %res, %res1
ret <8 x double> %res2 ret <8 x double> %res2
} }
declare <8 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) declare <8 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32)
define <8 x double>@test_int_x86_avx512_maskz_vfmaddsub_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){ define <8 x double>@test_int_x86_avx512_maskz_vfmaddsub_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){
; CHECK-LABEL: test_int_x86_avx512_maskz_vfmaddsub_pd_512: ; CHECK-LABEL: test_int_x86_avx512_maskz_vfmaddsub_pd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfmaddsub213pd %zmm2, %zmm1, %zmm3 {%k1} {z} ; CHECK-NEXT: vfmaddsub213pd %zmm2, %zmm1, %zmm3 {%k1} {z}
; CHECK-NEXT: vfmaddsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0 ; CHECK-NEXT: vfmaddsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0
; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4) %res = call <8 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4)
%res1 = call <8 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0) %res1 = call <8 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0)
%res2 = fadd <8 x double> %res, %res1 %res2 = fadd <8 x double> %res, %res1
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
ret <16 x float> %res2 ret <16 x float> %res2
} }
declare <8 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) declare <8 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32)
define <8 x double>@test_int_x86_avx512_mask3_vfmsubadd_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){ define <8 x double>@test_int_x86_avx512_mask3_vfmsubadd_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){
; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsubadd_pd_512: ; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsubadd_pd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm2, %zmm3 ; CHECK-NEXT: vmovaps %zmm2, %zmm3
; CHECK-NEXT: vfmsubadd231pd %zmm1, %zmm0, %zmm3 {%k1} ; CHECK-NEXT: vfmsubadd231pd %zmm1, %zmm0, %zmm3 {%k1}
; CHECK-NEXT: vfmsubadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0 ; CHECK-NEXT: vfmsubadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0
; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4) %res = call <8 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4)
%res1 = call <8 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0) %res1 = call <8 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0)
%res2 = fadd <8 x double> %res, %res1 %res2 = fadd <8 x double> %res, %res1
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; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <16 x float> @llvm.x86.avx512.mask3.vfmsubadd.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3, i32 4) %res = call <16 x float> @llvm.x86.avx512.mask3.vfmsubadd.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3, i32 4)
%res1 = call <16 x float> @llvm.x86.avx512.mask3.vfmsubadd.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 -1, i32 0) %res1 = call <16 x float> @llvm.x86.avx512.mask3.vfmsubadd.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 -1, i32 0)
%res2 = fadd <16 x float> %res, %res1 %res2 = fadd <16 x float> %res, %res1
ret <16 x float> %res2 ret <16 x float> %res2
} }
define <16 x float> @test_mask_round_vfmadd512_ps_rrb_rne(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) { define <16 x float> @test_mask_round_vfmadd512_ps_rrb_rne(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) {
; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrb_rne ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrb_rne:
; CHECK: vfmadd213ps {rn-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x19,0xa8,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vfmadd213ps {rn-sae}, %zmm2, %zmm1, %zmm0 {%k1}
; CHECK-NEXT: retq
%res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 0) nounwind %res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 0) nounwind
ret <16 x float> %res ret <16 x float> %res
} }
define <16 x float> @test_mask_round_vfmadd512_ps_rrb_rtn(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) { define <16 x float> @test_mask_round_vfmadd512_ps_rrb_rtn(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) {
; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrb_rtn ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrb_rtn:
; CHECK: vfmadd213ps {rd-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x39,0xa8,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vfmadd213ps {rd-sae}, %zmm2, %zmm1, %zmm0 {%k1}
; CHECK-NEXT: retq
%res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 1) nounwind %res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 1) nounwind
ret <16 x float> %res ret <16 x float> %res
} }
define <16 x float> @test_mask_round_vfmadd512_ps_rrb_rtp(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) { define <16 x float> @test_mask_round_vfmadd512_ps_rrb_rtp(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) {
; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrb_rtp ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrb_rtp:
; CHECK: vfmadd213ps {ru-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x59,0xa8,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vfmadd213ps {ru-sae}, %zmm2, %zmm1, %zmm0 {%k1}
; CHECK-NEXT: retq
%res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 2) nounwind %res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 2) nounwind
ret <16 x float> %res ret <16 x float> %res
} }
define <16 x float> @test_mask_round_vfmadd512_ps_rrb_rtz(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) { define <16 x float> @test_mask_round_vfmadd512_ps_rrb_rtz(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) {
; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrb_rtz ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrb_rtz:
; CHECK: vfmadd213ps {rz-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x79,0xa8,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vfmadd213ps {rz-sae}, %zmm2, %zmm1, %zmm0 {%k1}
; CHECK-NEXT: retq
%res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 3) nounwind %res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 3) nounwind
ret <16 x float> %res ret <16 x float> %res
} }
define <16 x float> @test_mask_round_vfmadd512_ps_rrb_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) { define <16 x float> @test_mask_round_vfmadd512_ps_rrb_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) {
; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrb_current ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrb_current:
; CHECK: vfmadd213ps %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x49,0xa8,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vfmadd213ps %zmm2, %zmm1, %zmm0 {%k1}
; CHECK-NEXT: retq
%res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 4) nounwind %res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 4) nounwind
ret <16 x float> %res ret <16 x float> %res
} }
define <16 x float> @test_mask_round_vfmadd512_ps_rrbz_rne(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) { define <16 x float> @test_mask_round_vfmadd512_ps_rrbz_rne(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrbz_rne ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrbz_rne:
; CHECK: vfmadd213ps {rn-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x18,0xa8,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: vfmadd213ps {rn-sae}, %zmm2, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 0) nounwind %res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 0) nounwind
ret <16 x float> %res ret <16 x float> %res
} }
define <16 x float> @test_mask_round_vfmadd512_ps_rrbz_rtn(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) { define <16 x float> @test_mask_round_vfmadd512_ps_rrbz_rtn(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrbz_rtn ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrbz_rtn:
; CHECK: vfmadd213ps {rd-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x38,0xa8,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: vfmadd213ps {rd-sae}, %zmm2, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 1) nounwind %res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 1) nounwind
ret <16 x float> %res ret <16 x float> %res
} }
define <16 x float> @test_mask_round_vfmadd512_ps_rrbz_rtp(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) { define <16 x float> @test_mask_round_vfmadd512_ps_rrbz_rtp(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrbz_rtp ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrbz_rtp:
; CHECK: vfmadd213ps {ru-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x58,0xa8,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: vfmadd213ps {ru-sae}, %zmm2, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 2) nounwind %res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 2) nounwind
ret <16 x float> %res ret <16 x float> %res
} }
define <16 x float> @test_mask_round_vfmadd512_ps_rrbz_rtz(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) { define <16 x float> @test_mask_round_vfmadd512_ps_rrbz_rtz(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrbz_rtz ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrbz_rtz:
; CHECK: vfmadd213ps {rz-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x78,0xa8,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: vfmadd213ps {rz-sae}, %zmm2, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 3) nounwind %res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 3) nounwind
ret <16 x float> %res ret <16 x float> %res
} }
define <16 x float> @test_mask_round_vfmadd512_ps_rrbz_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) { define <16 x float> @test_mask_round_vfmadd512_ps_rrbz_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrbz_current ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrbz_current:
; CHECK: vfmadd213ps %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x48,0xa8,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: vfmadd213ps %zmm2, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 4) nounwind %res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 4) nounwind
ret <16 x float> %res ret <16 x float> %res
} }
declare <8 x double> @llvm.x86.avx512.mask3.vfmsub.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) declare <8 x double> @llvm.x86.avx512.mask3.vfmsub.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32)
define <8 x double>@test_int_x86_avx512_mask3_vfmsub_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){ define <8 x double>@test_int_x86_avx512_mask3_vfmsub_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){
; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsub_pd_512: ; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsub_pd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm2, %zmm3 ; CHECK-NEXT: vmovaps %zmm2, %zmm3
; CHECK-NEXT: vfmsub231pd %zmm1, %zmm0, %zmm3 {%k1} ; CHECK-NEXT: vfmsub231pd %zmm1, %zmm0, %zmm3 {%k1}
; CHECK-NEXT: vfmsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0 ; CHECK-NEXT: vfmsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0
; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask3.vfmsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4) %res = call <8 x double> @llvm.x86.avx512.mask3.vfmsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4)
%res1 = call <8 x double> @llvm.x86.avx512.mask3.vfmsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0) %res1 = call <8 x double> @llvm.x86.avx512.mask3.vfmsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0)
%res2 = fadd <8 x double> %res, %res1 %res2 = fadd <8 x double> %res, %res1
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; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <16 x float> @llvm.x86.avx512.mask3.vfmsub.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3, i32 4) %res = call <16 x float> @llvm.x86.avx512.mask3.vfmsub.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3, i32 4)
%res1 = call <16 x float> @llvm.x86.avx512.mask3.vfmsub.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 -1, i32 0) %res1 = call <16 x float> @llvm.x86.avx512.mask3.vfmsub.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 -1, i32 0)
%res2 = fadd <16 x float> %res, %res1 %res2 = fadd <16 x float> %res, %res1
ret <16 x float> %res2 ret <16 x float> %res2
} }
define <8 x double> @test_mask_round_vfmadd512_pd_rrb_rne(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { define <8 x double> @test_mask_round_vfmadd512_pd_rrb_rne(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrb_rne ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrb_rne:
; CHECK: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x19,0xa8,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0 {%k1}
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 0) nounwind %res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 0) nounwind
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double> @test_mask_round_vfmadd512_pd_rrb_rtn(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { define <8 x double> @test_mask_round_vfmadd512_pd_rrb_rtn(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrb_rtn ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrb_rtn:
; CHECK: vfmadd213pd {rd-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x39,0xa8,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vfmadd213pd {rd-sae}, %zmm2, %zmm1, %zmm0 {%k1}
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 1) nounwind %res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 1) nounwind
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double> @test_mask_round_vfmadd512_pd_rrb_rtp(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { define <8 x double> @test_mask_round_vfmadd512_pd_rrb_rtp(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrb_rtp ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrb_rtp:
; CHECK: vfmadd213pd {ru-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x59,0xa8,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vfmadd213pd {ru-sae}, %zmm2, %zmm1, %zmm0 {%k1}
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 2) nounwind %res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 2) nounwind
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double> @test_mask_round_vfmadd512_pd_rrb_rtz(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { define <8 x double> @test_mask_round_vfmadd512_pd_rrb_rtz(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrb_rtz ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrb_rtz:
; CHECK: vfmadd213pd {rz-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x79,0xa8,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vfmadd213pd {rz-sae}, %zmm2, %zmm1, %zmm0 {%k1}
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 3) nounwind %res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 3) nounwind
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double> @test_mask_round_vfmadd512_pd_rrb_current(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { define <8 x double> @test_mask_round_vfmadd512_pd_rrb_current(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrb_current ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrb_current:
; CHECK: vfmadd213pd %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x49,0xa8,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vfmadd213pd %zmm2, %zmm1, %zmm0 {%k1}
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 4) nounwind %res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 4) nounwind
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double> @test_mask_round_vfmadd512_pd_rrbz_rne(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { define <8 x double> @test_mask_round_vfmadd512_pd_rrbz_rne(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrbz_rne ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrbz_rne:
; CHECK: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x18,0xa8,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 0) nounwind %res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 0) nounwind
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double> @test_mask_round_vfmadd512_pd_rrbz_rtn(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { define <8 x double> @test_mask_round_vfmadd512_pd_rrbz_rtn(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrbz_rtn ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrbz_rtn:
; CHECK: vfmadd213pd {rd-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x38,0xa8,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: vfmadd213pd {rd-sae}, %zmm2, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 1) nounwind %res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 1) nounwind
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double> @test_mask_round_vfmadd512_pd_rrbz_rtp(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { define <8 x double> @test_mask_round_vfmadd512_pd_rrbz_rtp(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrbz_rtp ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrbz_rtp:
; CHECK: vfmadd213pd {ru-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x58,0xa8,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: vfmadd213pd {ru-sae}, %zmm2, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 2) nounwind %res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 2) nounwind
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double> @test_mask_round_vfmadd512_pd_rrbz_rtz(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { define <8 x double> @test_mask_round_vfmadd512_pd_rrbz_rtz(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrbz_rtz ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrbz_rtz:
; CHECK: vfmadd213pd {rz-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x78,0xa8,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: vfmadd213pd {rz-sae}, %zmm2, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 3) nounwind %res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 3) nounwind
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double> @test_mask_round_vfmadd512_pd_rrbz_current(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { define <8 x double> @test_mask_round_vfmadd512_pd_rrbz_current(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrbz_current ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrbz_current:
; CHECK: vfmadd213pd %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x48,0xa8,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: vfmadd213pd %zmm2, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 4) nounwind %res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 4) nounwind
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double>@test_int_x86_avx512_mask_vfmadd_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){ define <8 x double>@test_int_x86_avx512_mask_vfmadd_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){
; CHECK-LABEL: test_int_x86_avx512_mask_vfmadd_pd_512: ; CHECK-LABEL: test_int_x86_avx512_mask_vfmadd_pd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfmadd213pd %zmm2, %zmm1, %zmm3 {%k1} ; CHECK-NEXT: vfmadd213pd %zmm2, %zmm1, %zmm3 {%k1}
; CHECK-NEXT: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0 ; CHECK-NEXT: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0
; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4) %res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4)
%res1 = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0) %res1 = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0)
%res2 = fadd <8 x double> %res, %res1 %res2 = fadd <8 x double> %res, %res1
ret <8 x double> %res2 ret <8 x double> %res2
} }
declare <8 x double> @llvm.x86.avx512.mask3.vfmadd.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) declare <8 x double> @llvm.x86.avx512.mask3.vfmadd.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32)
define <8 x double>@test_int_x86_avx512_mask3_vfmadd_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){ define <8 x double>@test_int_x86_avx512_mask3_vfmadd_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){
; CHECK-LABEL: test_int_x86_avx512_mask3_vfmadd_pd_512: ; CHECK-LABEL: test_int_x86_avx512_mask3_vfmadd_pd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm2, %zmm3 ; CHECK-NEXT: vmovaps %zmm2, %zmm3
; CHECK-NEXT: vfmadd231pd %zmm1, %zmm0, %zmm3 {%k1} ; CHECK-NEXT: vfmadd231pd %zmm1, %zmm0, %zmm3 {%k1}
; CHECK-NEXT: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0 ; CHECK-NEXT: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0
; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask3.vfmadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4) %res = call <8 x double> @llvm.x86.avx512.mask3.vfmadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4)
%res1 = call <8 x double> @llvm.x86.avx512.mask3.vfmadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0) %res1 = call <8 x double> @llvm.x86.avx512.mask3.vfmadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0)
%res2 = fadd <8 x double> %res, %res1 %res2 = fadd <8 x double> %res, %res1
ret <8 x double> %res2 ret <8 x double> %res2
} }
declare <8 x double> @llvm.x86.avx512.maskz.vfmadd.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) declare <8 x double> @llvm.x86.avx512.maskz.vfmadd.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32)
define <8 x double>@test_int_x86_avx512_maskz_vfmadd_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){ define <8 x double>@test_int_x86_avx512_maskz_vfmadd_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){
; CHECK-LABEL: test_int_x86_avx512_maskz_vfmadd_pd_512: ; CHECK-LABEL: test_int_x86_avx512_maskz_vfmadd_pd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfmadd213pd %zmm2, %zmm1, %zmm3 {%k1} {z} ; CHECK-NEXT: vfmadd213pd %zmm2, %zmm1, %zmm3 {%k1} {z}
; CHECK-NEXT: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0 ; CHECK-NEXT: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0
; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.maskz.vfmadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4) %res = call <8 x double> @llvm.x86.avx512.maskz.vfmadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4)
%res1 = call <8 x double> @llvm.x86.avx512.maskz.vfmadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0) %res1 = call <8 x double> @llvm.x86.avx512.maskz.vfmadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0)
%res2 = fadd <8 x double> %res, %res1 %res2 = fadd <8 x double> %res, %res1
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
%res = call <16 x float> @llvm.x86.avx512.maskz.vfmadd.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3, i32 4) %res = call <16 x float> @llvm.x86.avx512.maskz.vfmadd.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3, i32 4)
%res1 = call <16 x float> @llvm.x86.avx512.maskz.vfmadd.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 -1, i32 0) %res1 = call <16 x float> @llvm.x86.avx512.maskz.vfmadd.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 -1, i32 0)
%res2 = fadd <16 x float> %res, %res1 %res2 = fadd <16 x float> %res, %res1
ret <16 x float> %res2 ret <16 x float> %res2
} }
define <8 x double> @test_mask_round_vfnmsub512_pd_rrb_rne(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { define <8 x double> @test_mask_round_vfnmsub512_pd_rrb_rne(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrb_rne ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrb_rne:
; CHECK: vfnmsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x19,0xae,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vfnmsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0 {%k1}
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 0) nounwind %res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 0) nounwind
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double> @test_mask_round_vfnmsub512_pd_rrb_rtn(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { define <8 x double> @test_mask_round_vfnmsub512_pd_rrb_rtn(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrb_rtn ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrb_rtn:
; CHECK: vfnmsub213pd {rd-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x39,0xae,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vfnmsub213pd {rd-sae}, %zmm2, %zmm1, %zmm0 {%k1}
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 1) nounwind %res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 1) nounwind
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double> @test_mask_round_vfnmsub512_pd_rrb_rtp(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { define <8 x double> @test_mask_round_vfnmsub512_pd_rrb_rtp(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrb_rtp ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrb_rtp:
; CHECK: vfnmsub213pd {ru-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x59,0xae,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vfnmsub213pd {ru-sae}, %zmm2, %zmm1, %zmm0 {%k1}
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 2) nounwind %res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 2) nounwind
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double> @test_mask_round_vfnmsub512_pd_rrb_rtz(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { define <8 x double> @test_mask_round_vfnmsub512_pd_rrb_rtz(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrb_rtz ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrb_rtz:
; CHECK: vfnmsub213pd {rz-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x79,0xae,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vfnmsub213pd {rz-sae}, %zmm2, %zmm1, %zmm0 {%k1}
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 3) nounwind %res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 3) nounwind
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double> @test_mask_round_vfnmsub512_pd_rrb_current(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { define <8 x double> @test_mask_round_vfnmsub512_pd_rrb_current(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) {
; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrb_current ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrb_current:
; CHECK: vfnmsub213pd %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x49,0xae,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vfnmsub213pd %zmm2, %zmm1, %zmm0 {%k1}
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 4) nounwind %res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 4) nounwind
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double> @test_mask_round_vfnmsub512_pd_rrbz_rne(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { define <8 x double> @test_mask_round_vfnmsub512_pd_rrbz_rne(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrbz_rne ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrbz_rne:
; CHECK: vfnmsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x18,0xae,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: vfnmsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 0) nounwind %res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 0) nounwind
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double> @test_mask_round_vfnmsub512_pd_rrbz_rtn(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { define <8 x double> @test_mask_round_vfnmsub512_pd_rrbz_rtn(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrbz_rtn ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrbz_rtn:
; CHECK: vfnmsub213pd {rd-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x38,0xae,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: vfnmsub213pd {rd-sae}, %zmm2, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 1) nounwind %res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 1) nounwind
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double> @test_mask_round_vfnmsub512_pd_rrbz_rtp(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { define <8 x double> @test_mask_round_vfnmsub512_pd_rrbz_rtp(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrbz_rtp ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrbz_rtp:
; CHECK: vfnmsub213pd {ru-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x58,0xae,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: vfnmsub213pd {ru-sae}, %zmm2, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 2) nounwind %res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 2) nounwind
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double> @test_mask_round_vfnmsub512_pd_rrbz_rtz(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { define <8 x double> @test_mask_round_vfnmsub512_pd_rrbz_rtz(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrbz_rtz ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrbz_rtz:
; CHECK: vfnmsub213pd {rz-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x78,0xae,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: vfnmsub213pd {rz-sae}, %zmm2, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 3) nounwind %res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 3) nounwind
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double> @test_mask_round_vfnmsub512_pd_rrbz_current(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { define <8 x double> @test_mask_round_vfnmsub512_pd_rrbz_current(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrbz_current ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrbz_current:
; CHECK: vfnmsub213pd %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x48,0xae,0xc2] ; CHECK: ## BB#0:
; CHECK-NEXT: vfnmsub213pd %zmm2, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 4) nounwind %res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 4) nounwind
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double>@test_int_x86_avx512_mask_vfnmsub_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){ define <8 x double>@test_int_x86_avx512_mask_vfnmsub_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){
; CHECK-LABEL: test_int_x86_avx512_mask_vfnmsub_pd_512: ; CHECK-LABEL: test_int_x86_avx512_mask_vfnmsub_pd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfnmsub213pd %zmm2, %zmm1, %zmm3 {%k1} ; CHECK-NEXT: vfnmsub213pd %zmm2, %zmm1, %zmm3 {%k1}
; CHECK-NEXT: vfnmsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0 ; CHECK-NEXT: vfnmsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0
; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4) %res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4)
%res1 = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0) %res1 = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0)
%res2 = fadd <8 x double> %res, %res1 %res2 = fadd <8 x double> %res, %res1
ret <8 x double> %res2 ret <8 x double> %res2
} }
declare <8 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) declare <8 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32)
define <8 x double>@test_int_x86_avx512_mask3_vfnmsub_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){ define <8 x double>@test_int_x86_avx512_mask3_vfnmsub_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){
; CHECK-LABEL: test_int_x86_avx512_mask3_vfnmsub_pd_512: ; CHECK-LABEL: test_int_x86_avx512_mask3_vfnmsub_pd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm2, %zmm3 ; CHECK-NEXT: vmovaps %zmm2, %zmm3
; CHECK-NEXT: vfnmsub231pd %zmm1, %zmm0, %zmm3 {%k1} ; CHECK-NEXT: vfnmsub231pd %zmm1, %zmm0, %zmm3 {%k1}
; CHECK-NEXT: vfnmsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0 ; CHECK-NEXT: vfnmsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0
; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4) %res = call <8 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4)
%res1 = call <8 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0) %res1 = call <8 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0)
%res2 = fadd <8 x double> %res, %res1 %res2 = fadd <8 x double> %res, %res1
Show All 30 Lines; CHECK-NEXT: retq
%res1 = call <16 x float> @llvm.x86.avx512.mask3.vfnmsub.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 -1, i32 0) %res1 = call <16 x float> @llvm.x86.avx512.mask3.vfnmsub.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 -1, i32 0)
%res2 = fadd <16 x float> %res, %res1 %res2 = fadd <16 x float> %res, %res1
ret <16 x float> %res2 ret <16 x float> %res2
} }
define <8 x double>@test_int_x86_avx512_mask_vfnmadd_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){ define <8 x double>@test_int_x86_avx512_mask_vfnmadd_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){
; CHECK-LABEL: test_int_x86_avx512_mask_vfnmadd_pd_512: ; CHECK-LABEL: test_int_x86_avx512_mask_vfnmadd_pd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfnmadd213pd %zmm2, %zmm1, %zmm3 {%k1} ; CHECK-NEXT: vfnmadd213pd %zmm2, %zmm1, %zmm3 {%k1}
; CHECK-NEXT: vfnmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0 ; CHECK-NEXT: vfnmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0
; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vfnmadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4) %res = call <8 x double> @llvm.x86.avx512.mask.vfnmadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4)
%res1 = call <8 x double> @llvm.x86.avx512.mask.vfnmadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0) %res1 = call <8 x double> @llvm.x86.avx512.mask.vfnmadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0)
%res2 = fadd <8 x double> %res, %res1 %res2 = fadd <8 x double> %res, %res1
Show All 17 Lines

llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll

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Show First 20 Lines • Show All 510 Lines • ▼ Show 20 Lines
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.vbroadcast.sd.512(i8* %a0) ; <<8 x double>> [#uses=1] %res = call <8 x double> @llvm.x86.avx512.vbroadcast.sd.512(i8* %a0) ; <<8 x double>> [#uses=1]
ret <8 x double> %res ret <8 x double> %res
} }
declare <8 x double> @llvm.x86.avx512.vbroadcast.sd.512(i8*) nounwind readonly declare <8 x double> @llvm.x86.avx512.vbroadcast.sd.512(i8*) nounwind readonly
define <16 x float> @test_x86_vbroadcast_ss_ps_512(<4 x float> %a0, <16 x float> %a1, i16 %mask ) { define <16 x float> @test_x86_vbroadcast_ss_ps_512(<4 x float> %a0, <16 x float> %a1, i16 %mask ) {
; CHECK-LABEL: test_x86_vbroadcast_ss_ps_512: ; CHECK-LABEL: test_x86_vbroadcast_ss_ps_512:
; CHECK: kmovw %edi, %k1 ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vbroadcastss %xmm0, %zmm1 {%k1} ; CHECK-NEXT: vbroadcastss %xmm0, %zmm1 {%k1}
; CHECK-NEXT: vbroadcastss %xmm0, %zmm2 {%k1} {z} ; CHECK-NEXT: vbroadcastss %xmm0, %zmm2 {%k1} {z}
; CHECK-NEXT: vbroadcastss %xmm0, %zmm0 ; CHECK-NEXT: vbroadcastss %xmm0, %zmm0
; CHECK-NEXT: vaddps %zmm1, %zmm0, %zmm0 ; CHECK-NEXT: vaddps %zmm1, %zmm0, %zmm0
; CHECK-NEXT: vaddps %zmm0, %zmm2, %zmm0
; CHECK-NEXT: retq
%res = call <16 x float> @llvm.x86.avx512.mask.broadcast.ss.ps.512(<4 x float> %a0, <16 x float> zeroinitializer, i16 -1) %res = call <16 x float> @llvm.x86.avx512.mask.broadcast.ss.ps.512(<4 x float> %a0, <16 x float> zeroinitializer, i16 -1)
%res1 = call <16 x float> @llvm.x86.avx512.mask.broadcast.ss.ps.512(<4 x float> %a0, <16 x float> %a1, i16 %mask) %res1 = call <16 x float> @llvm.x86.avx512.mask.broadcast.ss.ps.512(<4 x float> %a0, <16 x float> %a1, i16 %mask)
%res2 = call <16 x float> @llvm.x86.avx512.mask.broadcast.ss.ps.512(<4 x float> %a0, <16 x float> zeroinitializer, i16 %mask) %res2 = call <16 x float> @llvm.x86.avx512.mask.broadcast.ss.ps.512(<4 x float> %a0, <16 x float> zeroinitializer, i16 %mask)
%res3 = fadd <16 x float> %res, %res1 %res3 = fadd <16 x float> %res, %res1
%res4 = fadd <16 x float> %res2, %res3 %res4 = fadd <16 x float> %res2, %res3
ret <16 x float> %res4 ret <16 x float> %res4
} }
declare <16 x float> @llvm.x86.avx512.mask.broadcast.ss.ps.512(<4 x float>, <16 x float>, i16) nounwind readonly declare <16 x float> @llvm.x86.avx512.mask.broadcast.ss.ps.512(<4 x float>, <16 x float>, i16) nounwind readonly
define <8 x double> @test_x86_vbroadcast_sd_pd_512(<2 x double> %a0, <8 x double> %a1, i8 %mask ) { define <8 x double> @test_x86_vbroadcast_sd_pd_512(<2 x double> %a0, <8 x double> %a1, i8 %mask ) {
; CHECK-LABEL: test_x86_vbroadcast_sd_pd_512: ; CHECK-LABEL: test_x86_vbroadcast_sd_pd_512:
; CHECK: kmovw %eax, %k1 ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vbroadcastsd %xmm0, %zmm1 {%k1} ; CHECK-NEXT: vbroadcastsd %xmm0, %zmm1 {%k1}
; CHECK-NEXT: vbroadcastsd %xmm0, %zmm2 {%k1} {z} ; CHECK-NEXT: vbroadcastsd %xmm0, %zmm2 {%k1} {z}
; CHECK-NEXT: vbroadcastsd %xmm0, %zmm0 ; CHECK-NEXT: vbroadcastsd %xmm0, %zmm0
; CHECK-NEXT: vaddpd %zmm1, %zmm0, %zmm0 ; CHECK-NEXT: vaddpd %zmm1, %zmm0, %zmm0
; CHECK-NEXT: vaddpd %zmm0, %zmm2, %zmm0
; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.broadcast.sd.pd.512(<2 x double> %a0, <8 x double> zeroinitializer, i8 -1) %res = call <8 x double> @llvm.x86.avx512.mask.broadcast.sd.pd.512(<2 x double> %a0, <8 x double> zeroinitializer, i8 -1)
%res1 = call <8 x double> @llvm.x86.avx512.mask.broadcast.sd.pd.512(<2 x double> %a0, <8 x double> %a1, i8 %mask) %res1 = call <8 x double> @llvm.x86.avx512.mask.broadcast.sd.pd.512(<2 x double> %a0, <8 x double> %a1, i8 %mask)
%res2 = call <8 x double> @llvm.x86.avx512.mask.broadcast.sd.pd.512(<2 x double> %a0, <8 x double> zeroinitializer, i8 %mask) %res2 = call <8 x double> @llvm.x86.avx512.mask.broadcast.sd.pd.512(<2 x double> %a0, <8 x double> zeroinitializer, i8 %mask)
%res3 = fadd <8 x double> %res, %res1 %res3 = fadd <8 x double> %res, %res1
%res4 = fadd <8 x double> %res2, %res3 %res4 = fadd <8 x double> %res2, %res3
ret <8 x double> %res4 ret <8 x double> %res4
} }
declare <8 x double> @llvm.x86.avx512.mask.broadcast.sd.pd.512(<2 x double>, <8 x double>, i8) nounwind readonly declare <8 x double> @llvm.x86.avx512.mask.broadcast.sd.pd.512(<2 x double>, <8 x double>, i8) nounwind readonly
define <16 x i32>@test_int_x86_avx512_pbroadcastd_512(<4 x i32> %x0, <16 x i32> %x1, i16 %mask) { define <16 x i32>@test_int_x86_avx512_pbroadcastd_512(<4 x i32> %x0, <16 x i32> %x1, i16 %mask) {
; CHECK-LABEL: test_int_x86_avx512_pbroadcastd_512: ; CHECK-LABEL: test_int_x86_avx512_pbroadcastd_512:
Show All 22 Lines; CHECK-NEXT: retq
%res = call <16 x i32> @llvm.x86.avx512.pbroadcastd.i32.512(i32 %a0) ; <<16 x i32>> [#uses=1] %res = call <16 x i32> @llvm.x86.avx512.pbroadcastd.i32.512(i32 %a0) ; <<16 x i32>> [#uses=1]
ret <16 x i32> %res ret <16 x i32> %res
} }
declare <16 x i32> @llvm.x86.avx512.pbroadcastd.i32.512(i32) nounwind readonly declare <16 x i32> @llvm.x86.avx512.pbroadcastd.i32.512(i32) nounwind readonly
define <8 x i64>@test_int_x86_avx512_pbroadcastq_512(<2 x i64> %x0, <8 x i64> %x1, i8 %mask) { define <8 x i64>@test_int_x86_avx512_pbroadcastq_512(<2 x i64> %x0, <8 x i64> %x1, i8 %mask) {
; CHECK-LABEL: test_int_x86_avx512_pbroadcastq_512: ; CHECK-LABEL: test_int_x86_avx512_pbroadcastq_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpbroadcastq %xmm0, %zmm1 {%k1} ; CHECK-NEXT: vpbroadcastq %xmm0, %zmm1 {%k1}
; CHECK-NEXT: vpbroadcastq %xmm0, %zmm2 {%k1} {z} ; CHECK-NEXT: vpbroadcastq %xmm0, %zmm2 {%k1} {z}
; CHECK-NEXT: vpbroadcastq %xmm0, %zmm0 ; CHECK-NEXT: vpbroadcastq %xmm0, %zmm0
; CHECK-NEXT: vpaddq %zmm1, %zmm0, %zmm0 ; CHECK-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; CHECK-NEXT: vpaddq %zmm0, %zmm2, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm2, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.pbroadcastq.512(<2 x i64> %x0, <8 x i64> %x1,i8 -1) %res = call <8 x i64> @llvm.x86.avx512.pbroadcastq.512(<2 x i64> %x0, <8 x i64> %x1,i8 -1)
%res1 = call <8 x i64> @llvm.x86.avx512.pbroadcastq.512(<2 x i64> %x0, <8 x i64> %x1,i8 %mask) %res1 = call <8 x i64> @llvm.x86.avx512.pbroadcastq.512(<2 x i64> %x0, <8 x i64> %x1,i8 %mask)
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <16 x i32> @llvm.x86.avx512.mask.conflict.d.512(<16 x i32> %a, <16 x i32> zeroinitializer, i16 %mask) %res = call <16 x i32> @llvm.x86.avx512.mask.conflict.d.512(<16 x i32> %a, <16 x i32> zeroinitializer, i16 %mask)
ret <16 x i32> %res ret <16 x i32> %res
} }
define <8 x i64> @test_mask_conflict_q(<8 x i64> %a, <8 x i64> %b, i8 %mask) { define <8 x i64> @test_mask_conflict_q(<8 x i64> %a, <8 x i64> %b, i8 %mask) {
; CHECK-LABEL: test_mask_conflict_q: ; CHECK-LABEL: test_mask_conflict_q:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpconflictq %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vpconflictq %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vmovaps %zmm1, %zmm0 ; CHECK-NEXT: vmovaps %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.conflict.q.512(<8 x i64> %a, <8 x i64> %b, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.conflict.q.512(<8 x i64> %a, <8 x i64> %b, i8 %mask)
ret <8 x i64> %res ret <8 x i64> %res
} }
define <16 x i32> @test_lzcnt_d(<16 x i32> %a) { define <16 x i32> @test_lzcnt_d(<16 x i32> %a) {
Show All 28 Lines
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <16 x i32> @llvm.x86.avx512.mask.lzcnt.d.512(<16 x i32> %a, <16 x i32> %b, i16 %mask) %res = call <16 x i32> @llvm.x86.avx512.mask.lzcnt.d.512(<16 x i32> %a, <16 x i32> %b, i16 %mask)
ret <16 x i32> %res ret <16 x i32> %res
} }
define <8 x i64> @test_mask_lzcnt_q(<8 x i64> %a, <8 x i64> %b, i8 %mask) { define <8 x i64> @test_mask_lzcnt_q(<8 x i64> %a, <8 x i64> %b, i8 %mask) {
; CHECK-LABEL: test_mask_lzcnt_q: ; CHECK-LABEL: test_mask_lzcnt_q:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vplzcntq %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vplzcntq %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vmovaps %zmm1, %zmm0 ; CHECK-NEXT: vmovaps %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.lzcnt.q.512(<8 x i64> %a, <8 x i64> %b, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.lzcnt.q.512(<8 x i64> %a, <8 x i64> %b, i8 %mask)
ret <8 x i64> %res ret <8 x i64> %res
} }
define <16 x float> @test_x86_mask_blend_ps_512(i16 %a0, <16 x float> %a1, <16 x float> %a2) { define <16 x float> @test_x86_mask_blend_ps_512(i16 %a0, <16 x float> %a1, <16 x float> %a2) {
; CHECK-LABEL: test_x86_mask_blend_ps_512: ; CHECK-LABEL: test_x86_mask_blend_ps_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vblendmps %zmm1, %zmm0, %zmm0 {%k1} ; CHECK-NEXT: vblendmps %zmm1, %zmm0, %zmm0 {%k1}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <16 x float> @llvm.x86.avx512.mask.blend.ps.512(<16 x float> %a1, <16 x float> %a2, i16 %a0) ; <<16 x float>> [#uses=1] %res = call <16 x float> @llvm.x86.avx512.mask.blend.ps.512(<16 x float> %a1, <16 x float> %a2, i16 %a0) ; <<16 x float>> [#uses=1]
ret <16 x float> %res ret <16 x float> %res
} }
declare <16 x float> @llvm.x86.avx512.mask.blend.ps.512(<16 x float>, <16 x float>, i16) nounwind readonly declare <16 x float> @llvm.x86.avx512.mask.blend.ps.512(<16 x float>, <16 x float>, i16) nounwind readonly
define <8 x double> @test_x86_mask_blend_pd_512(i8 %a0, <8 x double> %a1, <8 x double> %a2) { define <8 x double> @test_x86_mask_blend_pd_512(i8 %a0, <8 x double> %a1, <8 x double> %a2) {
; CHECK-LABEL: test_x86_mask_blend_pd_512: ; CHECK-LABEL: test_x86_mask_blend_pd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vblendmpd %zmm1, %zmm0, %zmm0 {%k1} ; CHECK-NEXT: vblendmpd %zmm1, %zmm0, %zmm0 {%k1}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.blend.pd.512(<8 x double> %a1, <8 x double> %a2, i8 %a0) ; <<8 x double>> [#uses=1] %res = call <8 x double> @llvm.x86.avx512.mask.blend.pd.512(<8 x double> %a1, <8 x double> %a2, i8 %a0) ; <<8 x double>> [#uses=1]
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double> @test_x86_mask_blend_pd_512_memop(<8 x double> %a, <8 x double>* %ptr, i8 %mask) { define <8 x double> @test_x86_mask_blend_pd_512_memop(<8 x double> %a, <8 x double>* %ptr, i8 %mask) {
; CHECK-LABEL: test_x86_mask_blend_pd_512_memop: ; CHECK-LABEL: test_x86_mask_blend_pd_512_memop:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vblendmpd (%rdi), %zmm0, %zmm0 {%k1} ; CHECK-NEXT: vblendmpd (%rdi), %zmm0, %zmm0 {%k1}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%b = load <8 x double>, <8 x double>* %ptr %b = load <8 x double>, <8 x double>* %ptr
%res = call <8 x double> @llvm.x86.avx512.mask.blend.pd.512(<8 x double> %a, <8 x double> %b, i8 %mask) ; <<8 x double>> [#uses=1] %res = call <8 x double> @llvm.x86.avx512.mask.blend.pd.512(<8 x double> %a, <8 x double> %b, i8 %mask) ; <<8 x double>> [#uses=1]
ret <8 x double> %res ret <8 x double> %res
} }
declare <8 x double> @llvm.x86.avx512.mask.blend.pd.512(<8 x double>, <8 x double>, i8) nounwind readonly declare <8 x double> @llvm.x86.avx512.mask.blend.pd.512(<8 x double>, <8 x double>, i8) nounwind readonly
define <16 x i32> @test_x86_mask_blend_d_512(i16 %a0, <16 x i32> %a1, <16 x i32> %a2) { define <16 x i32> @test_x86_mask_blend_d_512(i16 %a0, <16 x i32> %a1, <16 x i32> %a2) {
; CHECK-LABEL: test_x86_mask_blend_d_512: ; CHECK-LABEL: test_x86_mask_blend_d_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vpblendmd %zmm1, %zmm0, %zmm0 {%k1} ; CHECK-NEXT: vpblendmd %zmm1, %zmm0, %zmm0 {%k1}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <16 x i32> @llvm.x86.avx512.mask.blend.d.512(<16 x i32> %a1, <16 x i32> %a2, i16 %a0) ; <<16 x i32>> [#uses=1] %res = call <16 x i32> @llvm.x86.avx512.mask.blend.d.512(<16 x i32> %a1, <16 x i32> %a2, i16 %a0) ; <<16 x i32>> [#uses=1]
ret <16 x i32> %res ret <16 x i32> %res
} }
declare <16 x i32> @llvm.x86.avx512.mask.blend.d.512(<16 x i32>, <16 x i32>, i16) nounwind readonly declare <16 x i32> @llvm.x86.avx512.mask.blend.d.512(<16 x i32>, <16 x i32>, i16) nounwind readonly
define <8 x i64> @test_x86_mask_blend_q_512(i8 %a0, <8 x i64> %a1, <8 x i64> %a2) { define <8 x i64> @test_x86_mask_blend_q_512(i8 %a0, <8 x i64> %a1, <8 x i64> %a2) {
; CHECK-LABEL: test_x86_mask_blend_q_512: ; CHECK-LABEL: test_x86_mask_blend_q_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpblendmq %zmm1, %zmm0, %zmm0 {%k1} ; CHECK-NEXT: vpblendmq %zmm1, %zmm0, %zmm0 {%k1}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.blend.q.512(<8 x i64> %a1, <8 x i64> %a2, i8 %a0) ; <<8 x i64>> [#uses=1] %res = call <8 x i64> @llvm.x86.avx512.mask.blend.q.512(<8 x i64> %a1, <8 x i64> %a2, i8 %a0) ; <<8 x i64>> [#uses=1]
ret <8 x i64> %res ret <8 x i64> %res
} }
declare <8 x i64> @llvm.x86.avx512.mask.blend.q.512(<8 x i64>, <8 x i64>, i8) nounwind readonly declare <8 x i64> @llvm.x86.avx512.mask.blend.q.512(<8 x i64>, <8 x i64>, i8) nounwind readonly
define i16 @test_cmpps(<16 x float> %a, <16 x float> %b) { define i16 @test_cmpps(<16 x float> %a, <16 x float> %b) {
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
ret <16 x i32> %res2 ret <16 x i32> %res2
} }
declare <8 x i64> @llvm.x86.avx512.mask.pabs.q.512(<8 x i64>, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.pabs.q.512(<8 x i64>, <8 x i64>, i8)
define <8 x i64>@test_int_x86_avx512_mask_pabs_q_512(<8 x i64> %x0, <8 x i64> %x1, i8 %x2) { define <8 x i64>@test_int_x86_avx512_mask_pabs_q_512(<8 x i64> %x0, <8 x i64> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pabs_q_512: ; CHECK-LABEL: test_int_x86_avx512_mask_pabs_q_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpabsq %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vpabsq %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vpabsq %zmm0, %zmm0 ; CHECK-NEXT: vpabsq %zmm0, %zmm0
; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.pabs.q.512(<8 x i64> %x0, <8 x i64> %x1, i8 %x2) %res = call <8 x i64> @llvm.x86.avx512.mask.pabs.q.512(<8 x i64> %x0, <8 x i64> %x1, i8 %x2)
%res1 = call <8 x i64> @llvm.x86.avx512.mask.pabs.q.512(<8 x i64> %x0, <8 x i64> %x1, i8 -1) %res1 = call <8 x i64> @llvm.x86.avx512.mask.pabs.q.512(<8 x i64> %x0, <8 x i64> %x1, i8 -1)
%res2 = add <8 x i64> %res, %res1 %res2 = add <8 x i64> %res, %res1
ret <8 x i64> %res2 ret <8 x i64> %res2
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
ret <16 x float> %res4 ret <16 x float> %res4
} }
declare <16 x float> @llvm.x86.avx512.mask.loadu.ps.512(i8*, <16 x float>, i16) declare <16 x float> @llvm.x86.avx512.mask.loadu.ps.512(i8*, <16 x float>, i16)
define <8 x double> @test_mask_load_aligned_pd(<8 x double> %data, i8* %ptr, i8 %mask) { define <8 x double> @test_mask_load_aligned_pd(<8 x double> %data, i8* %ptr, i8 %mask) {
; CHECK-LABEL: test_mask_load_aligned_pd: ; CHECK-LABEL: test_mask_load_aligned_pd:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovapd (%rdi), %zmm0 ; CHECK-NEXT: vmovapd (%rdi), %zmm0
; CHECK-NEXT: vmovapd (%rdi), %zmm0 {%k1} ; CHECK-NEXT: vmovapd (%rdi), %zmm0 {%k1}
; CHECK-NEXT: vmovapd (%rdi), %zmm1 {%k1} {z} ; CHECK-NEXT: vmovapd (%rdi), %zmm1 {%k1} {z}
; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.load.pd.512(i8* %ptr, <8 x double> zeroinitializer, i8 -1) %res = call <8 x double> @llvm.x86.avx512.mask.load.pd.512(i8* %ptr, <8 x double> zeroinitializer, i8 -1)
%res1 = call <8 x double> @llvm.x86.avx512.mask.load.pd.512(i8* %ptr, <8 x double> %res, i8 %mask) %res1 = call <8 x double> @llvm.x86.avx512.mask.load.pd.512(i8* %ptr, <8 x double> %res, i8 %mask)
%res2 = call <8 x double> @llvm.x86.avx512.mask.load.pd.512(i8* %ptr, <8 x double> zeroinitializer, i8 %mask) %res2 = call <8 x double> @llvm.x86.avx512.mask.load.pd.512(i8* %ptr, <8 x double> zeroinitializer, i8 %mask)
%res4 = fadd <8 x double> %res2, %res1 %res4 = fadd <8 x double> %res2, %res1
ret <8 x double> %res4 ret <8 x double> %res4
} }
declare <8 x double> @llvm.x86.avx512.mask.load.pd.512(i8*, <8 x double>, i8) declare <8 x double> @llvm.x86.avx512.mask.load.pd.512(i8*, <8 x double>, i8)
define <8 x double> @test_mask_load_unaligned_pd(<8 x double> %data, i8* %ptr, i8 %mask) { define <8 x double> @test_mask_load_unaligned_pd(<8 x double> %data, i8* %ptr, i8 %mask) {
; CHECK-LABEL: test_mask_load_unaligned_pd: ; CHECK-LABEL: test_mask_load_unaligned_pd:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovupd (%rdi), %zmm0 ; CHECK-NEXT: vmovupd (%rdi), %zmm0
; CHECK-NEXT: vmovupd (%rdi), %zmm0 {%k1} ; CHECK-NEXT: vmovupd (%rdi), %zmm0 {%k1}
; CHECK-NEXT: vmovupd (%rdi), %zmm1 {%k1} {z} ; CHECK-NEXT: vmovupd (%rdi), %zmm1 {%k1} {z}
; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.loadu.pd.512(i8* %ptr, <8 x double> zeroinitializer, i8 -1) %res = call <8 x double> @llvm.x86.avx512.mask.loadu.pd.512(i8* %ptr, <8 x double> zeroinitializer, i8 -1)
%res1 = call <8 x double> @llvm.x86.avx512.mask.loadu.pd.512(i8* %ptr, <8 x double> %res, i8 %mask) %res1 = call <8 x double> @llvm.x86.avx512.mask.loadu.pd.512(i8* %ptr, <8 x double> %res, i8 %mask)
%res2 = call <8 x double> @llvm.x86.avx512.mask.loadu.pd.512(i8* %ptr, <8 x double> zeroinitializer, i8 %mask) %res2 = call <8 x double> @llvm.x86.avx512.mask.loadu.pd.512(i8* %ptr, <8 x double> zeroinitializer, i8 %mask)
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; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.valign.q.512(<8 x i64> %a, <8 x i64> %b, i32 2, <8 x i64> zeroinitializer, i8 -1) %res = call <8 x i64> @llvm.x86.avx512.mask.valign.q.512(<8 x i64> %a, <8 x i64> %b, i32 2, <8 x i64> zeroinitializer, i8 -1)
ret <8 x i64> %res ret <8 x i64> %res
} }
define <8 x i64> @test_mask_valign_q(<8 x i64> %a, <8 x i64> %b, <8 x i64> %src, i8 %mask) { define <8 x i64> @test_mask_valign_q(<8 x i64> %a, <8 x i64> %b, <8 x i64> %src, i8 %mask) {
; CHECK-LABEL: test_mask_valign_q: ; CHECK-LABEL: test_mask_valign_q:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: valignq $2, %zmm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: valignq $2, %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vmovaps %zmm2, %zmm0 ; CHECK-NEXT: vmovaps %zmm2, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.valign.q.512(<8 x i64> %a, <8 x i64> %b, i32 2, <8 x i64> %src, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.valign.q.512(<8 x i64> %a, <8 x i64> %b, i32 2, <8 x i64> %src, i8 %mask)
ret <8 x i64> %res ret <8 x i64> %res
} }
declare <8 x i64> @llvm.x86.avx512.mask.valign.q.512(<8 x i64>, <8 x i64>, i32, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.valign.q.512(<8 x i64>, <8 x i64>, i32, <8 x i64>, i8)
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; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call i8 @llvm.x86.avx512.mask.pcmpeq.q.512(<8 x i64> %a, <8 x i64> %b, i8 -1) %res = call i8 @llvm.x86.avx512.mask.pcmpeq.q.512(<8 x i64> %a, <8 x i64> %b, i8 -1)
ret i8 %res ret i8 %res
} }
define i8 @test_mask_pcmpeq_q(<8 x i64> %a, <8 x i64> %b, i8 %mask) { define i8 @test_mask_pcmpeq_q(<8 x i64> %a, <8 x i64> %b, i8 %mask) {
; CHECK-LABEL: test_mask_pcmpeq_q: ; CHECK-LABEL: test_mask_pcmpeq_q:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 {%k1} ; CHECK-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call i8 @llvm.x86.avx512.mask.pcmpeq.q.512(<8 x i64> %a, <8 x i64> %b, i8 %mask) %res = call i8 @llvm.x86.avx512.mask.pcmpeq.q.512(<8 x i64> %a, <8 x i64> %b, i8 %mask)
ret i8 %res ret i8 %res
} }
declare i8 @llvm.x86.avx512.mask.pcmpeq.q.512(<8 x i64>, <8 x i64>, i8) declare i8 @llvm.x86.avx512.mask.pcmpeq.q.512(<8 x i64>, <8 x i64>, i8)
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; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call i8 @llvm.x86.avx512.mask.pcmpgt.q.512(<8 x i64> %a, <8 x i64> %b, i8 -1) %res = call i8 @llvm.x86.avx512.mask.pcmpgt.q.512(<8 x i64> %a, <8 x i64> %b, i8 -1)
ret i8 %res ret i8 %res
} }
define i8 @test_mask_pcmpgt_q(<8 x i64> %a, <8 x i64> %b, i8 %mask) { define i8 @test_mask_pcmpgt_q(<8 x i64> %a, <8 x i64> %b, i8 %mask) {
; CHECK-LABEL: test_mask_pcmpgt_q: ; CHECK-LABEL: test_mask_pcmpgt_q:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 {%k1} ; CHECK-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call i8 @llvm.x86.avx512.mask.pcmpgt.q.512(<8 x i64> %a, <8 x i64> %b, i8 %mask) %res = call i8 @llvm.x86.avx512.mask.pcmpgt.q.512(<8 x i64> %a, <8 x i64> %b, i8 %mask)
ret i8 %res ret i8 %res
} }
declare i8 @llvm.x86.avx512.mask.pcmpgt.q.512(<8 x i64>, <8 x i64>, i8) declare i8 @llvm.x86.avx512.mask.pcmpgt.q.512(<8 x i64>, <8 x i64>, i8)
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%res7 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 7, i8 -1) %res7 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 7, i8 -1)
%vec7 = insertelement <8 x i8> %vec6, i8 %res7, i32 7 %vec7 = insertelement <8 x i8> %vec6, i8 %res7, i32 7
ret <8 x i8> %vec7 ret <8 x i8> %vec7
} }
define <8 x i8> @test_mask_cmp_q_512(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) { define <8 x i8> @test_mask_cmp_q_512(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {
; CHECK-LABEL: test_mask_cmp_q_512: ; CHECK-LABEL: test_mask_cmp_q_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 {%k1} ; CHECK-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %r8d ; CHECK-NEXT: kmovw %k0, %r8d
; CHECK-NEXT: vpcmpltq %zmm1, %zmm0, %k0 {%k1} ; CHECK-NEXT: vpcmpltq %zmm1, %zmm0, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %r9d ; CHECK-NEXT: kmovw %k0, %r9d
; CHECK-NEXT: vpcmpleq %zmm1, %zmm0, %k0 {%k1} ; CHECK-NEXT: vpcmpleq %zmm1, %zmm0, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %r10d ; CHECK-NEXT: kmovw %k0, %r10d
; CHECK-NEXT: vpcmpunordq %zmm1, %zmm0, %k0 {%k1} ; CHECK-NEXT: vpcmpunordq %zmm1, %zmm0, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %r11d ; CHECK-NEXT: kmovw %k0, %r11d
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%res7 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 7, i8 -1) %res7 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 7, i8 -1)
%vec7 = insertelement <8 x i8> %vec6, i8 %res7, i32 7 %vec7 = insertelement <8 x i8> %vec6, i8 %res7, i32 7
ret <8 x i8> %vec7 ret <8 x i8> %vec7
} }
define <8 x i8> @test_mask_ucmp_q_512(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) { define <8 x i8> @test_mask_ucmp_q_512(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {
; CHECK-LABEL: test_mask_ucmp_q_512: ; CHECK-LABEL: test_mask_ucmp_q_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpcmpequq %zmm1, %zmm0, %k0 {%k1} ; CHECK-NEXT: vpcmpequq %zmm1, %zmm0, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %r8d ; CHECK-NEXT: kmovw %k0, %r8d
; CHECK-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 {%k1} ; CHECK-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %r9d ; CHECK-NEXT: kmovw %k0, %r9d
; CHECK-NEXT: vpcmpleuq %zmm1, %zmm0, %k0 {%k1} ; CHECK-NEXT: vpcmpleuq %zmm1, %zmm0, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %r10d ; CHECK-NEXT: kmovw %k0, %r10d
; CHECK-NEXT: vpcmpunorduq %zmm1, %zmm0, %k0 {%k1} ; CHECK-NEXT: vpcmpunorduq %zmm1, %zmm0, %k0 {%k1}
; CHECK-NEXT: kmovw %k0, %r11d ; CHECK-NEXT: kmovw %k0, %r11d
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; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.pslli.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 -1) %res = call <8 x i64> @llvm.x86.avx512.mask.pslli.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 -1)
ret <8 x i64> %res ret <8 x i64> %res
} }
define <8 x i64> @test_x86_avx512_mask_pslli_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) { define <8 x i64> @test_x86_avx512_mask_pslli_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {
; CHECK-LABEL: test_x86_avx512_mask_pslli_q: ; CHECK-LABEL: test_x86_avx512_mask_pslli_q:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsllq $7, %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vpsllq $7, %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vmovaps %zmm1, %zmm0 ; CHECK-NEXT: vmovaps %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.pslli.q(<8 x i64> %a0, i32 7, <8 x i64> %a1, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.pslli.q(<8 x i64> %a0, i32 7, <8 x i64> %a1, i8 %mask)
ret <8 x i64> %res ret <8 x i64> %res
} }
define <8 x i64> @test_x86_avx512_maskz_pslli_q(<8 x i64> %a0, i8 %mask) { define <8 x i64> @test_x86_avx512_maskz_pslli_q(<8 x i64> %a0, i8 %mask) {
; CHECK-LABEL: test_x86_avx512_maskz_pslli_q: ; CHECK-LABEL: test_x86_avx512_maskz_pslli_q:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsllq $7, %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vpsllq $7, %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.pslli.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.pslli.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 %mask)
ret <8 x i64> %res ret <8 x i64> %res
} }
declare <8 x i64> @llvm.x86.avx512.mask.pslli.q(<8 x i64>, i32, <8 x i64>, i8) nounwind readnone declare <8 x i64> @llvm.x86.avx512.mask.pslli.q(<8 x i64>, i32, <8 x i64>, i8) nounwind readnone
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; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psrli.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 -1) %res = call <8 x i64> @llvm.x86.avx512.mask.psrli.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 -1)
ret <8 x i64> %res ret <8 x i64> %res
} }
define <8 x i64> @test_x86_avx512_mask_psrli_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) { define <8 x i64> @test_x86_avx512_mask_psrli_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {
; CHECK-LABEL: test_x86_avx512_mask_psrli_q: ; CHECK-LABEL: test_x86_avx512_mask_psrli_q:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsrlq $7, %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vpsrlq $7, %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vmovaps %zmm1, %zmm0 ; CHECK-NEXT: vmovaps %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psrli.q(<8 x i64> %a0, i32 7, <8 x i64> %a1, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.psrli.q(<8 x i64> %a0, i32 7, <8 x i64> %a1, i8 %mask)
ret <8 x i64> %res ret <8 x i64> %res
} }
define <8 x i64> @test_x86_avx512_maskz_psrli_q(<8 x i64> %a0, i8 %mask) { define <8 x i64> @test_x86_avx512_maskz_psrli_q(<8 x i64> %a0, i8 %mask) {
; CHECK-LABEL: test_x86_avx512_maskz_psrli_q: ; CHECK-LABEL: test_x86_avx512_maskz_psrli_q:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsrlq $7, %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vpsrlq $7, %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psrli.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.psrli.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 %mask)
ret <8 x i64> %res ret <8 x i64> %res
} }
declare <8 x i64> @llvm.x86.avx512.mask.psrli.q(<8 x i64>, i32, <8 x i64>, i8) nounwind readnone declare <8 x i64> @llvm.x86.avx512.mask.psrli.q(<8 x i64>, i32, <8 x i64>, i8) nounwind readnone
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; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psrai.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 -1) %res = call <8 x i64> @llvm.x86.avx512.mask.psrai.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 -1)
ret <8 x i64> %res ret <8 x i64> %res
} }
define <8 x i64> @test_x86_avx512_mask_psrai_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) { define <8 x i64> @test_x86_avx512_mask_psrai_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {
; CHECK-LABEL: test_x86_avx512_mask_psrai_q: ; CHECK-LABEL: test_x86_avx512_mask_psrai_q:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsraq $7, %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vpsraq $7, %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vmovaps %zmm1, %zmm0 ; CHECK-NEXT: vmovaps %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psrai.q(<8 x i64> %a0, i32 7, <8 x i64> %a1, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.psrai.q(<8 x i64> %a0, i32 7, <8 x i64> %a1, i8 %mask)
ret <8 x i64> %res ret <8 x i64> %res
} }
define <8 x i64> @test_x86_avx512_maskz_psrai_q(<8 x i64> %a0, i8 %mask) { define <8 x i64> @test_x86_avx512_maskz_psrai_q(<8 x i64> %a0, i8 %mask) {
; CHECK-LABEL: test_x86_avx512_maskz_psrai_q: ; CHECK-LABEL: test_x86_avx512_maskz_psrai_q:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsraq $7, %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vpsraq $7, %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psrai.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.psrai.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 %mask)
ret <8 x i64> %res ret <8 x i64> %res
} }
declare <8 x i64> @llvm.x86.avx512.mask.psrai.q(<8 x i64>, i32, <8 x i64>, i8) nounwind readnone declare <8 x i64> @llvm.x86.avx512.mask.psrai.q(<8 x i64>, i32, <8 x i64>, i8) nounwind readnone
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; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psll.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> zeroinitializer, i8 -1) %res = call <8 x i64> @llvm.x86.avx512.mask.psll.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> zeroinitializer, i8 -1)
ret <8 x i64> %res ret <8 x i64> %res
} }
define <8 x i64> @test_x86_avx512_mask_psll_q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %a2, i8 %mask) { define <8 x i64> @test_x86_avx512_mask_psll_q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %a2, i8 %mask) {
; CHECK-LABEL: test_x86_avx512_mask_psll_q: ; CHECK-LABEL: test_x86_avx512_mask_psll_q:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsllq %xmm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vpsllq %xmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vmovaps %zmm2, %zmm0 ; CHECK-NEXT: vmovaps %zmm2, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psll.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %a2, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.psll.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %a2, i8 %mask)
ret <8 x i64> %res ret <8 x i64> %res
} }
define <8 x i64> @test_x86_avx512_maskz_psll_q(<8 x i64> %a0, <2 x i64> %a1, i8 %mask) { define <8 x i64> @test_x86_avx512_maskz_psll_q(<8 x i64> %a0, <2 x i64> %a1, i8 %mask) {
; CHECK-LABEL: test_x86_avx512_maskz_psll_q: ; CHECK-LABEL: test_x86_avx512_maskz_psll_q:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsllq %xmm1, %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vpsllq %xmm1, %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psll.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> zeroinitializer, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.psll.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> zeroinitializer, i8 %mask)
ret <8 x i64> %res ret <8 x i64> %res
} }
declare <8 x i64> @llvm.x86.avx512.mask.psll.q(<8 x i64>, <2 x i64>, <8 x i64>, i8) nounwind readnone declare <8 x i64> @llvm.x86.avx512.mask.psll.q(<8 x i64>, <2 x i64>, <8 x i64>, i8) nounwind readnone
Show All 36 Lines
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psrl.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> zeroinitializer, i8 -1) %res = call <8 x i64> @llvm.x86.avx512.mask.psrl.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> zeroinitializer, i8 -1)
ret <8 x i64> %res ret <8 x i64> %res
} }
define <8 x i64> @test_x86_avx512_mask_psrl_q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %a2, i8 %mask) { define <8 x i64> @test_x86_avx512_mask_psrl_q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %a2, i8 %mask) {
; CHECK-LABEL: test_x86_avx512_mask_psrl_q: ; CHECK-LABEL: test_x86_avx512_mask_psrl_q:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsrlq %xmm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vpsrlq %xmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vmovaps %zmm2, %zmm0 ; CHECK-NEXT: vmovaps %zmm2, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psrl.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %a2, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.psrl.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %a2, i8 %mask)
ret <8 x i64> %res ret <8 x i64> %res
} }
define <8 x i64> @test_x86_avx512_maskz_psrl_q(<8 x i64> %a0, <2 x i64> %a1, i8 %mask) { define <8 x i64> @test_x86_avx512_maskz_psrl_q(<8 x i64> %a0, <2 x i64> %a1, i8 %mask) {
; CHECK-LABEL: test_x86_avx512_maskz_psrl_q: ; CHECK-LABEL: test_x86_avx512_maskz_psrl_q:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsrlq %xmm1, %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vpsrlq %xmm1, %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psrl.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> zeroinitializer, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.psrl.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> zeroinitializer, i8 %mask)
ret <8 x i64> %res ret <8 x i64> %res
} }
declare <8 x i64> @llvm.x86.avx512.mask.psrl.q(<8 x i64>, <2 x i64>, <8 x i64>, i8) nounwind readnone declare <8 x i64> @llvm.x86.avx512.mask.psrl.q(<8 x i64>, <2 x i64>, <8 x i64>, i8) nounwind readnone
Show All 36 Lines
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psra.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> zeroinitializer, i8 -1) %res = call <8 x i64> @llvm.x86.avx512.mask.psra.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> zeroinitializer, i8 -1)
ret <8 x i64> %res ret <8 x i64> %res
} }
define <8 x i64> @test_x86_avx512_mask_psra_q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %a2, i8 %mask) { define <8 x i64> @test_x86_avx512_mask_psra_q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %a2, i8 %mask) {
; CHECK-LABEL: test_x86_avx512_mask_psra_q: ; CHECK-LABEL: test_x86_avx512_mask_psra_q:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsraq %xmm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vpsraq %xmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vmovaps %zmm2, %zmm0 ; CHECK-NEXT: vmovaps %zmm2, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psra.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %a2, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.psra.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %a2, i8 %mask)
ret <8 x i64> %res ret <8 x i64> %res
} }
define <8 x i64> @test_x86_avx512_maskz_psra_q(<8 x i64> %a0, <2 x i64> %a1, i8 %mask) { define <8 x i64> @test_x86_avx512_maskz_psra_q(<8 x i64> %a0, <2 x i64> %a1, i8 %mask) {
; CHECK-LABEL: test_x86_avx512_maskz_psra_q: ; CHECK-LABEL: test_x86_avx512_maskz_psra_q:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsraq %xmm1, %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vpsraq %xmm1, %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psra.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> zeroinitializer, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.psra.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> zeroinitializer, i8 %mask)
ret <8 x i64> %res ret <8 x i64> %res
} }
declare <8 x i64> @llvm.x86.avx512.mask.psra.q(<8 x i64>, <2 x i64>, <8 x i64>, i8) nounwind readnone declare <8 x i64> @llvm.x86.avx512.mask.psra.q(<8 x i64>, <2 x i64>, <8 x i64>, i8) nounwind readnone
Show All 36 Lines
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psllv.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> zeroinitializer, i8 -1) %res = call <8 x i64> @llvm.x86.avx512.mask.psllv.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> zeroinitializer, i8 -1)
ret <8 x i64> %res ret <8 x i64> %res
} }
define <8 x i64> @test_x86_avx512_mask_psllv_q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> %a2, i8 %mask) { define <8 x i64> @test_x86_avx512_mask_psllv_q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> %a2, i8 %mask) {
; CHECK-LABEL: test_x86_avx512_mask_psllv_q: ; CHECK-LABEL: test_x86_avx512_mask_psllv_q:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsllvq %zmm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vpsllvq %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vmovaps %zmm2, %zmm0 ; CHECK-NEXT: vmovaps %zmm2, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psllv.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> %a2, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.psllv.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> %a2, i8 %mask)
ret <8 x i64> %res ret <8 x i64> %res
} }
define <8 x i64> @test_x86_avx512_maskz_psllv_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) { define <8 x i64> @test_x86_avx512_maskz_psllv_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {
; CHECK-LABEL: test_x86_avx512_maskz_psllv_q: ; CHECK-LABEL: test_x86_avx512_maskz_psllv_q:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsllvq %zmm1, %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vpsllvq %zmm1, %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psllv.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> zeroinitializer, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.psllv.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> zeroinitializer, i8 %mask)
ret <8 x i64> %res ret <8 x i64> %res
} }
declare <8 x i64> @llvm.x86.avx512.mask.psllv.q(<8 x i64>, <8 x i64>, <8 x i64>, i8) nounwind readnone declare <8 x i64> @llvm.x86.avx512.mask.psllv.q(<8 x i64>, <8 x i64>, <8 x i64>, i8) nounwind readnone
Show All 37 Lines
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psrav.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> zeroinitializer, i8 -1) %res = call <8 x i64> @llvm.x86.avx512.mask.psrav.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> zeroinitializer, i8 -1)
ret <8 x i64> %res ret <8 x i64> %res
} }
define <8 x i64> @test_x86_avx512_mask_psrav_q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> %a2, i8 %mask) { define <8 x i64> @test_x86_avx512_mask_psrav_q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> %a2, i8 %mask) {
; CHECK-LABEL: test_x86_avx512_mask_psrav_q: ; CHECK-LABEL: test_x86_avx512_mask_psrav_q:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsravq %zmm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vpsravq %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vmovaps %zmm2, %zmm0 ; CHECK-NEXT: vmovaps %zmm2, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psrav.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> %a2, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.psrav.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> %a2, i8 %mask)
ret <8 x i64> %res ret <8 x i64> %res
} }
define <8 x i64> @test_x86_avx512_maskz_psrav_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) { define <8 x i64> @test_x86_avx512_maskz_psrav_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {
; CHECK-LABEL: test_x86_avx512_maskz_psrav_q: ; CHECK-LABEL: test_x86_avx512_maskz_psrav_q:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsravq %zmm1, %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vpsravq %zmm1, %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psrav.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> zeroinitializer, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.psrav.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> zeroinitializer, i8 %mask)
ret <8 x i64> %res ret <8 x i64> %res
} }
declare <8 x i64> @llvm.x86.avx512.mask.psrav.q(<8 x i64>, <8 x i64>, <8 x i64>, i8) nounwind readnone declare <8 x i64> @llvm.x86.avx512.mask.psrav.q(<8 x i64>, <8 x i64>, <8 x i64>, i8) nounwind readnone
Show All 36 Lines
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psrlv.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> zeroinitializer, i8 -1) %res = call <8 x i64> @llvm.x86.avx512.mask.psrlv.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> zeroinitializer, i8 -1)
ret <8 x i64> %res ret <8 x i64> %res
} }
define <8 x i64> @test_x86_avx512_mask_psrlv_q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> %a2, i8 %mask) { define <8 x i64> @test_x86_avx512_mask_psrlv_q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> %a2, i8 %mask) {
; CHECK-LABEL: test_x86_avx512_mask_psrlv_q: ; CHECK-LABEL: test_x86_avx512_mask_psrlv_q:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsrlvq %zmm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vpsrlvq %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vmovaps %zmm2, %zmm0 ; CHECK-NEXT: vmovaps %zmm2, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psrlv.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> %a2, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.psrlv.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> %a2, i8 %mask)
ret <8 x i64> %res ret <8 x i64> %res
} }
define <8 x i64> @test_x86_avx512_maskz_psrlv_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) { define <8 x i64> @test_x86_avx512_maskz_psrlv_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {
; CHECK-LABEL: test_x86_avx512_maskz_psrlv_q: ; CHECK-LABEL: test_x86_avx512_maskz_psrlv_q:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsrlvq %zmm1, %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vpsrlvq %zmm1, %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psrlv.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> zeroinitializer, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.psrlv.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> zeroinitializer, i8 %mask)
ret <8 x i64> %res ret <8 x i64> %res
} }
declare <8 x i64> @llvm.x86.avx512.mask.psrlv.q(<8 x i64>, <8 x i64>, <8 x i64>, i8) nounwind readnone declare <8 x i64> @llvm.x86.avx512.mask.psrlv.q(<8 x i64>, <8 x i64>, <8 x i64>, i8) nounwind readnone
▲ Show 20 Lines • Show All 184 Lines • ▼ Show 20 Lines %res = call <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float> %a0, <16 x float> %a1,
<16 x float> %passthru, i16 %mask, i32 3) <16 x float> %passthru, i16 %mask, i32 3)
ret <16 x float> %res ret <16 x float> %res
} }
;; mask double ;; mask double
define <8 x double> @test_vmulpd_mask_rn(<8 x double> %a0, <8 x double> %a1, i8 %mask) { define <8 x double> @test_vmulpd_mask_rn(<8 x double> %a0, <8 x double> %a1, i8 %mask) {
; CHECK-LABEL: test_vmulpd_mask_rn: ; CHECK-LABEL: test_vmulpd_mask_rn:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmulpd {rn-sae}, %zmm1, %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vmulpd {rn-sae}, %zmm1, %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.mul.pd.512(<8 x double> %a0, <8 x double> %a1, %res = call <8 x double> @llvm.x86.avx512.mask.mul.pd.512(<8 x double> %a0, <8 x double> %a1,
<8 x double> zeroinitializer, i8 %mask, i32 0) <8 x double> zeroinitializer, i8 %mask, i32 0)
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double> @test_vmulpd_mask_rd(<8 x double> %a0, <8 x double> %a1, i8 %mask) { define <8 x double> @test_vmulpd_mask_rd(<8 x double> %a0, <8 x double> %a1, i8 %mask) {
; CHECK-LABEL: test_vmulpd_mask_rd: ; CHECK-LABEL: test_vmulpd_mask_rd:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmulpd {rd-sae}, %zmm1, %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vmulpd {rd-sae}, %zmm1, %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.mul.pd.512(<8 x double> %a0, <8 x double> %a1, %res = call <8 x double> @llvm.x86.avx512.mask.mul.pd.512(<8 x double> %a0, <8 x double> %a1,
<8 x double> zeroinitializer, i8 %mask, i32 1) <8 x double> zeroinitializer, i8 %mask, i32 1)
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double> @test_vmulpd_mask_ru(<8 x double> %a0, <8 x double> %a1, i8 %mask) { define <8 x double> @test_vmulpd_mask_ru(<8 x double> %a0, <8 x double> %a1, i8 %mask) {
; CHECK-LABEL: test_vmulpd_mask_ru: ; CHECK-LABEL: test_vmulpd_mask_ru:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmulpd {ru-sae}, %zmm1, %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vmulpd {ru-sae}, %zmm1, %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.mul.pd.512(<8 x double> %a0, <8 x double> %a1, %res = call <8 x double> @llvm.x86.avx512.mask.mul.pd.512(<8 x double> %a0, <8 x double> %a1,
<8 x double> zeroinitializer, i8 %mask, i32 2) <8 x double> zeroinitializer, i8 %mask, i32 2)
ret <8 x double> %res ret <8 x double> %res
} }
define <8 x double> @test_vmulpd_mask_rz(<8 x double> %a0, <8 x double> %a1, i8 %mask) { define <8 x double> @test_vmulpd_mask_rz(<8 x double> %a0, <8 x double> %a1, i8 %mask) {
; CHECK-LABEL: test_vmulpd_mask_rz: ; CHECK-LABEL: test_vmulpd_mask_rz:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmulpd {rz-sae}, %zmm1, %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vmulpd {rz-sae}, %zmm1, %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.mul.pd.512(<8 x double> %a0, <8 x double> %a1, %res = call <8 x double> @llvm.x86.avx512.mask.mul.pd.512(<8 x double> %a0, <8 x double> %a1,
<8 x double> zeroinitializer, i8 %mask, i32 3) <8 x double> zeroinitializer, i8 %mask, i32 3)
ret <8 x double> %res ret <8 x double> %res
} }
define <16 x i32> @test_xor_epi32(<16 x i32> %a, <16 x i32> %b) { define <16 x i32> @test_xor_epi32(<16 x i32> %a, <16 x i32> %b) {
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; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.pxor.q.512(<8 x i64> %a,<8 x i64> %b, <8 x i64>zeroinitializer, i8 -1) %res = call <8 x i64> @llvm.x86.avx512.mask.pxor.q.512(<8 x i64> %a,<8 x i64> %b, <8 x i64>zeroinitializer, i8 -1)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_xor_epi64(<8 x i64> %a,<8 x i64> %b, <8 x i64> %passThru, i8 %mask) { define <8 x i64> @test_mask_xor_epi64(<8 x i64> %a,<8 x i64> %b, <8 x i64> %passThru, i8 %mask) {
; CHECK-LABEL: test_mask_xor_epi64: ; CHECK-LABEL: test_mask_xor_epi64:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpxorq %zmm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vpxorq %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vmovaps %zmm2, %zmm0 ; CHECK-NEXT: vmovaps %zmm2, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.pxor.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.pxor.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
declare <8 x i64> @llvm.x86.avx512.mask.pxor.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.pxor.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
define <8 x i64> @test_or_epi64(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @test_or_epi64(<8 x i64> %a, <8 x i64> %b) {
; CHECK-LABEL: test_or_epi64: ; CHECK-LABEL: test_or_epi64:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: vporq %zmm1, %zmm0, %zmm0 ; CHECK-NEXT: vporq %zmm1, %zmm0, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.por.q.512(<8 x i64> %a,<8 x i64> %b, <8 x i64>zeroinitializer, i8 -1) %res = call <8 x i64> @llvm.x86.avx512.mask.por.q.512(<8 x i64> %a,<8 x i64> %b, <8 x i64>zeroinitializer, i8 -1)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_or_epi64(<8 x i64> %a,<8 x i64> %b, <8 x i64> %passThru, i8 %mask) { define <8 x i64> @test_mask_or_epi64(<8 x i64> %a,<8 x i64> %b, <8 x i64> %passThru, i8 %mask) {
; CHECK-LABEL: test_mask_or_epi64: ; CHECK-LABEL: test_mask_or_epi64:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vporq %zmm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vporq %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vmovaps %zmm2, %zmm0 ; CHECK-NEXT: vmovaps %zmm2, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.por.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.por.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
declare <8 x i64> @llvm.x86.avx512.mask.por.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.por.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
define <8 x i64> @test_and_epi64(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @test_and_epi64(<8 x i64> %a, <8 x i64> %b) {
; CHECK-LABEL: test_and_epi64: ; CHECK-LABEL: test_and_epi64:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: vpandq %zmm1, %zmm0, %zmm0 ; CHECK-NEXT: vpandq %zmm1, %zmm0, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.pand.q.512(<8 x i64> %a,<8 x i64> %b, <8 x i64>zeroinitializer, i8 -1) %res = call <8 x i64> @llvm.x86.avx512.mask.pand.q.512(<8 x i64> %a,<8 x i64> %b, <8 x i64>zeroinitializer, i8 -1)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_and_epi64(<8 x i64> %a,<8 x i64> %b, <8 x i64> %passThru, i8 %mask) { define <8 x i64> @test_mask_and_epi64(<8 x i64> %a,<8 x i64> %b, <8 x i64> %passThru, i8 %mask) {
; CHECK-LABEL: test_mask_and_epi64: ; CHECK-LABEL: test_mask_and_epi64:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpandq %zmm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vpandq %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vmovaps %zmm2, %zmm0 ; CHECK-NEXT: vmovaps %zmm2, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.pand.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.pand.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
declare <8 x i64> @llvm.x86.avx512.mask.pand.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.pand.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
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; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1) %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_add_epi64_rrk(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask) { define <8 x i64> @test_mask_add_epi64_rrk(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask) {
; CHECK-LABEL: test_mask_add_epi64_rrk: ; CHECK-LABEL: test_mask_add_epi64_rrk:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpaddq %zmm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vpaddq %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vmovaps %zmm2, %zmm0 ; CHECK-NEXT: vmovaps %zmm2, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_add_epi64_rrkz(<8 x i64> %a, <8 x i64> %b, i8 %mask) { define <8 x i64> @test_mask_add_epi64_rrkz(<8 x i64> %a, <8 x i64> %b, i8 %mask) {
; CHECK-LABEL: test_mask_add_epi64_rrkz: ; CHECK-LABEL: test_mask_add_epi64_rrkz:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpaddq %zmm1, %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vpaddq %zmm1, %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_add_epi64_rm(<8 x i64> %a, <8 x i64>* %ptr_b) { define <8 x i64> @test_mask_add_epi64_rm(<8 x i64> %a, <8 x i64>* %ptr_b) {
; CHECK-LABEL: test_mask_add_epi64_rm: ; CHECK-LABEL: test_mask_add_epi64_rm:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: vpaddq (%rdi), %zmm0, %zmm0 ; CHECK-NEXT: vpaddq (%rdi), %zmm0, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%b = load <8 x i64>, <8 x i64>* %ptr_b %b = load <8 x i64>, <8 x i64>* %ptr_b
%res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1) %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_add_epi64_rmk(<8 x i64> %a, <8 x i64>* %ptr_b, <8 x i64> %passThru, i8 %mask) { define <8 x i64> @test_mask_add_epi64_rmk(<8 x i64> %a, <8 x i64>* %ptr_b, <8 x i64> %passThru, i8 %mask) {
; CHECK-LABEL: test_mask_add_epi64_rmk: ; CHECK-LABEL: test_mask_add_epi64_rmk:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpaddq (%rdi), %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vpaddq (%rdi), %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vmovaps %zmm1, %zmm0 ; CHECK-NEXT: vmovaps %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%b = load <8 x i64>, <8 x i64>* %ptr_b %b = load <8 x i64>, <8 x i64>* %ptr_b
%res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_add_epi64_rmkz(<8 x i64> %a, <8 x i64>* %ptr_b, i8 %mask) { define <8 x i64> @test_mask_add_epi64_rmkz(<8 x i64> %a, <8 x i64>* %ptr_b, i8 %mask) {
; CHECK-LABEL: test_mask_add_epi64_rmkz: ; CHECK-LABEL: test_mask_add_epi64_rmkz:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpaddq (%rdi), %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vpaddq (%rdi), %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%b = load <8 x i64>, <8 x i64>* %ptr_b %b = load <8 x i64>, <8 x i64>* %ptr_b
%res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_add_epi64_rmb(<8 x i64> %a, i64* %ptr_b) { define <8 x i64> @test_mask_add_epi64_rmb(<8 x i64> %a, i64* %ptr_b) {
; CHECK-LABEL: test_mask_add_epi64_rmb: ; CHECK-LABEL: test_mask_add_epi64_rmb:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: vpaddq (%rdi){1to8}, %zmm0, %zmm0 ; CHECK-NEXT: vpaddq (%rdi){1to8}, %zmm0, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%q = load i64, i64* %ptr_b %q = load i64, i64* %ptr_b
%vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0 %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
%b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer %b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
%res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1) %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_add_epi64_rmbk(<8 x i64> %a, i64* %ptr_b, <8 x i64> %passThru, i8 %mask) { define <8 x i64> @test_mask_add_epi64_rmbk(<8 x i64> %a, i64* %ptr_b, <8 x i64> %passThru, i8 %mask) {
; CHECK-LABEL: test_mask_add_epi64_rmbk: ; CHECK-LABEL: test_mask_add_epi64_rmbk:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpaddq (%rdi){1to8}, %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vpaddq (%rdi){1to8}, %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vmovaps %zmm1, %zmm0 ; CHECK-NEXT: vmovaps %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%q = load i64, i64* %ptr_b %q = load i64, i64* %ptr_b
%vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0 %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
%b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer %b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
%res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_add_epi64_rmbkz(<8 x i64> %a, i64* %ptr_b, i8 %mask) { define <8 x i64> @test_mask_add_epi64_rmbkz(<8 x i64> %a, i64* %ptr_b, i8 %mask) {
; CHECK-LABEL: test_mask_add_epi64_rmbkz: ; CHECK-LABEL: test_mask_add_epi64_rmbkz:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpaddq (%rdi){1to8}, %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vpaddq (%rdi){1to8}, %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%q = load i64, i64* %ptr_b %q = load i64, i64* %ptr_b
%vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0 %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
%b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer %b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
%res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
declare <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
define <8 x i64> @test_mask_sub_epi64_rr(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @test_mask_sub_epi64_rr(<8 x i64> %a, <8 x i64> %b) {
; CHECK-LABEL: test_mask_sub_epi64_rr: ; CHECK-LABEL: test_mask_sub_epi64_rr:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: vpsubq %zmm1, %zmm0, %zmm0 ; CHECK-NEXT: vpsubq %zmm1, %zmm0, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1) %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_sub_epi64_rrk(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask) { define <8 x i64> @test_mask_sub_epi64_rrk(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask) {
; CHECK-LABEL: test_mask_sub_epi64_rrk: ; CHECK-LABEL: test_mask_sub_epi64_rrk:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsubq %zmm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vpsubq %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vmovaps %zmm2, %zmm0 ; CHECK-NEXT: vmovaps %zmm2, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_sub_epi64_rrkz(<8 x i64> %a, <8 x i64> %b, i8 %mask) { define <8 x i64> @test_mask_sub_epi64_rrkz(<8 x i64> %a, <8 x i64> %b, i8 %mask) {
; CHECK-LABEL: test_mask_sub_epi64_rrkz: ; CHECK-LABEL: test_mask_sub_epi64_rrkz:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsubq %zmm1, %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vpsubq %zmm1, %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_sub_epi64_rm(<8 x i64> %a, <8 x i64>* %ptr_b) { define <8 x i64> @test_mask_sub_epi64_rm(<8 x i64> %a, <8 x i64>* %ptr_b) {
; CHECK-LABEL: test_mask_sub_epi64_rm: ; CHECK-LABEL: test_mask_sub_epi64_rm:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: vpsubq (%rdi), %zmm0, %zmm0 ; CHECK-NEXT: vpsubq (%rdi), %zmm0, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%b = load <8 x i64>, <8 x i64>* %ptr_b %b = load <8 x i64>, <8 x i64>* %ptr_b
%res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1) %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_sub_epi64_rmk(<8 x i64> %a, <8 x i64>* %ptr_b, <8 x i64> %passThru, i8 %mask) { define <8 x i64> @test_mask_sub_epi64_rmk(<8 x i64> %a, <8 x i64>* %ptr_b, <8 x i64> %passThru, i8 %mask) {
; CHECK-LABEL: test_mask_sub_epi64_rmk: ; CHECK-LABEL: test_mask_sub_epi64_rmk:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsubq (%rdi), %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vpsubq (%rdi), %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vmovaps %zmm1, %zmm0 ; CHECK-NEXT: vmovaps %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%b = load <8 x i64>, <8 x i64>* %ptr_b %b = load <8 x i64>, <8 x i64>* %ptr_b
%res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_sub_epi64_rmkz(<8 x i64> %a, <8 x i64>* %ptr_b, i8 %mask) { define <8 x i64> @test_mask_sub_epi64_rmkz(<8 x i64> %a, <8 x i64>* %ptr_b, i8 %mask) {
; CHECK-LABEL: test_mask_sub_epi64_rmkz: ; CHECK-LABEL: test_mask_sub_epi64_rmkz:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsubq (%rdi), %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vpsubq (%rdi), %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%b = load <8 x i64>, <8 x i64>* %ptr_b %b = load <8 x i64>, <8 x i64>* %ptr_b
%res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_sub_epi64_rmb(<8 x i64> %a, i64* %ptr_b) { define <8 x i64> @test_mask_sub_epi64_rmb(<8 x i64> %a, i64* %ptr_b) {
; CHECK-LABEL: test_mask_sub_epi64_rmb: ; CHECK-LABEL: test_mask_sub_epi64_rmb:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: vpsubq (%rdi){1to8}, %zmm0, %zmm0 ; CHECK-NEXT: vpsubq (%rdi){1to8}, %zmm0, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%q = load i64, i64* %ptr_b %q = load i64, i64* %ptr_b
%vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0 %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
%b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer %b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
%res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1) %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_sub_epi64_rmbk(<8 x i64> %a, i64* %ptr_b, <8 x i64> %passThru, i8 %mask) { define <8 x i64> @test_mask_sub_epi64_rmbk(<8 x i64> %a, i64* %ptr_b, <8 x i64> %passThru, i8 %mask) {
; CHECK-LABEL: test_mask_sub_epi64_rmbk: ; CHECK-LABEL: test_mask_sub_epi64_rmbk:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsubq (%rdi){1to8}, %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vpsubq (%rdi){1to8}, %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vmovaps %zmm1, %zmm0 ; CHECK-NEXT: vmovaps %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%q = load i64, i64* %ptr_b %q = load i64, i64* %ptr_b
%vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0 %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
%b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer %b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
%res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_sub_epi64_rmbkz(<8 x i64> %a, i64* %ptr_b, i8 %mask) { define <8 x i64> @test_mask_sub_epi64_rmbkz(<8 x i64> %a, i64* %ptr_b, i8 %mask) {
; CHECK-LABEL: test_mask_sub_epi64_rmbkz: ; CHECK-LABEL: test_mask_sub_epi64_rmbkz:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsubq (%rdi){1to8}, %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vpsubq (%rdi){1to8}, %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%q = load i64, i64* %ptr_b %q = load i64, i64* %ptr_b
%vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0 %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
%b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer %b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
%res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
declare <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
define <8 x i64> @test_mask_mul_epi32_rr(<16 x i32> %a, <16 x i32> %b) { define <8 x i64> @test_mask_mul_epi32_rr(<16 x i32> %a, <16 x i32> %b) {
; CHECK-LABEL: test_mask_mul_epi32_rr: ; CHECK-LABEL: test_mask_mul_epi32_rr:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: vpmuldq %zmm1, %zmm0, %zmm0 ; CHECK-NEXT: vpmuldq %zmm1, %zmm0, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 -1) %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 -1)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_mul_epi32_rrk(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask) { define <8 x i64> @test_mask_mul_epi32_rrk(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask) {
; CHECK-LABEL: test_mask_mul_epi32_rrk: ; CHECK-LABEL: test_mask_mul_epi32_rrk:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmuldq %zmm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vpmuldq %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vmovaps %zmm2, %zmm0 ; CHECK-NEXT: vmovaps %zmm2, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_mul_epi32_rrkz(<16 x i32> %a, <16 x i32> %b, i8 %mask) { define <8 x i64> @test_mask_mul_epi32_rrkz(<16 x i32> %a, <16 x i32> %b, i8 %mask) {
; CHECK-LABEL: test_mask_mul_epi32_rrkz: ; CHECK-LABEL: test_mask_mul_epi32_rrkz:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmuldq %zmm1, %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vpmuldq %zmm1, %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_mul_epi32_rm(<16 x i32> %a, <16 x i32>* %ptr_b) { define <8 x i64> @test_mask_mul_epi32_rm(<16 x i32> %a, <16 x i32>* %ptr_b) {
; CHECK-LABEL: test_mask_mul_epi32_rm: ; CHECK-LABEL: test_mask_mul_epi32_rm:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: vpmuldq (%rdi), %zmm0, %zmm0 ; CHECK-NEXT: vpmuldq (%rdi), %zmm0, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%b = load <16 x i32>, <16 x i32>* %ptr_b %b = load <16 x i32>, <16 x i32>* %ptr_b
%res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 -1) %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 -1)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_mul_epi32_rmk(<16 x i32> %a, <16 x i32>* %ptr_b, <8 x i64> %passThru, i8 %mask) { define <8 x i64> @test_mask_mul_epi32_rmk(<16 x i32> %a, <16 x i32>* %ptr_b, <8 x i64> %passThru, i8 %mask) {
; CHECK-LABEL: test_mask_mul_epi32_rmk: ; CHECK-LABEL: test_mask_mul_epi32_rmk:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmuldq (%rdi), %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vpmuldq (%rdi), %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vmovaps %zmm1, %zmm0 ; CHECK-NEXT: vmovaps %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%b = load <16 x i32>, <16 x i32>* %ptr_b %b = load <16 x i32>, <16 x i32>* %ptr_b
%res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_mul_epi32_rmkz(<16 x i32> %a, <16 x i32>* %ptr_b, i8 %mask) { define <8 x i64> @test_mask_mul_epi32_rmkz(<16 x i32> %a, <16 x i32>* %ptr_b, i8 %mask) {
; CHECK-LABEL: test_mask_mul_epi32_rmkz: ; CHECK-LABEL: test_mask_mul_epi32_rmkz:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmuldq (%rdi), %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vpmuldq (%rdi), %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%b = load <16 x i32>, <16 x i32>* %ptr_b %b = load <16 x i32>, <16 x i32>* %ptr_b
%res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_mul_epi32_rmb(<16 x i32> %a, i64* %ptr_b) { define <8 x i64> @test_mask_mul_epi32_rmb(<16 x i32> %a, i64* %ptr_b) {
; CHECK-LABEL: test_mask_mul_epi32_rmb: ; CHECK-LABEL: test_mask_mul_epi32_rmb:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: vpmuldq (%rdi){1to8}, %zmm0, %zmm0 ; CHECK-NEXT: vpmuldq (%rdi){1to8}, %zmm0, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%q = load i64, i64* %ptr_b %q = load i64, i64* %ptr_b
%vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0 %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
%b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
%b = bitcast <8 x i64> %b64 to <16 x i32> %b = bitcast <8 x i64> %b64 to <16 x i32>
%res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 -1) %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 -1)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_mul_epi32_rmbk(<16 x i32> %a, i64* %ptr_b, <8 x i64> %passThru, i8 %mask) { define <8 x i64> @test_mask_mul_epi32_rmbk(<16 x i32> %a, i64* %ptr_b, <8 x i64> %passThru, i8 %mask) {
; CHECK-LABEL: test_mask_mul_epi32_rmbk: ; CHECK-LABEL: test_mask_mul_epi32_rmbk:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmuldq (%rdi){1to8}, %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vpmuldq (%rdi){1to8}, %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vmovaps %zmm1, %zmm0 ; CHECK-NEXT: vmovaps %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%q = load i64, i64* %ptr_b %q = load i64, i64* %ptr_b
%vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0 %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
%b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
%b = bitcast <8 x i64> %b64 to <16 x i32> %b = bitcast <8 x i64> %b64 to <16 x i32>
%res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_mul_epi32_rmbkz(<16 x i32> %a, i64* %ptr_b, i8 %mask) { define <8 x i64> @test_mask_mul_epi32_rmbkz(<16 x i32> %a, i64* %ptr_b, i8 %mask) {
; CHECK-LABEL: test_mask_mul_epi32_rmbkz: ; CHECK-LABEL: test_mask_mul_epi32_rmbkz:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmuldq (%rdi){1to8}, %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vpmuldq (%rdi){1to8}, %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%q = load i64, i64* %ptr_b %q = load i64, i64* %ptr_b
%vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0 %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
%b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
%b = bitcast <8 x i64> %b64 to <16 x i32> %b = bitcast <8 x i64> %b64 to <16 x i32>
%res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
declare <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32>, <16 x i32>, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32>, <16 x i32>, <8 x i64>, i8)
define <8 x i64> @test_mask_mul_epu32_rr(<16 x i32> %a, <16 x i32> %b) { define <8 x i64> @test_mask_mul_epu32_rr(<16 x i32> %a, <16 x i32> %b) {
; CHECK-LABEL: test_mask_mul_epu32_rr: ; CHECK-LABEL: test_mask_mul_epu32_rr:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: vpmuludq %zmm1, %zmm0, %zmm0 ; CHECK-NEXT: vpmuludq %zmm1, %zmm0, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 -1) %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 -1)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_mul_epu32_rrk(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask) { define <8 x i64> @test_mask_mul_epu32_rrk(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask) {
; CHECK-LABEL: test_mask_mul_epu32_rrk: ; CHECK-LABEL: test_mask_mul_epu32_rrk:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmuludq %zmm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vpmuludq %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vmovaps %zmm2, %zmm0 ; CHECK-NEXT: vmovaps %zmm2, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_mul_epu32_rrkz(<16 x i32> %a, <16 x i32> %b, i8 %mask) { define <8 x i64> @test_mask_mul_epu32_rrkz(<16 x i32> %a, <16 x i32> %b, i8 %mask) {
; CHECK-LABEL: test_mask_mul_epu32_rrkz: ; CHECK-LABEL: test_mask_mul_epu32_rrkz:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmuludq %zmm1, %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vpmuludq %zmm1, %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_mul_epu32_rm(<16 x i32> %a, <16 x i32>* %ptr_b) { define <8 x i64> @test_mask_mul_epu32_rm(<16 x i32> %a, <16 x i32>* %ptr_b) {
; CHECK-LABEL: test_mask_mul_epu32_rm: ; CHECK-LABEL: test_mask_mul_epu32_rm:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: vpmuludq (%rdi), %zmm0, %zmm0 ; CHECK-NEXT: vpmuludq (%rdi), %zmm0, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%b = load <16 x i32>, <16 x i32>* %ptr_b %b = load <16 x i32>, <16 x i32>* %ptr_b
%res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 -1) %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 -1)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_mul_epu32_rmk(<16 x i32> %a, <16 x i32>* %ptr_b, <8 x i64> %passThru, i8 %mask) { define <8 x i64> @test_mask_mul_epu32_rmk(<16 x i32> %a, <16 x i32>* %ptr_b, <8 x i64> %passThru, i8 %mask) {
; CHECK-LABEL: test_mask_mul_epu32_rmk: ; CHECK-LABEL: test_mask_mul_epu32_rmk:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmuludq (%rdi), %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vpmuludq (%rdi), %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vmovaps %zmm1, %zmm0 ; CHECK-NEXT: vmovaps %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%b = load <16 x i32>, <16 x i32>* %ptr_b %b = load <16 x i32>, <16 x i32>* %ptr_b
%res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_mul_epu32_rmkz(<16 x i32> %a, <16 x i32>* %ptr_b, i8 %mask) { define <8 x i64> @test_mask_mul_epu32_rmkz(<16 x i32> %a, <16 x i32>* %ptr_b, i8 %mask) {
; CHECK-LABEL: test_mask_mul_epu32_rmkz: ; CHECK-LABEL: test_mask_mul_epu32_rmkz:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmuludq (%rdi), %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vpmuludq (%rdi), %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%b = load <16 x i32>, <16 x i32>* %ptr_b %b = load <16 x i32>, <16 x i32>* %ptr_b
%res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_mul_epu32_rmb(<16 x i32> %a, i64* %ptr_b) { define <8 x i64> @test_mask_mul_epu32_rmb(<16 x i32> %a, i64* %ptr_b) {
; CHECK-LABEL: test_mask_mul_epu32_rmb: ; CHECK-LABEL: test_mask_mul_epu32_rmb:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: vpmuludq (%rdi){1to8}, %zmm0, %zmm0 ; CHECK-NEXT: vpmuludq (%rdi){1to8}, %zmm0, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%q = load i64, i64* %ptr_b %q = load i64, i64* %ptr_b
%vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0 %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
%b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
%b = bitcast <8 x i64> %b64 to <16 x i32> %b = bitcast <8 x i64> %b64 to <16 x i32>
%res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 -1) %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 -1)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_mul_epu32_rmbk(<16 x i32> %a, i64* %ptr_b, <8 x i64> %passThru, i8 %mask) { define <8 x i64> @test_mask_mul_epu32_rmbk(<16 x i32> %a, i64* %ptr_b, <8 x i64> %passThru, i8 %mask) {
; CHECK-LABEL: test_mask_mul_epu32_rmbk: ; CHECK-LABEL: test_mask_mul_epu32_rmbk:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmuludq (%rdi){1to8}, %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vpmuludq (%rdi){1to8}, %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vmovaps %zmm1, %zmm0 ; CHECK-NEXT: vmovaps %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%q = load i64, i64* %ptr_b %q = load i64, i64* %ptr_b
%vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0 %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
%b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
%b = bitcast <8 x i64> %b64 to <16 x i32> %b = bitcast <8 x i64> %b64 to <16 x i32>
%res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
} }
define <8 x i64> @test_mask_mul_epu32_rmbkz(<16 x i32> %a, i64* %ptr_b, i8 %mask) { define <8 x i64> @test_mask_mul_epu32_rmbkz(<16 x i32> %a, i64* %ptr_b, i8 %mask) {
; CHECK-LABEL: test_mask_mul_epu32_rmbkz: ; CHECK-LABEL: test_mask_mul_epu32_rmbkz:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmuludq (%rdi){1to8}, %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vpmuludq (%rdi){1to8}, %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%q = load i64, i64* %ptr_b %q = load i64, i64* %ptr_b
%vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0 %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
%b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
%b = bitcast <8 x i64> %b64 to <16 x i32> %b = bitcast <8 x i64> %b64 to <16 x i32>
%res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 %mask) %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 %mask)
ret < 8 x i64> %res ret < 8 x i64> %res
▲ Show 20 Lines • Show All 1,097 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
%res1 = call <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1) %res1 = call <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1)
%res2 = add <16 x i32> %res, %res1 %res2 = add <16 x i32> %res, %res1
ret <16 x i32> %res2 ret <16 x i32> %res2
} }
define <8 x i64>@test_int_x86_avx512_mask_pmaxs_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) { define <8 x i64>@test_int_x86_avx512_mask_pmaxs_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmaxs_q_512: ; CHECK-LABEL: test_int_x86_avx512_mask_pmaxs_q_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmaxsq %zmm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vpmaxsq %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0 ; CHECK-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
; CHECK-NEXT: vpaddq %zmm0, %zmm2, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm2, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) %res = call <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3)
%res1 = call <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1) %res1 = call <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1)
%res2 = add <8 x i64> %res, %res1 %res2 = add <8 x i64> %res, %res1
ret <8 x i64> %res2 ret <8 x i64> %res2
Show All 15 Lines; CHECK-NEXT: retq
ret <16 x i32> %res2 ret <16 x i32> %res2
} }
declare <8 x i64> @llvm.x86.avx512.mask.pmaxu.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.pmaxu.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
define <8 x i64>@test_int_x86_avx512_mask_pmaxu_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) { define <8 x i64>@test_int_x86_avx512_mask_pmaxu_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmaxu_q_512: ; CHECK-LABEL: test_int_x86_avx512_mask_pmaxu_q_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmaxuq %zmm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vpmaxuq %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0 ; CHECK-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
; CHECK-NEXT: vpaddq %zmm0, %zmm2, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm2, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.pmaxu.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) %res = call <8 x i64> @llvm.x86.avx512.mask.pmaxu.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3)
%res1 = call <8 x i64> @llvm.x86.avx512.mask.pmaxu.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1) %res1 = call <8 x i64> @llvm.x86.avx512.mask.pmaxu.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1)
%res2 = add <8 x i64> %res, %res1 %res2 = add <8 x i64> %res, %res1
ret <8 x i64> %res2 ret <8 x i64> %res2
Show All 15 Lines; CHECK-NEXT: retq
ret <16 x i32> %res2 ret <16 x i32> %res2
} }
declare <8 x i64> @llvm.x86.avx512.mask.pmins.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.pmins.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
define <8 x i64>@test_int_x86_avx512_mask_pmins_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) { define <8 x i64>@test_int_x86_avx512_mask_pmins_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmins_q_512: ; CHECK-LABEL: test_int_x86_avx512_mask_pmins_q_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpminsq %zmm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vpminsq %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vpminsq %zmm1, %zmm0, %zmm0 ; CHECK-NEXT: vpminsq %zmm1, %zmm0, %zmm0
; CHECK-NEXT: vpaddq %zmm0, %zmm2, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm2, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.pmins.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) %res = call <8 x i64> @llvm.x86.avx512.mask.pmins.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3)
%res1 = call <8 x i64> @llvm.x86.avx512.mask.pmins.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1) %res1 = call <8 x i64> @llvm.x86.avx512.mask.pmins.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1)
%res2 = add <8 x i64> %res, %res1 %res2 = add <8 x i64> %res, %res1
ret <8 x i64> %res2 ret <8 x i64> %res2
Show All 13 Lines; CHECK-NEXT: retq
ret <16 x i32> %res2 ret <16 x i32> %res2
} }
declare <8 x i64> @llvm.x86.avx512.mask.pminu.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.pminu.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
define <8 x i64>@test_int_x86_avx512_mask_pminu_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) { define <8 x i64>@test_int_x86_avx512_mask_pminu_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_pminu_q_512: ; CHECK-LABEL: test_int_x86_avx512_mask_pminu_q_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpminuq %zmm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vpminuq %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vpminuq %zmm1, %zmm0, %zmm0 ; CHECK-NEXT: vpminuq %zmm1, %zmm0, %zmm0
; CHECK-NEXT: vpaddq %zmm0, %zmm2, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm2, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.pminu.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) %res = call <8 x i64> @llvm.x86.avx512.mask.pminu.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3)
%res1 = call <8 x i64> @llvm.x86.avx512.mask.pminu.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1) %res1 = call <8 x i64> @llvm.x86.avx512.mask.pminu.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1)
%res2 = add <8 x i64> %res, %res1 %res2 = add <8 x i64> %res, %res1
ret <8 x i64> %res2 ret <8 x i64> %res2
Show All 17 Lines; CHECK-NEXT: retq
ret <16 x i32> %res2 ret <16 x i32> %res2
} }
declare <8 x double> @llvm.x86.avx512.mask.vpermi2var.pd.512(<8 x double>, <8 x i64>, <8 x double>, i8) declare <8 x double> @llvm.x86.avx512.mask.vpermi2var.pd.512(<8 x double>, <8 x i64>, <8 x double>, i8)
define <8 x double>@test_int_x86_avx512_mask_vpermi2var_pd_512(<8 x double> %x0, <8 x i64> %x1, <8 x double> %x2, i8 %x3) { define <8 x double>@test_int_x86_avx512_mask_vpermi2var_pd_512(<8 x double> %x0, <8 x i64> %x1, <8 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vpermi2var_pd_512: ; CHECK-LABEL: test_int_x86_avx512_mask_vpermi2var_pd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm1, %zmm3 ; CHECK-NEXT: vmovaps %zmm1, %zmm3
; CHECK-NEXT: vpermi2pd %zmm2, %zmm0, %zmm3 {%k1} ; CHECK-NEXT: vpermi2pd %zmm2, %zmm0, %zmm3 {%k1}
; CHECK-NEXT: vpermi2pd %zmm2, %zmm0, %zmm1 ; CHECK-NEXT: vpermi2pd %zmm2, %zmm0, %zmm1
; CHECK-NEXT: vaddpd %zmm1, %zmm3, %zmm0 ; CHECK-NEXT: vaddpd %zmm1, %zmm3, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vpermi2var.pd.512(<8 x double> %x0, <8 x i64> %x1, <8 x double> %x2, i8 %x3) %res = call <8 x double> @llvm.x86.avx512.mask.vpermi2var.pd.512(<8 x double> %x0, <8 x i64> %x1, <8 x double> %x2, i8 %x3)
%res1 = call <8 x double> @llvm.x86.avx512.mask.vpermi2var.pd.512(<8 x double> %x0, <8 x i64> %x1, <8 x double> %x2, i8 -1) %res1 = call <8 x double> @llvm.x86.avx512.mask.vpermi2var.pd.512(<8 x double> %x0, <8 x i64> %x1, <8 x double> %x2, i8 -1)
%res2 = fadd <8 x double> %res, %res1 %res2 = fadd <8 x double> %res, %res1
Show All 17 Lines; CHECK-NEXT: retq
ret <16 x float> %res2 ret <16 x float> %res2
} }
declare <8 x i64> @llvm.x86.avx512.mask.vpermi2var.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.vpermi2var.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
define <8 x i64>@test_int_x86_avx512_mask_vpermi2var_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) { define <8 x i64>@test_int_x86_avx512_mask_vpermi2var_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vpermi2var_q_512: ; CHECK-LABEL: test_int_x86_avx512_mask_vpermi2var_q_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm1, %zmm3 ; CHECK-NEXT: vmovaps %zmm1, %zmm3
; CHECK-NEXT: vpermi2q %zmm2, %zmm0, %zmm3 {%k1} ; CHECK-NEXT: vpermi2q %zmm2, %zmm0, %zmm3 {%k1}
; CHECK-NEXT: vpermi2q %zmm2, %zmm0, %zmm1 ; CHECK-NEXT: vpermi2q %zmm2, %zmm0, %zmm1
; CHECK-NEXT: vpaddq %zmm1, %zmm3, %zmm0 ; CHECK-NEXT: vpaddq %zmm1, %zmm3, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.vpermi2var.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) %res = call <8 x i64> @llvm.x86.avx512.mask.vpermi2var.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3)
%res1 = call <8 x i64> @llvm.x86.avx512.mask.vpermi2var.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1) %res1 = call <8 x i64> @llvm.x86.avx512.mask.vpermi2var.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1)
%res2 = add <8 x i64> %res, %res1 %res2 = add <8 x i64> %res, %res1
Show All 18 Lines; CHECK-NEXT: retq
ret <16 x i32> %res2 ret <16 x i32> %res2
} }
declare <8 x double> @llvm.x86.avx512.maskz.vpermt2var.pd.512(<8 x i64>, <8 x double>, <8 x double>, i8) declare <8 x double> @llvm.x86.avx512.maskz.vpermt2var.pd.512(<8 x i64>, <8 x double>, <8 x double>, i8)
define <8 x double>@test_int_x86_avx512_maskz_vpermt2var_pd_512(<8 x i64> %x0, <8 x double> %x1, double* %x2ptr, i8 %x3) { define <8 x double>@test_int_x86_avx512_maskz_vpermt2var_pd_512(<8 x i64> %x0, <8 x double> %x1, double* %x2ptr, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_maskz_vpermt2var_pd_512: ; CHECK-LABEL: test_int_x86_avx512_maskz_vpermt2var_pd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm1, %zmm2 ; CHECK-NEXT: vmovaps %zmm1, %zmm2
; CHECK-NEXT: vpermt2pd (%rdi){1to8}, %zmm0, %zmm2 {%k1} {z} ; CHECK-NEXT: vpermt2pd (%rdi){1to8}, %zmm0, %zmm2 {%k1} {z}
; CHECK-NEXT: vpermt2pd %zmm1, %zmm0, %zmm1 ; CHECK-NEXT: vpermt2pd %zmm1, %zmm0, %zmm1
; CHECK-NEXT: vaddpd %zmm1, %zmm2, %zmm0 ; CHECK-NEXT: vaddpd %zmm1, %zmm2, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%x2s = load double, double* %x2ptr %x2s = load double, double* %x2ptr
%x2ins = insertelement <8 x double> undef, double %x2s, i32 0 %x2ins = insertelement <8 x double> undef, double %x2s, i32 0
%x2 = shufflevector <8 x double> %x2ins, <8 x double> undef, <8 x i32> zeroinitializer %x2 = shufflevector <8 x double> %x2ins, <8 x double> undef, <8 x i32> zeroinitializer
Show All 21 Lines
} }
declare <8 x i64> @llvm.x86.avx512.maskz.vpermt2var.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.maskz.vpermt2var.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
define <8 x i64>@test_int_x86_avx512_maskz_vpermt2var_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) { define <8 x i64>@test_int_x86_avx512_maskz_vpermt2var_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_maskz_vpermt2var_q_512: ; CHECK-LABEL: test_int_x86_avx512_maskz_vpermt2var_q_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm1, %zmm3 ; CHECK-NEXT: vmovaps %zmm1, %zmm3
; CHECK-NEXT: vpermt2q %zmm2, %zmm0, %zmm3 {%k1} {z} ; CHECK-NEXT: vpermt2q %zmm2, %zmm0, %zmm3 {%k1} {z}
; CHECK-NEXT: vpermt2q %zmm2, %zmm0, %zmm1 ; CHECK-NEXT: vpermt2q %zmm2, %zmm0, %zmm1
; CHECK-NEXT: vpaddq %zmm1, %zmm3, %zmm0 ; CHECK-NEXT: vpaddq %zmm1, %zmm3, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.maskz.vpermt2var.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) %res = call <8 x i64> @llvm.x86.avx512.maskz.vpermt2var.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3)
%res1 = call <8 x i64> @llvm.x86.avx512.maskz.vpermt2var.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1) %res1 = call <8 x i64> @llvm.x86.avx512.maskz.vpermt2var.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1)
%res2 = add <8 x i64> %res, %res1 %res2 = add <8 x i64> %res, %res1
Show All 16 Lines; CHECK-NEXT: retq
%res2 = add <16 x i32> %res, %res1 %res2 = add <16 x i32> %res, %res1
ret <16 x i32> %res2 ret <16 x i32> %res2
} }
declare <8 x double> @llvm.x86.avx512.mask.scalef.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) declare <8 x double> @llvm.x86.avx512.mask.scalef.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32)
define <8 x double>@test_int_x86_avx512_mask_scalef_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3) { define <8 x double>@test_int_x86_avx512_mask_scalef_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_scalef_pd_512: ; CHECK-LABEL: test_int_x86_avx512_mask_scalef_pd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vscalefpd {rz-sae}, %zmm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vscalefpd {rz-sae}, %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vscalefpd {rn-sae}, %zmm1, %zmm0, %zmm0 ; CHECK-NEXT: vscalefpd {rn-sae}, %zmm1, %zmm0, %zmm0
; CHECK-NEXT: vaddpd %zmm0, %zmm2, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm2, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.scalef.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 3) %res = call <8 x double> @llvm.x86.avx512.mask.scalef.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 3)
%res1 = call <8 x double> @llvm.x86.avx512.mask.scalef.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0) %res1 = call <8 x double> @llvm.x86.avx512.mask.scalef.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0)
%res2 = fadd <8 x double> %res, %res1 %res2 = fadd <8 x double> %res, %res1
ret <8 x double> %res2 ret <8 x double> %res2
Show All 14 Lines; CHECK-NEXT: retq
ret <16 x float> %res2 ret <16 x float> %res2
} }
declare <8 x double> @llvm.x86.avx512.mask.unpckh.pd.512(<8 x double>, <8 x double>, <8 x double>, i8) declare <8 x double> @llvm.x86.avx512.mask.unpckh.pd.512(<8 x double>, <8 x double>, <8 x double>, i8)
define <8 x double>@test_int_x86_avx512_mask_unpckh_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3) { define <8 x double>@test_int_x86_avx512_mask_unpckh_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_unpckh_pd_512: ; CHECK-LABEL: test_int_x86_avx512_mask_unpckh_pd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vunpckhpd {{.*#+}} zmm2 = zmm2[1],k1[1],zmm2[3],k1[3],zmm2[5],k1[5],zmm2[7],k1[7] ; CHECK-NEXT: vunpckhpd {{.*#+}} zmm2 = zmm2[1],k1[1],zmm2[3],k1[3],zmm2[5],k1[5],zmm2[7],k1[7]
; CHECK-NEXT: vunpckhpd {{.*#+}} zmm0 = zmm0[1],zmm1[1],zmm0[3],zmm1[3],zmm0[5],zmm1[5],zmm0[7],zmm1[7] ; CHECK-NEXT: vunpckhpd {{.*#+}} zmm0 = zmm0[1],zmm1[1],zmm0[3],zmm1[3],zmm0[5],zmm1[5],zmm0[7],zmm1[7]
; CHECK-NEXT: vaddpd %zmm0, %zmm2, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm2, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.unpckh.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3) %res = call <8 x double> @llvm.x86.avx512.mask.unpckh.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3)
%res1 = call <8 x double> @llvm.x86.avx512.mask.unpckh.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1) %res1 = call <8 x double> @llvm.x86.avx512.mask.unpckh.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1)
%res2 = fadd <8 x double> %res, %res1 %res2 = fadd <8 x double> %res, %res1
ret <8 x double> %res2 ret <8 x double> %res2
Show All 15 Lines; CHECK-NEXT: retq
ret <16 x float> %res2 ret <16 x float> %res2
} }
declare <8 x double> @llvm.x86.avx512.mask.unpckl.pd.512(<8 x double>, <8 x double>, <8 x double>, i8) declare <8 x double> @llvm.x86.avx512.mask.unpckl.pd.512(<8 x double>, <8 x double>, <8 x double>, i8)
define <8 x double>@test_int_x86_avx512_mask_unpckl_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3) { define <8 x double>@test_int_x86_avx512_mask_unpckl_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_unpckl_pd_512: ; CHECK-LABEL: test_int_x86_avx512_mask_unpckl_pd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vunpcklpd {{.*#+}} zmm2 = zmm2[0],k1[0],zmm2[2],k1[2],zmm2[4],k1[4],zmm2[6],k1[6] ; CHECK-NEXT: vunpcklpd {{.*#+}} zmm2 = zmm2[0],k1[0],zmm2[2],k1[2],zmm2[4],k1[4],zmm2[6],k1[6]
; CHECK-NEXT: vunpcklpd {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6] ; CHECK-NEXT: vunpcklpd {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6]
; CHECK-NEXT: vaddpd %zmm0, %zmm2, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm2, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.unpckl.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3) %res = call <8 x double> @llvm.x86.avx512.mask.unpckl.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3)
%res1 = call <8 x double> @llvm.x86.avx512.mask.unpckl.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1) %res1 = call <8 x double> @llvm.x86.avx512.mask.unpckl.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1)
%res2 = fadd <8 x double> %res, %res1 %res2 = fadd <8 x double> %res, %res1
ret <8 x double> %res2 ret <8 x double> %res2
Show All 15 Lines; CHECK-NEXT: retq
ret <16 x float> %res2 ret <16 x float> %res2
} }
declare <8 x i64> @llvm.x86.avx512.mask.punpcklqd.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.punpcklqd.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
define <8 x i64>@test_int_x86_avx512_mask_punpcklqd_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) { define <8 x i64>@test_int_x86_avx512_mask_punpcklqd_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_punpcklqd_q_512: ; CHECK-LABEL: test_int_x86_avx512_mask_punpcklqd_q_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpunpcklqdq {{.*#+}} zmm2 = zmm2[0],k1[0],zmm2[2],k1[2],zmm2[4],k1[4],zmm2[6],k1[6] ; CHECK-NEXT: vpunpcklqdq {{.*#+}} zmm2 = zmm2[0],k1[0],zmm2[2],k1[2],zmm2[4],k1[4],zmm2[6],k1[6]
; CHECK-NEXT: vpunpcklqdq {{.*#+}} zmm3 = k1[0],zmm0[0],k1[2],zmm0[2],k1[4],zmm0[4],k1[6],zmm0[6] ; CHECK-NEXT: vpunpcklqdq {{.*#+}} zmm3 = k1[0],zmm0[0],k1[2],zmm0[2],k1[4],zmm0[4],k1[6],zmm0[6]
; CHECK-NEXT: vpunpcklqdq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6] ; CHECK-NEXT: vpunpcklqdq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6]
; CHECK-NEXT: vpaddq %zmm0, %zmm2, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm2, %zmm0
; CHECK-NEXT: vpaddq %zmm0, %zmm3, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm3, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.punpcklqd.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) %res = call <8 x i64> @llvm.x86.avx512.mask.punpcklqd.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3)
%res1 = call <8 x i64> @llvm.x86.avx512.mask.punpcklqd.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1) %res1 = call <8 x i64> @llvm.x86.avx512.mask.punpcklqd.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1)
%res2 = call <8 x i64> @llvm.x86.avx512.mask.punpcklqd.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> zeroinitializer,i8 %x3) %res2 = call <8 x i64> @llvm.x86.avx512.mask.punpcklqd.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> zeroinitializer,i8 %x3)
%res3 = add <8 x i64> %res, %res1 %res3 = add <8 x i64> %res, %res1
%res4 = add <8 x i64> %res2, %res3 %res4 = add <8 x i64> %res2, %res3
ret <8 x i64> %res4 ret <8 x i64> %res4
} }
declare <8 x i64> @llvm.x86.avx512.mask.punpckhqd.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.punpckhqd.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
define <8 x i64>@test_int_x86_avx512_mask_punpckhqd_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) { define <8 x i64>@test_int_x86_avx512_mask_punpckhqd_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_punpckhqd_q_512: ; CHECK-LABEL: test_int_x86_avx512_mask_punpckhqd_q_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpunpckhqdq {{.*#+}} zmm2 = zmm2[1],k1[1],zmm2[3],k1[3],zmm2[5],k1[5],zmm2[7],k1[7] ; CHECK-NEXT: vpunpckhqdq {{.*#+}} zmm2 = zmm2[1],k1[1],zmm2[3],k1[3],zmm2[5],k1[5],zmm2[7],k1[7]
; CHECK-NEXT: vpunpckhqdq {{.*#+}} zmm0 = zmm0[1],zmm1[1],zmm0[3],zmm1[3],zmm0[5],zmm1[5],zmm0[7],zmm1[7] ; CHECK-NEXT: vpunpckhqdq {{.*#+}} zmm0 = zmm0[1],zmm1[1],zmm0[3],zmm1[3],zmm0[5],zmm1[5],zmm0[7],zmm1[7]
; CHECK-NEXT: vpaddq %zmm0, %zmm2, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm2, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.punpckhqd.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) %res = call <8 x i64> @llvm.x86.avx512.mask.punpckhqd.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3)
%res1 = call <8 x i64> @llvm.x86.avx512.mask.punpckhqd.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1) %res1 = call <8 x i64> @llvm.x86.avx512.mask.punpckhqd.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1)
%res2 = add <8 x i64> %res, %res1 %res2 = add <8 x i64> %res, %res1
ret <8 x i64> %res2 ret <8 x i64> %res2
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
ret <16 x i8> %res4 ret <16 x i8> %res4
} }
declare void @llvm.x86.avx512.mask.pmov.qb.mem.512(i8* %ptr, <8 x i64>, i8) declare void @llvm.x86.avx512.mask.pmov.qb.mem.512(i8* %ptr, <8 x i64>, i8)
define void @test_int_x86_avx512_mask_pmov_qb_mem_512(i8* %ptr, <8 x i64> %x1, i8 %x2) { define void @test_int_x86_avx512_mask_pmov_qb_mem_512(i8* %ptr, <8 x i64> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmov_qb_mem_512: ; CHECK-LABEL: test_int_x86_avx512_mask_pmov_qb_mem_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovqb %zmm0, (%rdi) ; CHECK-NEXT: vpmovqb %zmm0, (%rdi)
; CHECK-NEXT: vpmovqb %zmm0, (%rdi) {%k1} ; CHECK-NEXT: vpmovqb %zmm0, (%rdi) {%k1}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
call void @llvm.x86.avx512.mask.pmov.qb.mem.512(i8* %ptr, <8 x i64> %x1, i8 -1) call void @llvm.x86.avx512.mask.pmov.qb.mem.512(i8* %ptr, <8 x i64> %x1, i8 -1)
call void @llvm.x86.avx512.mask.pmov.qb.mem.512(i8* %ptr, <8 x i64> %x1, i8 %x2) call void @llvm.x86.avx512.mask.pmov.qb.mem.512(i8* %ptr, <8 x i64> %x1, i8 %x2)
ret void ret void
} }
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
ret void ret void
} }
declare <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64>, <8 x i16>, i8) declare <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64>, <8 x i16>, i8)
define <8 x i16>@test_int_x86_avx512_mask_pmov_qw_512(<8 x i64> %x0, <8 x i16> %x1, i8 %x2) { define <8 x i16>@test_int_x86_avx512_mask_pmov_qw_512(<8 x i64> %x0, <8 x i16> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmov_qw_512: ; CHECK-LABEL: test_int_x86_avx512_mask_pmov_qw_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovqw %zmm0, %xmm1 {%k1} ; CHECK-NEXT: vpmovqw %zmm0, %xmm1 {%k1}
; CHECK-NEXT: vpmovqw %zmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpmovqw %zmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpmovqw %zmm0, %xmm0 ; CHECK-NEXT: vpmovqw %zmm0, %xmm0
; CHECK-NEXT: vpaddw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpaddw %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddw %xmm2, %xmm0, %xmm0 ; CHECK-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res0 = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> %x0, <8 x i16> %x1, i8 -1) %res0 = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> %x0, <8 x i16> %x1, i8 -1)
%res1 = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> %x0, <8 x i16> %x1, i8 %x2) %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> %x0, <8 x i16> %x1, i8 %x2)
%res2 = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> %x0, <8 x i16> zeroinitializer, i8 %x2) %res2 = call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> %x0, <8 x i16> zeroinitializer, i8 %x2)
%res3 = add <8 x i16> %res0, %res1 %res3 = add <8 x i16> %res0, %res1
%res4 = add <8 x i16> %res3, %res2 %res4 = add <8 x i16> %res3, %res2
ret <8 x i16> %res4 ret <8 x i16> %res4
} }
declare void @llvm.x86.avx512.mask.pmov.qw.mem.512(i8* %ptr, <8 x i64>, i8) declare void @llvm.x86.avx512.mask.pmov.qw.mem.512(i8* %ptr, <8 x i64>, i8)
define void @test_int_x86_avx512_mask_pmov_qw_mem_512(i8* %ptr, <8 x i64> %x1, i8 %x2) { define void @test_int_x86_avx512_mask_pmov_qw_mem_512(i8* %ptr, <8 x i64> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmov_qw_mem_512: ; CHECK-LABEL: test_int_x86_avx512_mask_pmov_qw_mem_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovqw %zmm0, (%rdi) ; CHECK-NEXT: vpmovqw %zmm0, (%rdi)
; CHECK-NEXT: vpmovqw %zmm0, (%rdi) {%k1} ; CHECK-NEXT: vpmovqw %zmm0, (%rdi) {%k1}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
call void @llvm.x86.avx512.mask.pmov.qw.mem.512(i8* %ptr, <8 x i64> %x1, i8 -1) call void @llvm.x86.avx512.mask.pmov.qw.mem.512(i8* %ptr, <8 x i64> %x1, i8 -1)
call void @llvm.x86.avx512.mask.pmov.qw.mem.512(i8* %ptr, <8 x i64> %x1, i8 %x2) call void @llvm.x86.avx512.mask.pmov.qw.mem.512(i8* %ptr, <8 x i64> %x1, i8 %x2)
ret void ret void
} }
declare <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.512(<8 x i64>, <8 x i16>, i8) declare <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.512(<8 x i64>, <8 x i16>, i8)
define <8 x i16>@test_int_x86_avx512_mask_pmovs_qw_512(<8 x i64> %x0, <8 x i16> %x1, i8 %x2) { define <8 x i16>@test_int_x86_avx512_mask_pmovs_qw_512(<8 x i64> %x0, <8 x i16> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovs_qw_512: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovs_qw_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovsqw %zmm0, %xmm1 {%k1} ; CHECK-NEXT: vpmovsqw %zmm0, %xmm1 {%k1}
; CHECK-NEXT: vpmovsqw %zmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpmovsqw %zmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpmovsqw %zmm0, %xmm0 ; CHECK-NEXT: vpmovsqw %zmm0, %xmm0
; CHECK-NEXT: vpaddw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpaddw %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddw %xmm2, %xmm0, %xmm0 ; CHECK-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res0 = call <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.512(<8 x i64> %x0, <8 x i16> %x1, i8 -1) %res0 = call <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.512(<8 x i64> %x0, <8 x i16> %x1, i8 -1)
%res1 = call <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.512(<8 x i64> %x0, <8 x i16> %x1, i8 %x2) %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmovs.qw.512(<8 x i64> %x0, <8 x i16> %x1, i8 %x2)
Show All 17 Lines; CHECK-NEXT: retq
ret void ret void
} }
declare <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.512(<8 x i64>, <8 x i16>, i8) declare <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.512(<8 x i64>, <8 x i16>, i8)
define <8 x i16>@test_int_x86_avx512_mask_pmovus_qw_512(<8 x i64> %x0, <8 x i16> %x1, i8 %x2) { define <8 x i16>@test_int_x86_avx512_mask_pmovus_qw_512(<8 x i64> %x0, <8 x i16> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovus_qw_512: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovus_qw_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovusqw %zmm0, %xmm1 {%k1} ; CHECK-NEXT: vpmovusqw %zmm0, %xmm1 {%k1}
; CHECK-NEXT: vpmovusqw %zmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpmovusqw %zmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpmovusqw %zmm0, %xmm0 ; CHECK-NEXT: vpmovusqw %zmm0, %xmm0
; CHECK-NEXT: vpaddw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpaddw %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddw %xmm2, %xmm0, %xmm0 ; CHECK-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res0 = call <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.512(<8 x i64> %x0, <8 x i16> %x1, i8 -1) %res0 = call <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.512(<8 x i64> %x0, <8 x i16> %x1, i8 -1)
%res1 = call <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.512(<8 x i64> %x0, <8 x i16> %x1, i8 %x2) %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmovus.qw.512(<8 x i64> %x0, <8 x i16> %x1, i8 %x2)
Show All 17 Lines; CHECK-NEXT: retq
ret void ret void
} }
declare <8 x i32> @llvm.x86.avx512.mask.pmov.qd.512(<8 x i64>, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.pmov.qd.512(<8 x i64>, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_pmov_qd_512(<8 x i64> %x0, <8 x i32> %x1, i8 %x2) { define <8 x i32>@test_int_x86_avx512_mask_pmov_qd_512(<8 x i64> %x0, <8 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmov_qd_512: ; CHECK-LABEL: test_int_x86_avx512_mask_pmov_qd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovqd %zmm0, %ymm1 {%k1} ; CHECK-NEXT: vpmovqd %zmm0, %ymm1 {%k1}
; CHECK-NEXT: vpmovqd %zmm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpmovqd %zmm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vpmovqd %zmm0, %ymm0 ; CHECK-NEXT: vpmovqd %zmm0, %ymm0
; CHECK-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm2, %ymm0, %ymm0 ; CHECK-NEXT: vpaddd %ymm2, %ymm0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res0 = call <8 x i32> @llvm.x86.avx512.mask.pmov.qd.512(<8 x i64> %x0, <8 x i32> %x1, i8 -1) %res0 = call <8 x i32> @llvm.x86.avx512.mask.pmov.qd.512(<8 x i64> %x0, <8 x i32> %x1, i8 -1)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.pmov.qd.512(<8 x i64> %x0, <8 x i32> %x1, i8 %x2) %res1 = call <8 x i32> @llvm.x86.avx512.mask.pmov.qd.512(<8 x i64> %x0, <8 x i32> %x1, i8 %x2)
%res2 = call <8 x i32> @llvm.x86.avx512.mask.pmov.qd.512(<8 x i64> %x0, <8 x i32> zeroinitializer, i8 %x2) %res2 = call <8 x i32> @llvm.x86.avx512.mask.pmov.qd.512(<8 x i64> %x0, <8 x i32> zeroinitializer, i8 %x2)
%res3 = add <8 x i32> %res0, %res1 %res3 = add <8 x i32> %res0, %res1
%res4 = add <8 x i32> %res3, %res2 %res4 = add <8 x i32> %res3, %res2
ret <8 x i32> %res4 ret <8 x i32> %res4
} }
declare void @llvm.x86.avx512.mask.pmov.qd.mem.512(i8* %ptr, <8 x i64>, i8) declare void @llvm.x86.avx512.mask.pmov.qd.mem.512(i8* %ptr, <8 x i64>, i8)
define void @test_int_x86_avx512_mask_pmov_qd_mem_512(i8* %ptr, <8 x i64> %x1, i8 %x2) { define void @test_int_x86_avx512_mask_pmov_qd_mem_512(i8* %ptr, <8 x i64> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmov_qd_mem_512: ; CHECK-LABEL: test_int_x86_avx512_mask_pmov_qd_mem_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovqd %zmm0, (%rdi) ; CHECK-NEXT: vpmovqd %zmm0, (%rdi)
; CHECK-NEXT: vpmovqd %zmm0, (%rdi) {%k1} ; CHECK-NEXT: vpmovqd %zmm0, (%rdi) {%k1}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
call void @llvm.x86.avx512.mask.pmov.qd.mem.512(i8* %ptr, <8 x i64> %x1, i8 -1) call void @llvm.x86.avx512.mask.pmov.qd.mem.512(i8* %ptr, <8 x i64> %x1, i8 -1)
call void @llvm.x86.avx512.mask.pmov.qd.mem.512(i8* %ptr, <8 x i64> %x1, i8 %x2) call void @llvm.x86.avx512.mask.pmov.qd.mem.512(i8* %ptr, <8 x i64> %x1, i8 %x2)
ret void ret void
} }
declare <8 x i32> @llvm.x86.avx512.mask.pmovs.qd.512(<8 x i64>, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.pmovs.qd.512(<8 x i64>, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_pmovs_qd_512(<8 x i64> %x0, <8 x i32> %x1, i8 %x2) { define <8 x i32>@test_int_x86_avx512_mask_pmovs_qd_512(<8 x i64> %x0, <8 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovs_qd_512: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovs_qd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovsqd %zmm0, %ymm1 {%k1} ; CHECK-NEXT: vpmovsqd %zmm0, %ymm1 {%k1}
; CHECK-NEXT: vpmovsqd %zmm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpmovsqd %zmm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vpmovsqd %zmm0, %ymm0 ; CHECK-NEXT: vpmovsqd %zmm0, %ymm0
; CHECK-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm2, %ymm0, %ymm0 ; CHECK-NEXT: vpaddd %ymm2, %ymm0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res0 = call <8 x i32> @llvm.x86.avx512.mask.pmovs.qd.512(<8 x i64> %x0, <8 x i32> %x1, i8 -1) %res0 = call <8 x i32> @llvm.x86.avx512.mask.pmovs.qd.512(<8 x i64> %x0, <8 x i32> %x1, i8 -1)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.pmovs.qd.512(<8 x i64> %x0, <8 x i32> %x1, i8 %x2) %res1 = call <8 x i32> @llvm.x86.avx512.mask.pmovs.qd.512(<8 x i64> %x0, <8 x i32> %x1, i8 %x2)
Show All 17 Lines; CHECK-NEXT: retq
ret void ret void
} }
declare <8 x i32> @llvm.x86.avx512.mask.pmovus.qd.512(<8 x i64>, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.pmovus.qd.512(<8 x i64>, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_pmovus_qd_512(<8 x i64> %x0, <8 x i32> %x1, i8 %x2) { define <8 x i32>@test_int_x86_avx512_mask_pmovus_qd_512(<8 x i64> %x0, <8 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovus_qd_512: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovus_qd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovusqd %zmm0, %ymm1 {%k1} ; CHECK-NEXT: vpmovusqd %zmm0, %ymm1 {%k1}
; CHECK-NEXT: vpmovusqd %zmm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpmovusqd %zmm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vpmovusqd %zmm0, %ymm0 ; CHECK-NEXT: vpmovusqd %zmm0, %ymm0
; CHECK-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm2, %ymm0, %ymm0 ; CHECK-NEXT: vpaddd %ymm2, %ymm0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res0 = call <8 x i32> @llvm.x86.avx512.mask.pmovus.qd.512(<8 x i64> %x0, <8 x i32> %x1, i8 -1) %res0 = call <8 x i32> @llvm.x86.avx512.mask.pmovus.qd.512(<8 x i64> %x0, <8 x i32> %x1, i8 -1)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.pmovus.qd.512(<8 x i64> %x0, <8 x i32> %x1, i8 %x2) %res1 = call <8 x i32> @llvm.x86.avx512.mask.pmovus.qd.512(<8 x i64> %x0, <8 x i32> %x1, i8 %x2)
▲ Show 20 Lines • Show All 221 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
ret void ret void
} }
declare <8 x double> @llvm.x86.avx512.mask.cvtdq2pd.512(<8 x i32>, <8 x double>, i8) declare <8 x double> @llvm.x86.avx512.mask.cvtdq2pd.512(<8 x i32>, <8 x double>, i8)
define <8 x double>@test_int_x86_avx512_mask_cvt_dq2pd_512(<8 x i32> %x0, <8 x double> %x1, i8 %x2) { define <8 x double>@test_int_x86_avx512_mask_cvt_dq2pd_512(<8 x i32> %x0, <8 x double> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_dq2pd_512: ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_dq2pd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvtdq2pd %ymm0, %zmm1 {%k1} ; CHECK-NEXT: vcvtdq2pd %ymm0, %zmm1 {%k1}
; CHECK-NEXT: vcvtdq2pd %ymm0, %zmm0 ; CHECK-NEXT: vcvtdq2pd %ymm0, %zmm0
; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.cvtdq2pd.512(<8 x i32> %x0, <8 x double> %x1, i8 %x2) %res = call <8 x double> @llvm.x86.avx512.mask.cvtdq2pd.512(<8 x i32> %x0, <8 x double> %x1, i8 %x2)
%res1 = call <8 x double> @llvm.x86.avx512.mask.cvtdq2pd.512(<8 x i32> %x0, <8 x double> %x1, i8 -1) %res1 = call <8 x double> @llvm.x86.avx512.mask.cvtdq2pd.512(<8 x i32> %x0, <8 x double> %x1, i8 -1)
%res2 = fadd <8 x double> %res, %res1 %res2 = fadd <8 x double> %res, %res1
ret <8 x double> %res2 ret <8 x double> %res2
Show All 15 Lines; CHECK-NEXT: retq
ret <16 x float> %res2 ret <16 x float> %res2
} }
declare <8 x i32> @llvm.x86.avx512.mask.cvtpd2dq.512(<8 x double>, <8 x i32>, i8, i32) declare <8 x i32> @llvm.x86.avx512.mask.cvtpd2dq.512(<8 x double>, <8 x i32>, i8, i32)
define <8 x i32>@test_int_x86_avx512_mask_cvt_pd2dq_512(<8 x double> %x0, <8 x i32> %x1, i8 %x2) { define <8 x i32>@test_int_x86_avx512_mask_cvt_pd2dq_512(<8 x double> %x0, <8 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2dq_512: ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2dq_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvtpd2dq %zmm0, %ymm1 {%k1} ; CHECK-NEXT: vcvtpd2dq %zmm0, %ymm1 {%k1}
; CHECK-NEXT: vcvtpd2dq {rn-sae}, %zmm0, %ymm0 ; CHECK-NEXT: vcvtpd2dq {rn-sae}, %zmm0, %ymm0
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.cvtpd2dq.512(<8 x double> %x0, <8 x i32> %x1, i8 %x2, i32 4) %res = call <8 x i32> @llvm.x86.avx512.mask.cvtpd2dq.512(<8 x double> %x0, <8 x i32> %x1, i8 %x2, i32 4)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.cvtpd2dq.512(<8 x double> %x0, <8 x i32> %x1, i8 -1, i32 0) %res1 = call <8 x i32> @llvm.x86.avx512.mask.cvtpd2dq.512(<8 x double> %x0, <8 x i32> %x1, i8 -1, i32 0)
%res2 = add <8 x i32> %res, %res1 %res2 = add <8 x i32> %res, %res1
ret <8 x i32> %res2 ret <8 x i32> %res2
} }
declare <8 x float> @llvm.x86.avx512.mask.cvtpd2ps.512(<8 x double>, <8 x float>, i8, i32) declare <8 x float> @llvm.x86.avx512.mask.cvtpd2ps.512(<8 x double>, <8 x float>, i8, i32)
define <8 x float>@test_int_x86_avx512_mask_cvt_pd2ps_512(<8 x double> %x0, <8 x float> %x1, i8 %x2) { define <8 x float>@test_int_x86_avx512_mask_cvt_pd2ps_512(<8 x double> %x0, <8 x float> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2ps_512: ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2ps_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvtpd2ps %zmm0, %ymm1 {%k1} ; CHECK-NEXT: vcvtpd2ps %zmm0, %ymm1 {%k1}
; CHECK-NEXT: vcvtpd2ps {ru-sae}, %zmm0, %ymm0 ; CHECK-NEXT: vcvtpd2ps {ru-sae}, %zmm0, %ymm0
; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx512.mask.cvtpd2ps.512(<8 x double> %x0, <8 x float> %x1, i8 %x2, i32 4) %res = call <8 x float> @llvm.x86.avx512.mask.cvtpd2ps.512(<8 x double> %x0, <8 x float> %x1, i8 %x2, i32 4)
%res1 = call <8 x float> @llvm.x86.avx512.mask.cvtpd2ps.512(<8 x double> %x0, <8 x float> %x1, i8 -1, i32 2) %res1 = call <8 x float> @llvm.x86.avx512.mask.cvtpd2ps.512(<8 x double> %x0, <8 x float> %x1, i8 -1, i32 2)
%res2 = fadd <8 x float> %res, %res1 %res2 = fadd <8 x float> %res, %res1
ret <8 x float> %res2 ret <8 x float> %res2
} }
declare <8 x i32> @llvm.x86.avx512.mask.cvtpd2udq.512(<8 x double>, <8 x i32>, i8, i32) declare <8 x i32> @llvm.x86.avx512.mask.cvtpd2udq.512(<8 x double>, <8 x i32>, i8, i32)
define <8 x i32>@test_int_x86_avx512_mask_cvt_pd2udq_512(<8 x double> %x0, <8 x i32> %x1, i8 %x2) { define <8 x i32>@test_int_x86_avx512_mask_cvt_pd2udq_512(<8 x double> %x0, <8 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2udq_512: ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2udq_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvtpd2udq {ru-sae}, %zmm0, %ymm1 {%k1} ; CHECK-NEXT: vcvtpd2udq {ru-sae}, %zmm0, %ymm1 {%k1}
; CHECK-NEXT: vcvtpd2udq {rn-sae}, %zmm0, %ymm0 ; CHECK-NEXT: vcvtpd2udq {rn-sae}, %zmm0, %ymm0
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.cvtpd2udq.512(<8 x double> %x0, <8 x i32> %x1, i8 %x2, i32 2) %res = call <8 x i32> @llvm.x86.avx512.mask.cvtpd2udq.512(<8 x double> %x0, <8 x i32> %x1, i8 %x2, i32 2)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.cvtpd2udq.512(<8 x double> %x0, <8 x i32> %x1, i8 -1, i32 0) %res1 = call <8 x i32> @llvm.x86.avx512.mask.cvtpd2udq.512(<8 x double> %x0, <8 x i32> %x1, i8 -1, i32 0)
%res2 = add <8 x i32> %res, %res1 %res2 = add <8 x i32> %res, %res1
ret <8 x i32> %res2 ret <8 x i32> %res2
Show All 15 Lines; CHECK-NEXT: retq
ret <16 x i32> %res2 ret <16 x i32> %res2
} }
declare <8 x double> @llvm.x86.avx512.mask.cvtps2pd.512(<8 x float>, <8 x double>, i8, i32) declare <8 x double> @llvm.x86.avx512.mask.cvtps2pd.512(<8 x float>, <8 x double>, i8, i32)
define <8 x double>@test_int_x86_avx512_mask_cvt_ps2pd_512(<8 x float> %x0, <8 x double> %x1, i8 %x2) { define <8 x double>@test_int_x86_avx512_mask_cvt_ps2pd_512(<8 x float> %x0, <8 x double> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2pd_512: ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2pd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvtps2pd %ymm0, %zmm1 {%k1} ; CHECK-NEXT: vcvtps2pd %ymm0, %zmm1 {%k1}
; CHECK-NEXT: vcvtps2pd {sae}, %ymm0, %zmm0 ; CHECK-NEXT: vcvtps2pd {sae}, %ymm0, %zmm0
; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.cvtps2pd.512(<8 x float> %x0, <8 x double> %x1, i8 %x2, i32 4) %res = call <8 x double> @llvm.x86.avx512.mask.cvtps2pd.512(<8 x float> %x0, <8 x double> %x1, i8 %x2, i32 4)
%res1 = call <8 x double> @llvm.x86.avx512.mask.cvtps2pd.512(<8 x float> %x0, <8 x double> %x1, i8 -1, i32 8) %res1 = call <8 x double> @llvm.x86.avx512.mask.cvtps2pd.512(<8 x float> %x0, <8 x double> %x1, i8 -1, i32 8)
%res2 = fadd <8 x double> %res, %res1 %res2 = fadd <8 x double> %res, %res1
ret <8 x double> %res2 ret <8 x double> %res2
Show All 15 Lines; CHECK-NEXT: retq
ret <16 x i32> %res2 ret <16 x i32> %res2
} }
declare <8 x i32> @llvm.x86.avx512.mask.cvttpd2dq.512(<8 x double>, <8 x i32>, i8, i32) declare <8 x i32> @llvm.x86.avx512.mask.cvttpd2dq.512(<8 x double>, <8 x i32>, i8, i32)
define <8 x i32>@test_int_x86_avx512_mask_cvtt_pd2dq_512(<8 x double> %x0, <8 x i32> %x1, i8 %x2) { define <8 x i32>@test_int_x86_avx512_mask_cvtt_pd2dq_512(<8 x double> %x0, <8 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2dq_512: ; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2dq_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvttpd2dq %zmm0, %ymm1 {%k1} ; CHECK-NEXT: vcvttpd2dq %zmm0, %ymm1 {%k1}
; CHECK-NEXT: vcvttpd2dq {sae}, %zmm0, %ymm0 ; CHECK-NEXT: vcvttpd2dq {sae}, %zmm0, %ymm0
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.cvttpd2dq.512(<8 x double> %x0, <8 x i32> %x1, i8 %x2, i32 4) %res = call <8 x i32> @llvm.x86.avx512.mask.cvttpd2dq.512(<8 x double> %x0, <8 x i32> %x1, i8 %x2, i32 4)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.cvttpd2dq.512(<8 x double> %x0, <8 x i32> %x1, i8 -1, i32 8) %res1 = call <8 x i32> @llvm.x86.avx512.mask.cvttpd2dq.512(<8 x double> %x0, <8 x i32> %x1, i8 -1, i32 8)
%res2 = add <8 x i32> %res, %res1 %res2 = add <8 x i32> %res, %res1
ret <8 x i32> %res2 ret <8 x i32> %res2
} }
declare <8 x double> @llvm.x86.avx512.mask.cvtudq2pd.512(<8 x i32>, <8 x double>, i8) declare <8 x double> @llvm.x86.avx512.mask.cvtudq2pd.512(<8 x i32>, <8 x double>, i8)
define <8 x double>@test_int_x86_avx512_mask_cvt_udq2pd_512(<8 x i32> %x0, <8 x double> %x1, i8 %x2) { define <8 x double>@test_int_x86_avx512_mask_cvt_udq2pd_512(<8 x i32> %x0, <8 x double> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_udq2pd_512: ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_udq2pd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvtudq2pd %ymm0, %zmm1 {%k1} ; CHECK-NEXT: vcvtudq2pd %ymm0, %zmm1 {%k1}
; CHECK-NEXT: vcvtudq2pd %ymm0, %zmm0 ; CHECK-NEXT: vcvtudq2pd %ymm0, %zmm0
; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.cvtudq2pd.512(<8 x i32> %x0, <8 x double> %x1, i8 %x2) %res = call <8 x double> @llvm.x86.avx512.mask.cvtudq2pd.512(<8 x i32> %x0, <8 x double> %x1, i8 %x2)
%res1 = call <8 x double> @llvm.x86.avx512.mask.cvtudq2pd.512(<8 x i32> %x0, <8 x double> %x1, i8 -1) %res1 = call <8 x double> @llvm.x86.avx512.mask.cvtudq2pd.512(<8 x i32> %x0, <8 x double> %x1, i8 -1)
%res2 = fadd <8 x double> %res, %res1 %res2 = fadd <8 x double> %res, %res1
ret <8 x double> %res2 ret <8 x double> %res2
Show All 16 Lines; CHECK-NEXT: retq
ret <16 x float> %res2 ret <16 x float> %res2
} }
declare <8 x i32> @llvm.x86.avx512.mask.cvttpd2udq.512(<8 x double>, <8 x i32>, i8, i32) declare <8 x i32> @llvm.x86.avx512.mask.cvttpd2udq.512(<8 x double>, <8 x i32>, i8, i32)
define <8 x i32>@test_int_x86_avx512_mask_cvtt_pd2udq_512(<8 x double> %x0, <8 x i32> %x1, i8 %x2) { define <8 x i32>@test_int_x86_avx512_mask_cvtt_pd2udq_512(<8 x double> %x0, <8 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2udq_512: ; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2udq_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvttpd2udq %zmm0, %ymm1 {%k1} ; CHECK-NEXT: vcvttpd2udq %zmm0, %ymm1 {%k1}
; CHECK-NEXT: vcvttpd2udq {sae}, %zmm0, %ymm0 ; CHECK-NEXT: vcvttpd2udq {sae}, %zmm0, %ymm0
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.cvttpd2udq.512(<8 x double> %x0, <8 x i32> %x1, i8 %x2, i32 4) %res = call <8 x i32> @llvm.x86.avx512.mask.cvttpd2udq.512(<8 x double> %x0, <8 x i32> %x1, i8 %x2, i32 4)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.cvttpd2udq.512(<8 x double> %x0, <8 x i32> %x1, i8 -1, i32 8) %res1 = call <8 x i32> @llvm.x86.avx512.mask.cvttpd2udq.512(<8 x double> %x0, <8 x i32> %x1, i8 -1, i32 8)
%res2 = add <8 x i32> %res, %res1 %res2 = add <8 x i32> %res, %res1
ret <8 x i32> %res2 ret <8 x i32> %res2
▲ Show 20 Lines • Show All 224 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
ret <16 x float> %res2 ret <16 x float> %res2
} }
declare <8 x double> @llvm.x86.avx512.mask.shuf.f64x2(<8 x double>, <8 x double>, i32, <8 x double>, i8) declare <8 x double> @llvm.x86.avx512.mask.shuf.f64x2(<8 x double>, <8 x double>, i32, <8 x double>, i8)
define <8 x double>@test_int_x86_avx512_mask_shuf_f64x2(<8 x double> %x0, <8 x double> %x1, <8 x double> %x3, i8 %x4) { define <8 x double>@test_int_x86_avx512_mask_shuf_f64x2(<8 x double> %x0, <8 x double> %x1, <8 x double> %x3, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_shuf_f64x2: ; CHECK-LABEL: test_int_x86_avx512_mask_shuf_f64x2:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm2 = zmm0[4,5,2,3],zmm1[2,3,0,1] ; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm2 = zmm0[4,5,2,3],zmm1[2,3,0,1]
; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm3 = zmm0[4,5,2,3],zmm1[2,3,0,1] ; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm3 = zmm0[4,5,2,3],zmm1[2,3,0,1]
; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[4,5,2,3],zmm1[2,3,0,1] ; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[4,5,2,3],zmm1[2,3,0,1]
; CHECK-NEXT: vaddpd %zmm0, %zmm2, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm2, %zmm0
; CHECK-NEXT: vaddpd %zmm3, %zmm0, %zmm0 ; CHECK-NEXT: vaddpd %zmm3, %zmm0, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.shuf.f64x2(<8 x double> %x0, <8 x double> %x1, i32 22, <8 x double> %x3, i8 %x4) %res = call <8 x double> @llvm.x86.avx512.mask.shuf.f64x2(<8 x double> %x0, <8 x double> %x1, i32 22, <8 x double> %x3, i8 %x4)
%res1 = call <8 x double> @llvm.x86.avx512.mask.shuf.f64x2(<8 x double> %x0, <8 x double> %x1, i32 22, <8 x double> %x3, i8 -1) %res1 = call <8 x double> @llvm.x86.avx512.mask.shuf.f64x2(<8 x double> %x0, <8 x double> %x1, i32 22, <8 x double> %x3, i8 -1)
Show All 20 Lines; CHECK-NEXT: retq
ret <16 x i32> %res2 ret <16 x i32> %res2
} }
declare <8 x i64> @llvm.x86.avx512.mask.shuf.i64x2(<8 x i64>, <8 x i64>, i32, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.shuf.i64x2(<8 x i64>, <8 x i64>, i32, <8 x i64>, i8)
define <8 x i64>@test_int_x86_avx512_mask_shuf_i64x2(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x3, i8 %x4) { define <8 x i64>@test_int_x86_avx512_mask_shuf_i64x2(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x3, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_shuf_i64x2: ; CHECK-LABEL: test_int_x86_avx512_mask_shuf_i64x2:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm0[4,5,2,3],zmm1[2,3,0,1] ; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm0[4,5,2,3],zmm1[2,3,0,1]
; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[4,5,2,3],zmm1[2,3,0,1] ; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[4,5,2,3],zmm1[2,3,0,1]
; CHECK-NEXT: vpaddq %zmm0, %zmm2, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm2, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.shuf.i64x2(<8 x i64> %x0, <8 x i64> %x1, i32 22, <8 x i64> %x3, i8 %x4) %res = call <8 x i64> @llvm.x86.avx512.mask.shuf.i64x2(<8 x i64> %x0, <8 x i64> %x1, i32 22, <8 x i64> %x3, i8 %x4)
%res1 = call <8 x i64> @llvm.x86.avx512.mask.shuf.i64x2(<8 x i64> %x0, <8 x i64> %x1, i32 22, <8 x i64> %x3, i8 -1) %res1 = call <8 x i64> @llvm.x86.avx512.mask.shuf.i64x2(<8 x i64> %x0, <8 x i64> %x1, i32 22, <8 x i64> %x3, i8 -1)
%res2 = add <8 x i64> %res, %res1 %res2 = add <8 x i64> %res, %res1
ret <8 x i64> %res2 ret <8 x i64> %res2
} }
declare <8 x double> @llvm.x86.avx512.mask.getmant.pd.512(<8 x double>, i32, <8 x double>, i8, i32) declare <8 x double> @llvm.x86.avx512.mask.getmant.pd.512(<8 x double>, i32, <8 x double>, i8, i32)
define <8 x double>@test_int_x86_avx512_mask_getmant_pd_512(<8 x double> %x0, <8 x double> %x2, i8 %x3) { define <8 x double>@test_int_x86_avx512_mask_getmant_pd_512(<8 x double> %x0, <8 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_getmant_pd_512: ; CHECK-LABEL: test_int_x86_avx512_mask_getmant_pd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vgetmantpd $11, %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vgetmantpd $11, %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vgetmantpd $11, {sae}, %zmm0, %zmm0 ; CHECK-NEXT: vgetmantpd $11, {sae}, %zmm0, %zmm0
; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.getmant.pd.512(<8 x double> %x0, i32 11, <8 x double> %x2, i8 %x3, i32 4) %res = call <8 x double> @llvm.x86.avx512.mask.getmant.pd.512(<8 x double> %x0, i32 11, <8 x double> %x2, i8 %x3, i32 4)
%res1 = call <8 x double> @llvm.x86.avx512.mask.getmant.pd.512(<8 x double> %x0, i32 11, <8 x double> %x2, i8 -1, i32 8) %res1 = call <8 x double> @llvm.x86.avx512.mask.getmant.pd.512(<8 x double> %x0, i32 11, <8 x double> %x2, i8 -1, i32 8)
%res2 = fadd <8 x double> %res, %res1 %res2 = fadd <8 x double> %res, %res1
ret <8 x double> %res2 ret <8 x double> %res2
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
ret <4 x float> %res13 ret <4 x float> %res13
} }
declare <8 x double> @llvm.x86.avx512.mask.shuf.pd.512(<8 x double>, <8 x double>, i32, <8 x double>, i8) declare <8 x double> @llvm.x86.avx512.mask.shuf.pd.512(<8 x double>, <8 x double>, i32, <8 x double>, i8)
define <8 x double>@test_int_x86_avx512_mask_shuf_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x3, i8 %x4) { define <8 x double>@test_int_x86_avx512_mask_shuf_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x3, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_shuf_pd_512: ; CHECK-LABEL: test_int_x86_avx512_mask_shuf_pd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vshufpd {{.*#+}} zmm2 = zmm2[0],k1[1],zmm2[3],k1[2],zmm2[5],k1[4],zmm2[6],k1[6] ; CHECK-NEXT: vshufpd {{.*#+}} zmm2 = zmm2[0],k1[1],zmm2[3],k1[2],zmm2[5],k1[4],zmm2[6],k1[6]
; CHECK-NEXT: vshufpd {{.*#+}} zmm3 = k1[0],zmm0[1],k1[3],zmm0[2],k1[5],zmm0[4],k1[6],zmm0[6] ; CHECK-NEXT: vshufpd {{.*#+}} zmm3 = k1[0],zmm0[1],k1[3],zmm0[2],k1[5],zmm0[4],k1[6],zmm0[6]
; CHECK-NEXT: vshufpd {{.*#+}} zmm0 = zmm0[0],zmm1[1],zmm0[3],zmm1[2],zmm0[5],zmm1[4],zmm0[6],zmm1[6] ; CHECK-NEXT: vshufpd {{.*#+}} zmm0 = zmm0[0],zmm1[1],zmm0[3],zmm1[2],zmm0[5],zmm1[4],zmm0[6],zmm1[6]
; CHECK-NEXT: vaddpd %zmm0, %zmm2, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm2, %zmm0
; CHECK-NEXT: vaddpd %zmm3, %zmm0, %zmm0 ; CHECK-NEXT: vaddpd %zmm3, %zmm0, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.shuf.pd.512(<8 x double> %x0, <8 x double> %x1, i32 22, <8 x double> %x3, i8 %x4) %res = call <8 x double> @llvm.x86.avx512.mask.shuf.pd.512(<8 x double> %x0, <8 x double> %x1, i32 22, <8 x double> %x3, i8 %x4)
%res1 = call <8 x double> @llvm.x86.avx512.mask.shuf.pd.512(<8 x double> %x0, <8 x double> %x1, i32 22, <8 x double> %x3, i8 -1) %res1 = call <8 x double> @llvm.x86.avx512.mask.shuf.pd.512(<8 x double> %x0, <8 x double> %x1, i32 22, <8 x double> %x3, i8 -1)
Show All 20 Lines; CHECK-NEXT: retq
ret <16 x float> %res2 ret <16 x float> %res2
} }
declare <8 x double> @llvm.x86.avx512.mask.vpermil.pd.512(<8 x double>, i32, <8 x double>, i8) declare <8 x double> @llvm.x86.avx512.mask.vpermil.pd.512(<8 x double>, i32, <8 x double>, i8)
define <8 x double>@test_int_x86_avx512_mask_vpermil_pd_512(<8 x double> %x0, <8 x double> %x2, i8 %x3) { define <8 x double>@test_int_x86_avx512_mask_vpermil_pd_512(<8 x double> %x0, <8 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vpermil_pd_512: ; CHECK-LABEL: test_int_x86_avx512_mask_vpermil_pd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpermilpd {{.*#+}} zmm1 = zmm1[0,1,3,2,5,4,6,6] ; CHECK-NEXT: vpermilpd {{.*#+}} zmm1 = zmm1[0,1,3,2,5,4,6,6]
; CHECK-NEXT: vpermilpd {{.*#+}} zmm2 = k1[0,1,3,2,5,4,6,6] ; CHECK-NEXT: vpermilpd {{.*#+}} zmm2 = k1[0,1,3,2,5,4,6,6]
; CHECK-NEXT: vpermilpd {{.*#+}} zmm0 = zmm0[0,1,3,2,5,4,6,6] ; CHECK-NEXT: vpermilpd {{.*#+}} zmm0 = zmm0[0,1,3,2,5,4,6,6]
; CHECK-NEXT: vaddpd %zmm2, %zmm1, %zmm1 ; CHECK-NEXT: vaddpd %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vpermil.pd.512(<8 x double> %x0, i32 22, <8 x double> %x2, i8 %x3) %res = call <8 x double> @llvm.x86.avx512.mask.vpermil.pd.512(<8 x double> %x0, i32 22, <8 x double> %x2, i8 %x3)
%res1 = call <8 x double> @llvm.x86.avx512.mask.vpermil.pd.512(<8 x double> %x0, i32 22, <8 x double> zeroinitializer, i8 %x3) %res1 = call <8 x double> @llvm.x86.avx512.mask.vpermil.pd.512(<8 x double> %x0, i32 22, <8 x double> zeroinitializer, i8 %x3)
Show All 23 Lines; CHECK-NEXT: retq
ret <16 x float> %res4 ret <16 x float> %res4
} }
declare <8 x double> @llvm.x86.avx512.mask.vpermilvar.pd.512(<8 x double>, <8 x i64>, <8 x double>, i8) declare <8 x double> @llvm.x86.avx512.mask.vpermilvar.pd.512(<8 x double>, <8 x i64>, <8 x double>, i8)
define <8 x double>@test_int_x86_avx512_mask_vpermilvar_pd_512(<8 x double> %x0, <8 x i64> %x1, <8 x double> %x2, i8 %x3) { define <8 x double>@test_int_x86_avx512_mask_vpermilvar_pd_512(<8 x double> %x0, <8 x i64> %x1, <8 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vpermilvar_pd_512: ; CHECK-LABEL: test_int_x86_avx512_mask_vpermilvar_pd_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpermilpd %zmm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vpermilpd %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vpermilpd %zmm1, %zmm0, %zmm3 {%k1} {z} ; CHECK-NEXT: vpermilpd %zmm1, %zmm0, %zmm3 {%k1} {z}
; CHECK-NEXT: vpermilpd %zmm1, %zmm0, %zmm0 ; CHECK-NEXT: vpermilpd %zmm1, %zmm0, %zmm0
; CHECK-NEXT: vaddpd %zmm3, %zmm2, %zmm1 ; CHECK-NEXT: vaddpd %zmm3, %zmm2, %zmm1
; CHECK-NEXT: vaddpd %zmm1, %zmm0, %zmm0 ; CHECK-NEXT: vaddpd %zmm1, %zmm0, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.vpermilvar.pd.512(<8 x double> %x0, <8 x i64> %x1, <8 x double> %x2, i8 %x3) %res = call <8 x double> @llvm.x86.avx512.mask.vpermilvar.pd.512(<8 x double> %x0, <8 x i64> %x1, <8 x double> %x2, i8 %x3)
%res1 = call <8 x double> @llvm.x86.avx512.mask.vpermilvar.pd.512(<8 x double> %x0, <8 x i64> %x1, <8 x double> zeroinitializer, i8 %x3) %res1 = call <8 x double> @llvm.x86.avx512.mask.vpermilvar.pd.512(<8 x double> %x0, <8 x i64> %x1, <8 x double> zeroinitializer, i8 %x3)
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
ret <16 x i32> %res4 ret <16 x i32> %res4
} }
declare <8 x double> @llvm.x86.avx512.mask.insertf64x4.512(<8 x double>, <4 x double>, i32, <8 x double>, i8) declare <8 x double> @llvm.x86.avx512.mask.insertf64x4.512(<8 x double>, <4 x double>, i32, <8 x double>, i8)
define <8 x double>@test_int_x86_avx512_mask_insertf64x4_512(<8 x double> %x0, <4 x double> %x1, <8 x double> %x3, i8 %x4) { define <8 x double>@test_int_x86_avx512_mask_insertf64x4_512(<8 x double> %x0, <4 x double> %x1, <8 x double> %x3, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_insertf64x4_512: ; CHECK-LABEL: test_int_x86_avx512_mask_insertf64x4_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm3 {%k1} {z} ; CHECK-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm3 {%k1} {z}
; CHECK-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 ; CHECK-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
; CHECK-NEXT: vaddpd %zmm0, %zmm2, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm2, %zmm0
; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.insertf64x4.512(<8 x double> %x0, <4 x double> %x1, i32 1, <8 x double> %x3, i8 %x4) %res = call <8 x double> @llvm.x86.avx512.mask.insertf64x4.512(<8 x double> %x0, <4 x double> %x1, i32 1, <8 x double> %x3, i8 %x4)
%res1 = call <8 x double> @llvm.x86.avx512.mask.insertf64x4.512(<8 x double> %x0, <4 x double> %x1, i32 1, <8 x double> %x3, i8 -1) %res1 = call <8 x double> @llvm.x86.avx512.mask.insertf64x4.512(<8 x double> %x0, <4 x double> %x1, i32 1, <8 x double> %x3, i8 -1)
%res2 = call <8 x double> @llvm.x86.avx512.mask.insertf64x4.512(<8 x double> %x0, <4 x double> %x1, i32 1, <8 x double> zeroinitializer, i8 %x4) %res2 = call <8 x double> @llvm.x86.avx512.mask.insertf64x4.512(<8 x double> %x0, <4 x double> %x1, i32 1, <8 x double> zeroinitializer, i8 %x4)
%res3 = fadd <8 x double> %res, %res1 %res3 = fadd <8 x double> %res, %res1
%res4 = fadd <8 x double> %res2, %res3 %res4 = fadd <8 x double> %res2, %res3
ret <8 x double> %res4 ret <8 x double> %res4
} }
declare <8 x i64> @llvm.x86.avx512.mask.inserti64x4.512(<8 x i64>, <4 x i64>, i32, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.inserti64x4.512(<8 x i64>, <4 x i64>, i32, <8 x i64>, i8)
define <8 x i64>@test_int_x86_avx512_mask_inserti64x4_512(<8 x i64> %x0, <4 x i64> %x1, <8 x i64> %x3, i8 %x4) { define <8 x i64>@test_int_x86_avx512_mask_inserti64x4_512(<8 x i64> %x0, <4 x i64> %x1, <8 x i64> %x3, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_inserti64x4_512: ; CHECK-LABEL: test_int_x86_avx512_mask_inserti64x4_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm3 {%k1} {z} ; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm3 {%k1} {z}
; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 ; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
; CHECK-NEXT: vpaddq %zmm0, %zmm2, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm2, %zmm0
; CHECK-NEXT: vpaddq %zmm0, %zmm3, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm3, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.inserti64x4.512(<8 x i64> %x0, <4 x i64> %x1, i32 1, <8 x i64> %x3, i8 %x4) %res = call <8 x i64> @llvm.x86.avx512.mask.inserti64x4.512(<8 x i64> %x0, <4 x i64> %x1, i32 1, <8 x i64> %x3, i8 %x4)
%res1 = call <8 x i64> @llvm.x86.avx512.mask.inserti64x4.512(<8 x i64> %x0, <4 x i64> %x1, i32 1, <8 x i64> %x3, i8 -1) %res1 = call <8 x i64> @llvm.x86.avx512.mask.inserti64x4.512(<8 x i64> %x0, <4 x i64> %x1, i32 1, <8 x i64> %x3, i8 -1)
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
ret <16 x i32> %res2 ret <16 x i32> %res2
} }
declare <8 x i64> @llvm.x86.avx512.mask.pternlog.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i32, i8) declare <8 x i64> @llvm.x86.avx512.mask.pternlog.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i32, i8)
define <8 x i64>@test_int_x86_avx512_mask_pternlog_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x4) { define <8 x i64>@test_int_x86_avx512_mask_pternlog_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_pternlog_q_512: ; CHECK-LABEL: test_int_x86_avx512_mask_pternlog_q_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vpternlogq $33, %zmm2, %zmm1, %zmm3 {%k1} ; CHECK-NEXT: vpternlogq $33, %zmm2, %zmm1, %zmm3 {%k1}
; CHECK-NEXT: vpternlogq $33, %zmm2, %zmm1, %zmm0 ; CHECK-NEXT: vpternlogq $33, %zmm2, %zmm1, %zmm0
; CHECK-NEXT: vpaddq %zmm0, %zmm3, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm3, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.pternlog.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i32 33, i8 %x4) %res = call <8 x i64> @llvm.x86.avx512.mask.pternlog.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i32 33, i8 %x4)
%res1 = call <8 x i64> @llvm.x86.avx512.mask.pternlog.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i32 33, i8 -1) %res1 = call <8 x i64> @llvm.x86.avx512.mask.pternlog.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i32 33, i8 -1)
%res2 = add <8 x i64> %res, %res1 %res2 = add <8 x i64> %res, %res1
ret <8 x i64> %res2 ret <8 x i64> %res2
} }
declare <8 x i64> @llvm.x86.avx512.maskz.pternlog.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i32, i8) declare <8 x i64> @llvm.x86.avx512.maskz.pternlog.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i32, i8)
define <8 x i64>@test_int_x86_avx512_maskz_pternlog_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x4) { define <8 x i64>@test_int_x86_avx512_maskz_pternlog_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_maskz_pternlog_q_512: ; CHECK-LABEL: test_int_x86_avx512_maskz_pternlog_q_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vpternlogq $33, %zmm2, %zmm1, %zmm3 {%k1} {z} ; CHECK-NEXT: vpternlogq $33, %zmm2, %zmm1, %zmm3 {%k1} {z}
; CHECK-NEXT: vpternlogq $33, %zmm2, %zmm1, %zmm0 ; CHECK-NEXT: vpternlogq $33, %zmm2, %zmm1, %zmm0
; CHECK-NEXT: vpaddq %zmm0, %zmm3, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm3, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.maskz.pternlog.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i32 33, i8 %x4) %res = call <8 x i64> @llvm.x86.avx512.maskz.pternlog.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i32 33, i8 %x4)
%res1 = call <8 x i64> @llvm.x86.avx512.maskz.pternlog.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i32 33, i8 -1) %res1 = call <8 x i64> @llvm.x86.avx512.maskz.pternlog.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i32 33, i8 -1)
%res2 = add <8 x i64> %res, %res1 %res2 = add <8 x i64> %res, %res1
Show All 40 Lines; CHECK-NEXT: retq
ret <16 x float> %res4 ret <16 x float> %res4
} }
declare <8 x double> @llvm.x86.avx512.mask.movddup.512(<8 x double>, <8 x double>, i8) declare <8 x double> @llvm.x86.avx512.mask.movddup.512(<8 x double>, <8 x double>, i8)
define <8 x double>@test_int_x86_avx512_mask_movddup_512(<8 x double> %x0, <8 x double> %x1, i8 %x2) { define <8 x double>@test_int_x86_avx512_mask_movddup_512(<8 x double> %x0, <8 x double> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_movddup_512: ; CHECK-LABEL: test_int_x86_avx512_mask_movddup_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovddup {{.*#+}} zmm1 = zmm0[0,0,2,2,4,4,6,6] ; CHECK-NEXT: vmovddup {{.*#+}} zmm1 = zmm0[0,0,2,2,4,4,6,6]
; CHECK-NEXT: vmovddup {{.*#+}} zmm2 = zmm0[0,0,2,2,4,4,6,6] ; CHECK-NEXT: vmovddup {{.*#+}} zmm2 = zmm0[0,0,2,2,4,4,6,6]
; CHECK-NEXT: vmovddup {{.*#+}} zmm0 = zmm0[0,0,2,2,4,4,6,6] ; CHECK-NEXT: vmovddup {{.*#+}} zmm0 = zmm0[0,0,2,2,4,4,6,6]
; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: vaddpd %zmm0, %zmm2, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm2, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.movddup.512(<8 x double> %x0, <8 x double> %x1, i8 %x2) %res = call <8 x double> @llvm.x86.avx512.mask.movddup.512(<8 x double> %x0, <8 x double> %x1, i8 %x2)
%res1 = call <8 x double> @llvm.x86.avx512.mask.movddup.512(<8 x double> %x0, <8 x double> %x1, i8 -1) %res1 = call <8 x double> @llvm.x86.avx512.mask.movddup.512(<8 x double> %x0, <8 x double> %x1, i8 -1)
▲ Show 20 Lines • Show All 171 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.move.sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) %res = call <2 x double> @llvm.x86.avx512.mask.move.sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3)
ret <2 x double> %res ret <2 x double> %res
} }
declare <16 x float> @llvm.x86.avx512.mask.broadcastf32x4.512(<4 x float>, <16 x float>, i16) declare <16 x float> @llvm.x86.avx512.mask.broadcastf32x4.512(<4 x float>, <16 x float>, i16)
define <16 x float>@test_int_x86_avx512_mask_broadcastf32x4_512(<4 x float> %x0, <16 x float> %x2, i16 %mask) { define <16 x float>@test_int_x86_avx512_mask_broadcastf32x4_512(<4 x float> %x0, <16 x float> %x2, i16 %mask) {
; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf32x4_512: ; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf32x4_512:
; CHECK: kmovw %edi, %k1 ; CHECK: ## BB#0:
; CHECK: vshuff32x4 $0, %zmm0, %zmm0, %zmm2 {%k1} {z} ; CHECK-NEXT: kmovw %edi, %k1
; CHECK: vshuff32x4 $0, %zmm0, %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vshuff32x4 {{.*#+}} zmm2 = zmm0[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
; CHECK: vshuff32x4 $0, %zmm0, %zmm0, %zmm0 ; CHECK-NEXT: vshuff32x4 {{.*#+}} zmm1 = zmm0[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
; CHECK: vaddps %zmm1, %zmm0, %zmm0 ; CHECK-NEXT: vshuff32x4 {{.*#+}} zmm0 = zmm0[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
; CHECK: vaddps %zmm0, %zmm2, %zmm0 ; CHECK-NEXT: vaddps %zmm1, %zmm0, %zmm0
; CHECK-NEXT: vaddps %zmm0, %zmm2, %zmm0
; CHECK-NEXT: retq
%res1 = call <16 x float> @llvm.x86.avx512.mask.broadcastf32x4.512(<4 x float> %x0, <16 x float> %x2, i16 -1) %res1 = call <16 x float> @llvm.x86.avx512.mask.broadcastf32x4.512(<4 x float> %x0, <16 x float> %x2, i16 -1)
%res2 = call <16 x float> @llvm.x86.avx512.mask.broadcastf32x4.512(<4 x float> %x0, <16 x float> %x2, i16 %mask) %res2 = call <16 x float> @llvm.x86.avx512.mask.broadcastf32x4.512(<4 x float> %x0, <16 x float> %x2, i16 %mask)
%res3 = call <16 x float> @llvm.x86.avx512.mask.broadcastf32x4.512(<4 x float> %x0, <16 x float> zeroinitializer, i16 %mask) %res3 = call <16 x float> @llvm.x86.avx512.mask.broadcastf32x4.512(<4 x float> %x0, <16 x float> zeroinitializer, i16 %mask)
%res4 = fadd <16 x float> %res1, %res2 %res4 = fadd <16 x float> %res1, %res2
%res5 = fadd <16 x float> %res3, %res4 %res5 = fadd <16 x float> %res3, %res4
ret <16 x float> %res5 ret <16 x float> %res5
} }
declare <8 x double> @llvm.x86.avx512.mask.broadcastf64x4.512(<4 x double>, <8 x double>, i8) declare <8 x double> @llvm.x86.avx512.mask.broadcastf64x4.512(<4 x double>, <8 x double>, i8)
define <8 x double>@test_int_x86_avx512_mask_broadcastf64x4_512(<4 x double> %x0, <8 x double> %x2, i8 %mask) { define <8 x double>@test_int_x86_avx512_mask_broadcastf64x4_512(<4 x double> %x0, <8 x double> %x2, i8 %mask) {
; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf64x4_512: ; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf64x4_512:
; CHECK: kmovw %eax, %k1 ; CHECK: ## BB#0:
; CHECK: vshuff64x2 $68, %zmm0, %zmm0, %zmm2 {%k1} {z} ; CHECK-NEXT: kmovw %edi, %k1
; CHECK: vshuff64x2 $68, %zmm0, %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm2 = zmm0[0,1,2,3,0,1,2,3]
; CHECK: vshuff64x2 $68, %zmm0, %zmm0, %zmm0 ; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm1 = zmm0[0,1,2,3,0,1,2,3]
; CHECK: vaddpd %zmm1, %zmm0, %zmm0 ; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3,0,1,2,3]
; CHECK: vaddpd %zmm0, %zmm2, %zmm0 ; CHECK-NEXT: vaddpd %zmm1, %zmm0, %zmm0
; CHECK-NEXT: vaddpd %zmm0, %zmm2, %zmm0
; CHECK-NEXT: retq
%res1 = call <8 x double> @llvm.x86.avx512.mask.broadcastf64x4.512(<4 x double> %x0, <8 x double> %x2, i8 -1) %res1 = call <8 x double> @llvm.x86.avx512.mask.broadcastf64x4.512(<4 x double> %x0, <8 x double> %x2, i8 -1)
%res2 = call <8 x double> @llvm.x86.avx512.mask.broadcastf64x4.512(<4 x double> %x0, <8 x double> %x2, i8 %mask) %res2 = call <8 x double> @llvm.x86.avx512.mask.broadcastf64x4.512(<4 x double> %x0, <8 x double> %x2, i8 %mask)
%res3 = call <8 x double> @llvm.x86.avx512.mask.broadcastf64x4.512(<4 x double> %x0, <8 x double> zeroinitializer, i8 %mask) %res3 = call <8 x double> @llvm.x86.avx512.mask.broadcastf64x4.512(<4 x double> %x0, <8 x double> zeroinitializer, i8 %mask)
%res4 = fadd <8 x double> %res1, %res2 %res4 = fadd <8 x double> %res1, %res2
%res5 = fadd <8 x double> %res3, %res4 %res5 = fadd <8 x double> %res3, %res4
ret <8 x double> %res5 ret <8 x double> %res5
} }
declare <16 x i32> @llvm.x86.avx512.mask.broadcasti32x4.512(<4 x i32>, <16 x i32>, i16) declare <16 x i32> @llvm.x86.avx512.mask.broadcasti32x4.512(<4 x i32>, <16 x i32>, i16)
define <16 x i32>@test_int_x86_avx512_mask_broadcasti32x4_512(<4 x i32> %x0, <16 x i32> %x2, i16 %mask) { define <16 x i32>@test_int_x86_avx512_mask_broadcasti32x4_512(<4 x i32> %x0, <16 x i32> %x2, i16 %mask) {
; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti32x4_512: ; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti32x4_512:
; CHECK: kmovw %edi, %k1 ; CHECK: ## BB#0:
; CHECK: vshufi32x4 $0, %zmm0, %zmm0, %zmm2 {%k1} {z} ; CHECK-NEXT: kmovw %edi, %k1
; CHECK: vshufi32x4 $0, %zmm0, %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vshufi32x4 {{.*#+}} zmm2 = zmm0[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
; CHECK: vshufi32x4 $0, %zmm0, %zmm0, %zmm0 ; CHECK-NEXT: vshufi32x4 {{.*#+}} zmm1 = zmm0[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
; CHECK: vpaddd %zmm1, %zmm0, %zmm0 ; CHECK-NEXT: vshufi32x4 {{.*#+}} zmm0 = zmm0[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
; CHECK: vpaddd %zmm0, %zmm2, %zmm0 ; CHECK-NEXT: vpaddd %zmm1, %zmm0, %zmm0
; CHECK-NEXT: vpaddd %zmm0, %zmm2, %zmm0
; CHECK-NEXT: retq
%res1 = call <16 x i32> @llvm.x86.avx512.mask.broadcasti32x4.512(<4 x i32> %x0, <16 x i32> %x2, i16 -1) %res1 = call <16 x i32> @llvm.x86.avx512.mask.broadcasti32x4.512(<4 x i32> %x0, <16 x i32> %x2, i16 -1)
%res2 = call <16 x i32> @llvm.x86.avx512.mask.broadcasti32x4.512(<4 x i32> %x0, <16 x i32> %x2, i16 %mask) %res2 = call <16 x i32> @llvm.x86.avx512.mask.broadcasti32x4.512(<4 x i32> %x0, <16 x i32> %x2, i16 %mask)
%res3 = call <16 x i32> @llvm.x86.avx512.mask.broadcasti32x4.512(<4 x i32> %x0, <16 x i32> zeroinitializer, i16 %mask) %res3 = call <16 x i32> @llvm.x86.avx512.mask.broadcasti32x4.512(<4 x i32> %x0, <16 x i32> zeroinitializer, i16 %mask)
%res4 = add <16 x i32> %res1, %res2 %res4 = add <16 x i32> %res1, %res2
%res5 = add <16 x i32> %res3, %res4 %res5 = add <16 x i32> %res3, %res4
ret <16 x i32> %res5 ret <16 x i32> %res5
} }
declare <8 x i64> @llvm.x86.avx512.mask.broadcasti64x4.512(<4 x i64>, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.broadcasti64x4.512(<4 x i64>, <8 x i64>, i8)
define <8 x i64>@test_int_x86_avx512_mask_broadcasti64x4_512(<4 x i64> %x0, <8 x i64> %x2, i8 %mask) { define <8 x i64>@test_int_x86_avx512_mask_broadcasti64x4_512(<4 x i64> %x0, <8 x i64> %x2, i8 %mask) {
; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti64x4_512: ; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti64x4_512:
; CHECK: kmovw %eax, %k1 ; CHECK: ## BB#0:
; CHECK: vshufi64x2 $68, %zmm0, %zmm0, %zmm2 {%k1} {z} ; CHECK-NEXT: kmovw %edi, %k1
; CHECK: vshufi64x2 $68, %zmm0, %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm0[0,1,2,3,0,1,2,3]
; CHECK: vshufi64x2 $68, %zmm0, %zmm0, %zmm0 ; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm1 = zmm0[0,1,2,3,0,1,2,3]
; CHECK: vpaddq %zmm1, %zmm0, %zmm0 ; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3,0,1,2,3]
; CHECK: vpaddq %zmm0, %zmm2, %zmm0 ; CHECK-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; CHECK-NEXT: vpaddq %zmm0, %zmm2, %zmm0
; CHECK-NEXT: retq
%res1 = call <8 x i64> @llvm.x86.avx512.mask.broadcasti64x4.512(<4 x i64> %x0, <8 x i64> %x2, i8 -1) %res1 = call <8 x i64> @llvm.x86.avx512.mask.broadcasti64x4.512(<4 x i64> %x0, <8 x i64> %x2, i8 -1)
%res2 = call <8 x i64> @llvm.x86.avx512.mask.broadcasti64x4.512(<4 x i64> %x0, <8 x i64> %x2, i8 %mask) %res2 = call <8 x i64> @llvm.x86.avx512.mask.broadcasti64x4.512(<4 x i64> %x0, <8 x i64> %x2, i8 %mask)
%res3 = call <8 x i64> @llvm.x86.avx512.mask.broadcasti64x4.512(<4 x i64> %x0, <8 x i64> zeroinitializer, i8 %mask) %res3 = call <8 x i64> @llvm.x86.avx512.mask.broadcasti64x4.512(<4 x i64> %x0, <8 x i64> zeroinitializer, i8 %mask)
%res4 = add <8 x i64> %res1, %res2 %res4 = add <8 x i64> %res1, %res2
%res5 = add <8 x i64> %res3, %res4 %res5 = add <8 x i64> %res3, %res4
ret <8 x i64> %res5 ret <8 x i64> %res5
} }
declare <8 x i64> @llvm.x86.avx512.mask.psrl.qi.512(<8 x i64>, i8, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.psrl.qi.512(<8 x i64>, i8, <8 x i64>, i8)
define <8 x i64>@test_int_x86_avx512_mask_psrl_qi_512(<8 x i64> %x0, i8 %x1, <8 x i64> %x2, i8 %x3) { define <8 x i64>@test_int_x86_avx512_mask_psrl_qi_512(<8 x i64> %x0, i8 %x1, <8 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psrl_qi_512: ; CHECK-LABEL: test_int_x86_avx512_mask_psrl_qi_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsrlq $255, %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vpsrlq $255, %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vpsrlq $255, %zmm0, %zmm2 {%k1} {z} ; CHECK-NEXT: vpsrlq $255, %zmm0, %zmm2 {%k1} {z}
; CHECK-NEXT: vpsrlq $255, %zmm0, %zmm0 ; CHECK-NEXT: vpsrlq $255, %zmm0, %zmm0
; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
; CHECK-NEXT: vpaddq %zmm2, %zmm0, %zmm0 ; CHECK-NEXT: vpaddq %zmm2, %zmm0, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psrl.qi.512(<8 x i64> %x0, i8 255, <8 x i64> %x2, i8 %x3) %res = call <8 x i64> @llvm.x86.avx512.mask.psrl.qi.512(<8 x i64> %x0, i8 255, <8 x i64> %x2, i8 %x3)
%res1 = call <8 x i64> @llvm.x86.avx512.mask.psrl.qi.512(<8 x i64> %x0, i8 255, <8 x i64> %x2, i8 -1) %res1 = call <8 x i64> @llvm.x86.avx512.mask.psrl.qi.512(<8 x i64> %x0, i8 255, <8 x i64> %x2, i8 -1)
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
ret <16 x i32> %res4 ret <16 x i32> %res4
} }
declare <8 x i64> @llvm.x86.avx512.mask.psra.qi.512(<8 x i64>, i8, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.psra.qi.512(<8 x i64>, i8, <8 x i64>, i8)
define <8 x i64>@test_int_x86_avx512_mask_psra_qi_512(<8 x i64> %x0, i8 %x1, <8 x i64> %x2, i8 %x3) { define <8 x i64>@test_int_x86_avx512_mask_psra_qi_512(<8 x i64> %x0, i8 %x1, <8 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psra_qi_512: ; CHECK-LABEL: test_int_x86_avx512_mask_psra_qi_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsraq $3, %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vpsraq $3, %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vpsraq $3, %zmm0, %zmm2 {%k1} {z} ; CHECK-NEXT: vpsraq $3, %zmm0, %zmm2 {%k1} {z}
; CHECK-NEXT: vpsraq $3, %zmm0, %zmm0 ; CHECK-NEXT: vpsraq $3, %zmm0, %zmm0
; CHECK-NEXT: vpaddq %zmm2, %zmm1, %zmm1 ; CHECK-NEXT: vpaddq %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psra.qi.512(<8 x i64> %x0, i8 3, <8 x i64> %x2, i8 %x3) %res = call <8 x i64> @llvm.x86.avx512.mask.psra.qi.512(<8 x i64> %x0, i8 3, <8 x i64> %x2, i8 %x3)
%res1 = call <8 x i64> @llvm.x86.avx512.mask.psra.qi.512(<8 x i64> %x0, i8 3, <8 x i64> zeroinitializer, i8 %x3) %res1 = call <8 x i64> @llvm.x86.avx512.mask.psra.qi.512(<8 x i64> %x0, i8 3, <8 x i64> zeroinitializer, i8 %x3)
Show All 23 Lines; CHECK-NEXT: retq
ret <16 x i32> %res4 ret <16 x i32> %res4
} }
declare <8 x i64> @llvm.x86.avx512.mask.psll.qi.512(<8 x i64>, i8, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.psll.qi.512(<8 x i64>, i8, <8 x i64>, i8)
define <8 x i64>@test_int_x86_avx512_mask_psll_qi_512(<8 x i64> %x0, i8 %x1, <8 x i64> %x2, i8 %x3) { define <8 x i64>@test_int_x86_avx512_mask_psll_qi_512(<8 x i64> %x0, i8 %x1, <8 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psll_qi_512: ; CHECK-LABEL: test_int_x86_avx512_mask_psll_qi_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsllq $3, %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vpsllq $3, %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vpsllq $3, %zmm0, %zmm2 {%k1} {z} ; CHECK-NEXT: vpsllq $3, %zmm0, %zmm2 {%k1} {z}
; CHECK-NEXT: vpsllq $3, %zmm0, %zmm0 ; CHECK-NEXT: vpsllq $3, %zmm0, %zmm0
; CHECK-NEXT: vpaddq %zmm2, %zmm1, %zmm1 ; CHECK-NEXT: vpaddq %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.psll.qi.512(<8 x i64> %x0, i8 3, <8 x i64> %x2, i8 %x3) %res = call <8 x i64> @llvm.x86.avx512.mask.psll.qi.512(<8 x i64> %x0, i8 3, <8 x i64> %x2, i8 %x3)
%res1 = call <8 x i64> @llvm.x86.avx512.mask.psll.qi.512(<8 x i64> %x0, i8 3, <8 x i64> zeroinitializer, i8 %x3) %res1 = call <8 x i64> @llvm.x86.avx512.mask.psll.qi.512(<8 x i64> %x0, i8 3, <8 x i64> zeroinitializer, i8 %x3)
%res2 = call <8 x i64> @llvm.x86.avx512.mask.psll.qi.512(<8 x i64> %x0, i8 3, <8 x i64> %x2, i8 -1) %res2 = call <8 x i64> @llvm.x86.avx512.mask.psll.qi.512(<8 x i64> %x0, i8 3, <8 x i64> %x2, i8 -1)
%res3 = add <8 x i64> %res, %res1 %res3 = add <8 x i64> %res, %res1
%res4 = add <8 x i64> %res3, %res2 %res4 = add <8 x i64> %res3, %res2
ret <8 x i64> %res4 ret <8 x i64> %res4
} }
declare <16 x i32> @llvm.x86.avx512.mask.pshuf.d.512(<16 x i32>, i16, <16 x i32>, i8) declare <16 x i32> @llvm.x86.avx512.mask.pshuf.d.512(<16 x i32>, i16, <16 x i32>, i8)
define <16 x i32>@test_int_x86_avx512_mask_pshuf_d_512(<16 x i32> %x0, i16 %x1, <16 x i32> %x2, i8 %x3) { define <16 x i32>@test_int_x86_avx512_mask_pshuf_d_512(<16 x i32> %x0, i16 %x1, <16 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_pshuf_d_512: ; CHECK-LABEL: test_int_x86_avx512_mask_pshuf_d_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %esi, %k1 ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: vpshufd $3, %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vpshufd $3, %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vpshufd $3, %zmm0, %zmm2 {%k1} {z} ; CHECK-NEXT: vpshufd $3, %zmm0, %zmm2 {%k1} {z}
; CHECK-NEXT: vpshufd $3, %zmm0, %zmm0 ; CHECK-NEXT: vpshufd $3, %zmm0, %zmm0
; CHECK-NEXT: vpaddd %zmm2, %zmm1, %zmm1 ; CHECK-NEXT: vpaddd %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpaddd %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vpaddd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <16 x i32> @llvm.x86.avx512.mask.pshuf.d.512(<16 x i32> %x0, i16 3, <16 x i32> %x2, i8 %x3) %res = call <16 x i32> @llvm.x86.avx512.mask.pshuf.d.512(<16 x i32> %x0, i16 3, <16 x i32> %x2, i8 %x3)
%res1 = call <16 x i32> @llvm.x86.avx512.mask.pshuf.d.512(<16 x i32> %x0, i16 3, <16 x i32> zeroinitializer, i8 %x3) %res1 = call <16 x i32> @llvm.x86.avx512.mask.pshuf.d.512(<16 x i32> %x0, i16 3, <16 x i32> zeroinitializer, i8 %x3)
%res2 = call <16 x i32> @llvm.x86.avx512.mask.pshuf.d.512(<16 x i32> %x0, i16 3, <16 x i32> %x2, i8 -1) %res2 = call <16 x i32> @llvm.x86.avx512.mask.pshuf.d.512(<16 x i32> %x0, i16 3, <16 x i32> %x2, i8 -1)
%res3 = add <16 x i32> %res, %res1 %res3 = add <16 x i32> %res, %res1
%res4 = add <16 x i32> %res3, %res2 %res4 = add <16 x i32> %res3, %res2
ret <16 x i32> %res4 ret <16 x i32> %res4
} }
declare <16 x i32> @llvm.x86.avx512.mask.prorv.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16) declare <16 x i32> @llvm.x86.avx512.mask.prorv.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
define <16 x i32>@test_int_x86_avx512_mask_prorv_d_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) { define <16 x i32>@test_int_x86_avx512_mask_prorv_d_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_prorv_d_512: ; CHECK-LABEL: test_int_x86_avx512_mask_prorv_d_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vprorvd %zmm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vprorvd %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vprorvd %zmm1, %zmm0, %zmm3 {%k1} {z} ; CHECK-NEXT: vprorvd %zmm1, %zmm0, %zmm3 {%k1} {z}
; CHECK-NEXT: vprorvd %zmm1, %zmm0, %zmm0 ; CHECK-NEXT: vprorvd %zmm1, %zmm0, %zmm0
; CHECK-NEXT: vpaddd %zmm3, %zmm2, %zmm1 ; CHECK-NEXT: vpaddd %zmm3, %zmm2, %zmm1
; CHECK-NEXT: vpaddd %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vpaddd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <16 x i32> @llvm.x86.avx512.mask.prorv.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) %res = call <16 x i32> @llvm.x86.avx512.mask.prorv.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3)
%res1 = call <16 x i32> @llvm.x86.avx512.mask.prorv.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> zeroinitializer, i16 %x3) %res1 = call <16 x i32> @llvm.x86.avx512.mask.prorv.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> zeroinitializer, i16 %x3)
%res2 = call <16 x i32> @llvm.x86.avx512.mask.prorv.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1) %res2 = call <16 x i32> @llvm.x86.avx512.mask.prorv.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1)
%res3 = add <16 x i32> %res, %res1 %res3 = add <16 x i32> %res, %res1
%res4 = add <16 x i32> %res3, %res2 %res4 = add <16 x i32> %res3, %res2
ret <16 x i32> %res4 ret <16 x i32> %res4
} }
declare <8 x i64> @llvm.x86.avx512.mask.prorv.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.prorv.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
define <8 x i64>@test_int_x86_avx512_mask_prorv_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) { define <8 x i64>@test_int_x86_avx512_mask_prorv_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_prorv_q_512: ; CHECK-LABEL: test_int_x86_avx512_mask_prorv_q_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vprorvq %zmm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vprorvq %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vprorvq %zmm1, %zmm0, %zmm3 {%k1} {z} ; CHECK-NEXT: vprorvq %zmm1, %zmm0, %zmm3 {%k1} {z}
; CHECK-NEXT: vprorvq %zmm1, %zmm0, %zmm0 ; CHECK-NEXT: vprorvq %zmm1, %zmm0, %zmm0
; CHECK-NEXT: vpaddq %zmm3, %zmm2, %zmm1 ; CHECK-NEXT: vpaddq %zmm3, %zmm2, %zmm1
; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.prorv.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) %res = call <8 x i64> @llvm.x86.avx512.mask.prorv.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3)
%res1 = call <8 x i64> @llvm.x86.avx512.mask.prorv.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> zeroinitializer, i8 %x3) %res1 = call <8 x i64> @llvm.x86.avx512.mask.prorv.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> zeroinitializer, i8 %x3)
%res2 = call <8 x i64> @llvm.x86.avx512.mask.prorv.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1) %res2 = call <8 x i64> @llvm.x86.avx512.mask.prorv.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1)
%res3 = add <8 x i64> %res, %res1 %res3 = add <8 x i64> %res, %res1
%res4 = add <8 x i64> %res3, %res2 %res4 = add <8 x i64> %res3, %res2
ret <8 x i64> %res4 ret <8 x i64> %res4
} }
declare <16 x i32> @llvm.x86.avx512.mask.prol.d.512(<16 x i32>, i8, <16 x i32>, i16) declare <16 x i32> @llvm.x86.avx512.mask.prol.d.512(<16 x i32>, i8, <16 x i32>, i16)
define <16 x i32>@test_int_x86_avx512_mask_prol_d_512(<16 x i32> %x0, i8 %x1, <16 x i32> %x2, i16 %x3) { define <16 x i32>@test_int_x86_avx512_mask_prol_d_512(<16 x i32> %x0, i8 %x1, <16 x i32> %x2, i16 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_prol_d_512: ; CHECK-LABEL: test_int_x86_avx512_mask_prol_d_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %esi, %k1 ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: vprold $3, %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vprold $3, %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vprold $3, %zmm0, %zmm2 {%k1} {z} ; CHECK-NEXT: vprold $3, %zmm0, %zmm2 {%k1} {z}
; CHECK-NEXT: vprold $3, %zmm0, %zmm0 ; CHECK-NEXT: vprold $3, %zmm0, %zmm0
; CHECK-NEXT: vpaddd %zmm2, %zmm1, %zmm1 ; CHECK-NEXT: vpaddd %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpaddd %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vpaddd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <16 x i32> @llvm.x86.avx512.mask.prol.d.512(<16 x i32> %x0, i8 3, <16 x i32> %x2, i16 %x3) %res = call <16 x i32> @llvm.x86.avx512.mask.prol.d.512(<16 x i32> %x0, i8 3, <16 x i32> %x2, i16 %x3)
%res1 = call <16 x i32> @llvm.x86.avx512.mask.prol.d.512(<16 x i32> %x0, i8 3, <16 x i32> zeroinitializer, i16 %x3) %res1 = call <16 x i32> @llvm.x86.avx512.mask.prol.d.512(<16 x i32> %x0, i8 3, <16 x i32> zeroinitializer, i16 %x3)
%res2 = call <16 x i32> @llvm.x86.avx512.mask.prol.d.512(<16 x i32> %x0, i8 3, <16 x i32> %x2, i16 -1) %res2 = call <16 x i32> @llvm.x86.avx512.mask.prol.d.512(<16 x i32> %x0, i8 3, <16 x i32> %x2, i16 -1)
%res3 = add <16 x i32> %res, %res1 %res3 = add <16 x i32> %res, %res1
%res4 = add <16 x i32> %res3, %res2 %res4 = add <16 x i32> %res3, %res2
ret <16 x i32> %res4 ret <16 x i32> %res4
} }
declare <8 x i64> @llvm.x86.avx512.mask.prol.q.512(<8 x i64>, i8, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.prol.q.512(<8 x i64>, i8, <8 x i64>, i8)
define <8 x i64>@test_int_x86_avx512_mask_prol_q_512(<8 x i64> %x0, i8 %x1, <8 x i64> %x2, i8 %x3) { define <8 x i64>@test_int_x86_avx512_mask_prol_q_512(<8 x i64> %x0, i8 %x1, <8 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_prol_q_512: ; CHECK-LABEL: test_int_x86_avx512_mask_prol_q_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vprolq $3, %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vprolq $3, %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vprolq $3, %zmm0, %zmm2 {%k1} {z} ; CHECK-NEXT: vprolq $3, %zmm0, %zmm2 {%k1} {z}
; CHECK-NEXT: vprolq $3, %zmm0, %zmm0 ; CHECK-NEXT: vprolq $3, %zmm0, %zmm0
; CHECK-NEXT: vpaddq %zmm2, %zmm1, %zmm1 ; CHECK-NEXT: vpaddq %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.prol.q.512(<8 x i64> %x0, i8 3, <8 x i64> %x2, i8 %x3) %res = call <8 x i64> @llvm.x86.avx512.mask.prol.q.512(<8 x i64> %x0, i8 3, <8 x i64> %x2, i8 %x3)
%res1 = call <8 x i64> @llvm.x86.avx512.mask.prol.q.512(<8 x i64> %x0, i8 3, <8 x i64> zeroinitializer, i8 %x3) %res1 = call <8 x i64> @llvm.x86.avx512.mask.prol.q.512(<8 x i64> %x0, i8 3, <8 x i64> zeroinitializer, i8 %x3)
%res2 = call <8 x i64> @llvm.x86.avx512.mask.prol.q.512(<8 x i64> %x0, i8 3, <8 x i64> %x2, i8 -1) %res2 = call <8 x i64> @llvm.x86.avx512.mask.prol.q.512(<8 x i64> %x0, i8 3, <8 x i64> %x2, i8 -1)
%res3 = add <8 x i64> %res, %res1 %res3 = add <8 x i64> %res, %res1
%res4 = add <8 x i64> %res3, %res2 %res4 = add <8 x i64> %res3, %res2
ret <8 x i64> %res4 ret <8 x i64> %res4
} }
Show All 15 Lines; CHECK-NEXT: retq
ret <16 x i32> %res4 ret <16 x i32> %res4
} }
declare <8 x i64> @llvm.x86.avx512.mask.load.q.512(i8*, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.load.q.512(i8*, <8 x i64>, i8)
define <8 x i64> @test_mask_load_aligned_q(<8 x i64> %data, i8* %ptr, i8 %mask) { define <8 x i64> @test_mask_load_aligned_q(<8 x i64> %data, i8* %ptr, i8 %mask) {
; CHECK-LABEL: test_mask_load_aligned_q: ; CHECK-LABEL: test_mask_load_aligned_q:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovdqa64 (%rdi), %zmm0 ; CHECK-NEXT: vmovdqa64 (%rdi), %zmm0
; CHECK-NEXT: vmovdqa64 (%rdi), %zmm0 {%k1} ; CHECK-NEXT: vmovdqa64 (%rdi), %zmm0 {%k1}
; CHECK-NEXT: vmovdqa64 (%rdi), %zmm1 {%k1} {z} ; CHECK-NEXT: vmovdqa64 (%rdi), %zmm1 {%k1} {z}
; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.load.q.512(i8* %ptr, <8 x i64> zeroinitializer, i8 -1) %res = call <8 x i64> @llvm.x86.avx512.mask.load.q.512(i8* %ptr, <8 x i64> zeroinitializer, i8 -1)
%res1 = call <8 x i64> @llvm.x86.avx512.mask.load.q.512(i8* %ptr, <8 x i64> %res, i8 %mask) %res1 = call <8 x i64> @llvm.x86.avx512.mask.load.q.512(i8* %ptr, <8 x i64> %res, i8 %mask)
%res2 = call <8 x i64> @llvm.x86.avx512.mask.load.q.512(i8* %ptr, <8 x i64> zeroinitializer, i8 %mask) %res2 = call <8 x i64> @llvm.x86.avx512.mask.load.q.512(i8* %ptr, <8 x i64> zeroinitializer, i8 %mask)
%res4 = add <8 x i64> %res2, %res1 %res4 = add <8 x i64> %res2, %res1
ret <8 x i64> %res4 ret <8 x i64> %res4
} }
declare <16 x i32> @llvm.x86.avx512.mask.pmovzxb.d.512(<16 x i8>, <16 x i32>, i16) declare <16 x i32> @llvm.x86.avx512.mask.pmovzxb.d.512(<16 x i8>, <16 x i32>, i16)
define <16 x i32>@test_int_x86_avx512_mask_pmovzxb_d_512(<16 x i8> %x0, <16 x i32> %x1, i16 %x2) { define <16 x i32>@test_int_x86_avx512_mask_pmovzxb_d_512(<16 x i8> %x0, <16 x i32> %x1, i16 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxb_d_512: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxb_d_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vpmovzxbd %xmm0, %zmm1 {%k1} ; CHECK-NEXT: vpmovzxbd %xmm0, %zmm1 {%k1}
; CHECK-NEXT: vpmovzxbd %xmm0, %zmm2 {%k1} {z} ; CHECK-NEXT: vpmovzxbd %xmm0, %zmm2 {%k1} {z}
; CHECK-NEXT: vpmovzxbd %xmm0, %zmm0 ; CHECK-NEXT: vpmovzxbd %xmm0, %zmm0
; CHECK-NEXT: vpaddd %zmm2, %zmm1, %zmm1 ; CHECK-NEXT: vpaddd %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpaddd %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vpaddd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <16 x i32> @llvm.x86.avx512.mask.pmovzxb.d.512(<16 x i8> %x0, <16 x i32> %x1, i16 %x2) %res = call <16 x i32> @llvm.x86.avx512.mask.pmovzxb.d.512(<16 x i8> %x0, <16 x i32> %x1, i16 %x2)
%res1 = call <16 x i32> @llvm.x86.avx512.mask.pmovzxb.d.512(<16 x i8> %x0, <16 x i32> zeroinitializer, i16 %x2) %res1 = call <16 x i32> @llvm.x86.avx512.mask.pmovzxb.d.512(<16 x i8> %x0, <16 x i32> zeroinitializer, i16 %x2)
%res2 = call <16 x i32> @llvm.x86.avx512.mask.pmovzxb.d.512(<16 x i8> %x0, <16 x i32> %x1, i16 -1) %res2 = call <16 x i32> @llvm.x86.avx512.mask.pmovzxb.d.512(<16 x i8> %x0, <16 x i32> %x1, i16 -1)
%res3 = add <16 x i32> %res, %res1 %res3 = add <16 x i32> %res, %res1
%res4 = add <16 x i32> %res3, %res2 %res4 = add <16 x i32> %res3, %res2
ret <16 x i32> %res4 ret <16 x i32> %res4
} }
declare <8 x i64> @llvm.x86.avx512.mask.pmovzxb.q.512(<16 x i8>, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.pmovzxb.q.512(<16 x i8>, <8 x i64>, i8)
define <8 x i64>@test_int_x86_avx512_mask_pmovzxb_q_512(<16 x i8> %x0, <8 x i64> %x1, i8 %x2) { define <8 x i64>@test_int_x86_avx512_mask_pmovzxb_q_512(<16 x i8> %x0, <8 x i64> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxb_q_512: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxb_q_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovzxbq %xmm0, %zmm1 {%k1} ; CHECK-NEXT: vpmovzxbq %xmm0, %zmm1 {%k1}
; CHECK-NEXT: vpmovzxbq %xmm0, %zmm2 {%k1} {z} ; CHECK-NEXT: vpmovzxbq %xmm0, %zmm2 {%k1} {z}
; CHECK-NEXT: vpmovzxbq %xmm0, %zmm0 ; CHECK-NEXT: vpmovzxbq %xmm0, %zmm0
; CHECK-NEXT: vpaddq %zmm2, %zmm1, %zmm1 ; CHECK-NEXT: vpaddq %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.pmovzxb.q.512(<16 x i8> %x0, <8 x i64> %x1, i8 %x2) %res = call <8 x i64> @llvm.x86.avx512.mask.pmovzxb.q.512(<16 x i8> %x0, <8 x i64> %x1, i8 %x2)
%res1 = call <8 x i64> @llvm.x86.avx512.mask.pmovzxb.q.512(<16 x i8> %x0, <8 x i64> zeroinitializer, i8 %x2) %res1 = call <8 x i64> @llvm.x86.avx512.mask.pmovzxb.q.512(<16 x i8> %x0, <8 x i64> zeroinitializer, i8 %x2)
%res2 = call <8 x i64> @llvm.x86.avx512.mask.pmovzxb.q.512(<16 x i8> %x0, <8 x i64> %x1, i8 -1) %res2 = call <8 x i64> @llvm.x86.avx512.mask.pmovzxb.q.512(<16 x i8> %x0, <8 x i64> %x1, i8 -1)
%res3 = add <8 x i64> %res, %res1 %res3 = add <8 x i64> %res, %res1
%res4 = add <8 x i64> %res3, %res2 %res4 = add <8 x i64> %res3, %res2
ret <8 x i64> %res4 ret <8 x i64> %res4
} }
declare <8 x i64> @llvm.x86.avx512.mask.pmovzxd.q.512(<8 x i32>, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.pmovzxd.q.512(<8 x i32>, <8 x i64>, i8)
define <8 x i64>@test_int_x86_avx512_mask_pmovzxd_q_512(<8 x i32> %x0, <8 x i64> %x1, i8 %x2) { define <8 x i64>@test_int_x86_avx512_mask_pmovzxd_q_512(<8 x i32> %x0, <8 x i64> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxd_q_512: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxd_q_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovzxdq %ymm0, %zmm1 {%k1} ; CHECK-NEXT: vpmovzxdq %ymm0, %zmm1 {%k1}
; CHECK-NEXT: vpmovzxdq %ymm0, %zmm2 {%k1} {z} ; CHECK-NEXT: vpmovzxdq %ymm0, %zmm2 {%k1} {z}
; CHECK-NEXT: vpmovzxdq %ymm0, %zmm0 ; CHECK-NEXT: vpmovzxdq %ymm0, %zmm0
; CHECK-NEXT: vpaddq %zmm2, %zmm1, %zmm1 ; CHECK-NEXT: vpaddq %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.pmovzxd.q.512(<8 x i32> %x0, <8 x i64> %x1, i8 %x2) %res = call <8 x i64> @llvm.x86.avx512.mask.pmovzxd.q.512(<8 x i32> %x0, <8 x i64> %x1, i8 %x2)
%res1 = call <8 x i64> @llvm.x86.avx512.mask.pmovzxd.q.512(<8 x i32> %x0, <8 x i64> zeroinitializer, i8 %x2) %res1 = call <8 x i64> @llvm.x86.avx512.mask.pmovzxd.q.512(<8 x i32> %x0, <8 x i64> zeroinitializer, i8 %x2)
%res2 = call <8 x i64> @llvm.x86.avx512.mask.pmovzxd.q.512(<8 x i32> %x0, <8 x i64> %x1, i8 -1) %res2 = call <8 x i64> @llvm.x86.avx512.mask.pmovzxd.q.512(<8 x i32> %x0, <8 x i64> %x1, i8 -1)
%res3 = add <8 x i64> %res, %res1 %res3 = add <8 x i64> %res, %res1
%res4 = add <8 x i64> %res3, %res2 %res4 = add <8 x i64> %res3, %res2
ret <8 x i64> %res4 ret <8 x i64> %res4
} }
declare <16 x i32> @llvm.x86.avx512.mask.pmovzxw.d.512(<16 x i16>, <16 x i32>, i16) declare <16 x i32> @llvm.x86.avx512.mask.pmovzxw.d.512(<16 x i16>, <16 x i32>, i16)
define <16 x i32>@test_int_x86_avx512_mask_pmovzxw_d_512(<16 x i16> %x0, <16 x i32> %x1, i16 %x2) { define <16 x i32>@test_int_x86_avx512_mask_pmovzxw_d_512(<16 x i16> %x0, <16 x i32> %x1, i16 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxw_d_512: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxw_d_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vpmovzxwd %ymm0, %zmm1 {%k1} ; CHECK-NEXT: vpmovzxwd %ymm0, %zmm1 {%k1}
; CHECK-NEXT: vpmovzxwd %ymm0, %zmm2 {%k1} {z} ; CHECK-NEXT: vpmovzxwd %ymm0, %zmm2 {%k1} {z}
; CHECK-NEXT: vpmovzxwd %ymm0, %zmm0 ; CHECK-NEXT: vpmovzxwd %ymm0, %zmm0
; CHECK-NEXT: vpaddd %zmm2, %zmm1, %zmm1 ; CHECK-NEXT: vpaddd %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpaddd %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vpaddd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <16 x i32> @llvm.x86.avx512.mask.pmovzxw.d.512(<16 x i16> %x0, <16 x i32> %x1, i16 %x2) %res = call <16 x i32> @llvm.x86.avx512.mask.pmovzxw.d.512(<16 x i16> %x0, <16 x i32> %x1, i16 %x2)
%res1 = call <16 x i32> @llvm.x86.avx512.mask.pmovzxw.d.512(<16 x i16> %x0, <16 x i32> zeroinitializer, i16 %x2) %res1 = call <16 x i32> @llvm.x86.avx512.mask.pmovzxw.d.512(<16 x i16> %x0, <16 x i32> zeroinitializer, i16 %x2)
%res2 = call <16 x i32> @llvm.x86.avx512.mask.pmovzxw.d.512(<16 x i16> %x0, <16 x i32> %x1, i16 -1) %res2 = call <16 x i32> @llvm.x86.avx512.mask.pmovzxw.d.512(<16 x i16> %x0, <16 x i32> %x1, i16 -1)
%res3 = add <16 x i32> %res, %res1 %res3 = add <16 x i32> %res, %res1
%res4 = add <16 x i32> %res3, %res2 %res4 = add <16 x i32> %res3, %res2
ret <16 x i32> %res4 ret <16 x i32> %res4
} }
declare <8 x i64> @llvm.x86.avx512.mask.pmovzxw.q.512(<8 x i16>, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.pmovzxw.q.512(<8 x i16>, <8 x i64>, i8)
define <8 x i64>@test_int_x86_avx512_mask_pmovzxw_q_512(<8 x i16> %x0, <8 x i64> %x1, i8 %x2) { define <8 x i64>@test_int_x86_avx512_mask_pmovzxw_q_512(<8 x i16> %x0, <8 x i64> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxw_q_512: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxw_q_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovzxwq %xmm0, %zmm1 {%k1} ; CHECK-NEXT: vpmovzxwq %xmm0, %zmm1 {%k1}
; CHECK-NEXT: vpmovzxwq %xmm0, %zmm2 {%k1} {z} ; CHECK-NEXT: vpmovzxwq %xmm0, %zmm2 {%k1} {z}
; CHECK-NEXT: vpmovzxwq %xmm0, %zmm0 ; CHECK-NEXT: vpmovzxwq %xmm0, %zmm0
; CHECK-NEXT: vpaddq %zmm2, %zmm1, %zmm1 ; CHECK-NEXT: vpaddq %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.pmovzxw.q.512(<8 x i16> %x0, <8 x i64> %x1, i8 %x2) %res = call <8 x i64> @llvm.x86.avx512.mask.pmovzxw.q.512(<8 x i16> %x0, <8 x i64> %x1, i8 %x2)
%res1 = call <8 x i64> @llvm.x86.avx512.mask.pmovzxw.q.512(<8 x i16> %x0, <8 x i64> zeroinitializer, i8 %x2) %res1 = call <8 x i64> @llvm.x86.avx512.mask.pmovzxw.q.512(<8 x i16> %x0, <8 x i64> zeroinitializer, i8 %x2)
%res2 = call <8 x i64> @llvm.x86.avx512.mask.pmovzxw.q.512(<8 x i16> %x0, <8 x i64> %x1, i8 -1) %res2 = call <8 x i64> @llvm.x86.avx512.mask.pmovzxw.q.512(<8 x i16> %x0, <8 x i64> %x1, i8 -1)
%res3 = add <8 x i64> %res, %res1 %res3 = add <8 x i64> %res, %res1
%res4 = add <8 x i64> %res3, %res2 %res4 = add <8 x i64> %res3, %res2
ret <8 x i64> %res4 ret <8 x i64> %res4
} }
declare <16 x i32> @llvm.x86.avx512.mask.pmovsxb.d.512(<16 x i8>, <16 x i32>, i16) declare <16 x i32> @llvm.x86.avx512.mask.pmovsxb.d.512(<16 x i8>, <16 x i32>, i16)
define <16 x i32>@test_int_x86_avx512_mask_pmovsxb_d_512(<16 x i8> %x0, <16 x i32> %x1, i16 %x2) { define <16 x i32>@test_int_x86_avx512_mask_pmovsxb_d_512(<16 x i8> %x0, <16 x i32> %x1, i16 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxb_d_512: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxb_d_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vpmovsxbd %xmm0, %zmm1 {%k1} ; CHECK-NEXT: vpmovsxbd %xmm0, %zmm1 {%k1}
; CHECK-NEXT: vpmovsxbd %xmm0, %zmm2 {%k1} {z} ; CHECK-NEXT: vpmovsxbd %xmm0, %zmm2 {%k1} {z}
; CHECK-NEXT: vpmovsxbd %xmm0, %zmm0 ; CHECK-NEXT: vpmovsxbd %xmm0, %zmm0
; CHECK-NEXT: vpaddd %zmm2, %zmm1, %zmm1 ; CHECK-NEXT: vpaddd %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpaddd %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vpaddd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <16 x i32> @llvm.x86.avx512.mask.pmovsxb.d.512(<16 x i8> %x0, <16 x i32> %x1, i16 %x2) %res = call <16 x i32> @llvm.x86.avx512.mask.pmovsxb.d.512(<16 x i8> %x0, <16 x i32> %x1, i16 %x2)
%res1 = call <16 x i32> @llvm.x86.avx512.mask.pmovsxb.d.512(<16 x i8> %x0, <16 x i32> zeroinitializer, i16 %x2) %res1 = call <16 x i32> @llvm.x86.avx512.mask.pmovsxb.d.512(<16 x i8> %x0, <16 x i32> zeroinitializer, i16 %x2)
%res2 = call <16 x i32> @llvm.x86.avx512.mask.pmovsxb.d.512(<16 x i8> %x0, <16 x i32> %x1, i16 -1) %res2 = call <16 x i32> @llvm.x86.avx512.mask.pmovsxb.d.512(<16 x i8> %x0, <16 x i32> %x1, i16 -1)
%res3 = add <16 x i32> %res, %res1 %res3 = add <16 x i32> %res, %res1
%res4 = add <16 x i32> %res3, %res2 %res4 = add <16 x i32> %res3, %res2
ret <16 x i32> %res4 ret <16 x i32> %res4
} }
declare <8 x i64> @llvm.x86.avx512.mask.pmovsxb.q.512(<16 x i8>, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.pmovsxb.q.512(<16 x i8>, <8 x i64>, i8)
define <8 x i64>@test_int_x86_avx512_mask_pmovsxb_q_512(<16 x i8> %x0, <8 x i64> %x1, i8 %x2) { define <8 x i64>@test_int_x86_avx512_mask_pmovsxb_q_512(<16 x i8> %x0, <8 x i64> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxb_q_512: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxb_q_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovsxbq %xmm0, %zmm1 {%k1} ; CHECK-NEXT: vpmovsxbq %xmm0, %zmm1 {%k1}
; CHECK-NEXT: vpmovsxbq %xmm0, %zmm2 {%k1} {z} ; CHECK-NEXT: vpmovsxbq %xmm0, %zmm2 {%k1} {z}
; CHECK-NEXT: vpmovsxbq %xmm0, %zmm0 ; CHECK-NEXT: vpmovsxbq %xmm0, %zmm0
; CHECK-NEXT: vpaddq %zmm2, %zmm1, %zmm1 ; CHECK-NEXT: vpaddq %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.pmovsxb.q.512(<16 x i8> %x0, <8 x i64> %x1, i8 %x2) %res = call <8 x i64> @llvm.x86.avx512.mask.pmovsxb.q.512(<16 x i8> %x0, <8 x i64> %x1, i8 %x2)
%res1 = call <8 x i64> @llvm.x86.avx512.mask.pmovsxb.q.512(<16 x i8> %x0, <8 x i64> zeroinitializer, i8 %x2) %res1 = call <8 x i64> @llvm.x86.avx512.mask.pmovsxb.q.512(<16 x i8> %x0, <8 x i64> zeroinitializer, i8 %x2)
%res2 = call <8 x i64> @llvm.x86.avx512.mask.pmovsxb.q.512(<16 x i8> %x0, <8 x i64> %x1, i8 -1) %res2 = call <8 x i64> @llvm.x86.avx512.mask.pmovsxb.q.512(<16 x i8> %x0, <8 x i64> %x1, i8 -1)
%res3 = add <8 x i64> %res, %res1 %res3 = add <8 x i64> %res, %res1
%res4 = add <8 x i64> %res3, %res2 %res4 = add <8 x i64> %res3, %res2
ret <8 x i64> %res4 ret <8 x i64> %res4
} }
declare <8 x i64> @llvm.x86.avx512.mask.pmovsxd.q.512(<8 x i32>, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.pmovsxd.q.512(<8 x i32>, <8 x i64>, i8)
define <8 x i64>@test_int_x86_avx512_mask_pmovsxd_q_512(<8 x i32> %x0, <8 x i64> %x1, i8 %x2) { define <8 x i64>@test_int_x86_avx512_mask_pmovsxd_q_512(<8 x i32> %x0, <8 x i64> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxd_q_512: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxd_q_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovsxdq %ymm0, %zmm1 {%k1} ; CHECK-NEXT: vpmovsxdq %ymm0, %zmm1 {%k1}
; CHECK-NEXT: vpmovsxdq %ymm0, %zmm2 {%k1} {z} ; CHECK-NEXT: vpmovsxdq %ymm0, %zmm2 {%k1} {z}
; CHECK-NEXT: vpmovsxdq %ymm0, %zmm0 ; CHECK-NEXT: vpmovsxdq %ymm0, %zmm0
; CHECK-NEXT: vpaddq %zmm2, %zmm1, %zmm1 ; CHECK-NEXT: vpaddq %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.pmovsxd.q.512(<8 x i32> %x0, <8 x i64> %x1, i8 %x2) %res = call <8 x i64> @llvm.x86.avx512.mask.pmovsxd.q.512(<8 x i32> %x0, <8 x i64> %x1, i8 %x2)
%res1 = call <8 x i64> @llvm.x86.avx512.mask.pmovsxd.q.512(<8 x i32> %x0, <8 x i64> zeroinitializer, i8 %x2) %res1 = call <8 x i64> @llvm.x86.avx512.mask.pmovsxd.q.512(<8 x i32> %x0, <8 x i64> zeroinitializer, i8 %x2)
%res2 = call <8 x i64> @llvm.x86.avx512.mask.pmovsxd.q.512(<8 x i32> %x0, <8 x i64> %x1, i8 -1) %res2 = call <8 x i64> @llvm.x86.avx512.mask.pmovsxd.q.512(<8 x i32> %x0, <8 x i64> %x1, i8 -1)
%res3 = add <8 x i64> %res, %res1 %res3 = add <8 x i64> %res, %res1
%res4 = add <8 x i64> %res3, %res2 %res4 = add <8 x i64> %res3, %res2
ret <8 x i64> %res4 ret <8 x i64> %res4
} }
declare <16 x i32> @llvm.x86.avx512.mask.pmovsxw.d.512(<16 x i16>, <16 x i32>, i16) declare <16 x i32> @llvm.x86.avx512.mask.pmovsxw.d.512(<16 x i16>, <16 x i32>, i16)
define <16 x i32>@test_int_x86_avx512_mask_pmovsxw_d_512(<16 x i16> %x0, <16 x i32> %x1, i16 %x2) { define <16 x i32>@test_int_x86_avx512_mask_pmovsxw_d_512(<16 x i16> %x0, <16 x i32> %x1, i16 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxw_d_512: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxw_d_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vpmovsxwd %ymm0, %zmm1 {%k1} ; CHECK-NEXT: vpmovsxwd %ymm0, %zmm1 {%k1}
; CHECK-NEXT: vpmovsxwd %ymm0, %zmm2 {%k1} {z} ; CHECK-NEXT: vpmovsxwd %ymm0, %zmm2 {%k1} {z}
; CHECK-NEXT: vpmovsxwd %ymm0, %zmm0 ; CHECK-NEXT: vpmovsxwd %ymm0, %zmm0
; CHECK-NEXT: vpaddd %zmm2, %zmm1, %zmm1 ; CHECK-NEXT: vpaddd %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpaddd %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vpaddd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <16 x i32> @llvm.x86.avx512.mask.pmovsxw.d.512(<16 x i16> %x0, <16 x i32> %x1, i16 %x2) %res = call <16 x i32> @llvm.x86.avx512.mask.pmovsxw.d.512(<16 x i16> %x0, <16 x i32> %x1, i16 %x2)
%res1 = call <16 x i32> @llvm.x86.avx512.mask.pmovsxw.d.512(<16 x i16> %x0, <16 x i32> zeroinitializer, i16 %x2) %res1 = call <16 x i32> @llvm.x86.avx512.mask.pmovsxw.d.512(<16 x i16> %x0, <16 x i32> zeroinitializer, i16 %x2)
%res2 = call <16 x i32> @llvm.x86.avx512.mask.pmovsxw.d.512(<16 x i16> %x0, <16 x i32> %x1, i16 -1) %res2 = call <16 x i32> @llvm.x86.avx512.mask.pmovsxw.d.512(<16 x i16> %x0, <16 x i32> %x1, i16 -1)
%res3 = add <16 x i32> %res, %res1 %res3 = add <16 x i32> %res, %res1
%res4 = add <16 x i32> %res3, %res2 %res4 = add <16 x i32> %res3, %res2
ret <16 x i32> %res4 ret <16 x i32> %res4
} }
declare <8 x i64> @llvm.x86.avx512.mask.pmovsxw.q.512(<8 x i16>, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.pmovsxw.q.512(<8 x i16>, <8 x i64>, i8)
define <8 x i64>@test_int_x86_avx512_mask_pmovsxw_q_512(<8 x i16> %x0, <8 x i64> %x1, i8 %x2) { define <8 x i64>@test_int_x86_avx512_mask_pmovsxw_q_512(<8 x i16> %x0, <8 x i64> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxw_q_512: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxw_q_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovsxwq %xmm0, %zmm1 {%k1} ; CHECK-NEXT: vpmovsxwq %xmm0, %zmm1 {%k1}
; CHECK-NEXT: vpmovsxwq %xmm0, %zmm2 {%k1} {z} ; CHECK-NEXT: vpmovsxwq %xmm0, %zmm2 {%k1} {z}
; CHECK-NEXT: vpmovsxwq %xmm0, %zmm0 ; CHECK-NEXT: vpmovsxwq %xmm0, %zmm0
; CHECK-NEXT: vpaddq %zmm2, %zmm1, %zmm1 ; CHECK-NEXT: vpaddq %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.pmovsxw.q.512(<8 x i16> %x0, <8 x i64> %x1, i8 %x2) %res = call <8 x i64> @llvm.x86.avx512.mask.pmovsxw.q.512(<8 x i16> %x0, <8 x i64> %x1, i8 %x2)
%res1 = call <8 x i64> @llvm.x86.avx512.mask.pmovsxw.q.512(<8 x i16> %x0, <8 x i64> zeroinitializer, i8 %x2) %res1 = call <8 x i64> @llvm.x86.avx512.mask.pmovsxw.q.512(<8 x i16> %x0, <8 x i64> zeroinitializer, i8 %x2)
%res2 = call <8 x i64> @llvm.x86.avx512.mask.pmovsxw.q.512(<8 x i16> %x0, <8 x i64> %x1, i8 -1) %res2 = call <8 x i64> @llvm.x86.avx512.mask.pmovsxw.q.512(<8 x i16> %x0, <8 x i64> %x1, i8 -1)
%res3 = add <8 x i64> %res, %res1 %res3 = add <8 x i64> %res, %res1
%res4 = add <8 x i64> %res3, %res2 %res4 = add <8 x i64> %res3, %res2
ret <8 x i64> %res4 ret <8 x i64> %res4
} }
declare <8 x double> @llvm.x86.avx512.mask.perm.df.512(<8 x double>, i8, <8 x double>, i8) declare <8 x double> @llvm.x86.avx512.mask.perm.df.512(<8 x double>, i8, <8 x double>, i8)
define <8 x double>@test_int_x86_avx512_mask_perm_df_512(<8 x double> %x0, i8 %x1, <8 x double> %x2, i8 %x3) { define <8 x double>@test_int_x86_avx512_mask_perm_df_512(<8 x double> %x0, i8 %x1, <8 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_perm_df_512: ; CHECK-LABEL: test_int_x86_avx512_mask_perm_df_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpermpd $3, %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vpermpd $3, %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vpermpd $3, %zmm0, %zmm2 {%k1} {z} ; CHECK-NEXT: vpermpd $3, %zmm0, %zmm2 {%k1} {z}
; CHECK-NEXT: vpermpd $3, %zmm0, %zmm0 ; CHECK-NEXT: vpermpd $3, %zmm0, %zmm0
; CHECK-NEXT: vaddpd %zmm2, %zmm1, %zmm1 ; CHECK-NEXT: vaddpd %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.perm.df.512(<8 x double> %x0, i8 3, <8 x double> %x2, i8 %x3) %res = call <8 x double> @llvm.x86.avx512.mask.perm.df.512(<8 x double> %x0, i8 3, <8 x double> %x2, i8 %x3)
%res1 = call <8 x double> @llvm.x86.avx512.mask.perm.df.512(<8 x double> %x0, i8 3, <8 x double> zeroinitializer, i8 %x3) %res1 = call <8 x double> @llvm.x86.avx512.mask.perm.df.512(<8 x double> %x0, i8 3, <8 x double> zeroinitializer, i8 %x3)
%res2 = call <8 x double> @llvm.x86.avx512.mask.perm.df.512(<8 x double> %x0, i8 3, <8 x double> %x2, i8 -1) %res2 = call <8 x double> @llvm.x86.avx512.mask.perm.df.512(<8 x double> %x0, i8 3, <8 x double> %x2, i8 -1)
%res3 = fadd <8 x double> %res, %res1 %res3 = fadd <8 x double> %res, %res1
%res4 = fadd <8 x double> %res3, %res2 %res4 = fadd <8 x double> %res3, %res2
ret <8 x double> %res4 ret <8 x double> %res4
} }
declare <8 x i64> @llvm.x86.avx512.mask.perm.di.512(<8 x i64>, i8, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.perm.di.512(<8 x i64>, i8, <8 x i64>, i8)
define <8 x i64>@test_int_x86_avx512_mask_perm_di_512(<8 x i64> %x0, i8 %x1, <8 x i64> %x2, i8 %x3) { define <8 x i64>@test_int_x86_avx512_mask_perm_di_512(<8 x i64> %x0, i8 %x1, <8 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_perm_di_512: ; CHECK-LABEL: test_int_x86_avx512_mask_perm_di_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpermq $3, %zmm0, %zmm1 {%k1} ; CHECK-NEXT: vpermq $3, %zmm0, %zmm1 {%k1}
; CHECK-NEXT: vpermq $3, %zmm0, %zmm2 {%k1} {z} ; CHECK-NEXT: vpermq $3, %zmm0, %zmm2 {%k1} {z}
; CHECK-NEXT: vpermq $3, %zmm0, %zmm0 ; CHECK-NEXT: vpermq $3, %zmm0, %zmm0
; CHECK-NEXT: vpaddq %zmm2, %zmm1, %zmm1 ; CHECK-NEXT: vpaddq %zmm2, %zmm1, %zmm1
; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.perm.di.512(<8 x i64> %x0, i8 3, <8 x i64> %x2, i8 %x3) %res = call <8 x i64> @llvm.x86.avx512.mask.perm.di.512(<8 x i64> %x0, i8 3, <8 x i64> %x2, i8 %x3)
%res1 = call <8 x i64> @llvm.x86.avx512.mask.perm.di.512(<8 x i64> %x0, i8 3, <8 x i64> zeroinitializer, i8 %x3) %res1 = call <8 x i64> @llvm.x86.avx512.mask.perm.di.512(<8 x i64> %x0, i8 3, <8 x i64> zeroinitializer, i8 %x3)
%res2 = call <8 x i64> @llvm.x86.avx512.mask.perm.di.512(<8 x i64> %x0, i8 3, <8 x i64> %x2, i8 -1) %res2 = call <8 x i64> @llvm.x86.avx512.mask.perm.di.512(<8 x i64> %x0, i8 3, <8 x i64> %x2, i8 -1)
%res3 = add <8 x i64> %res, %res1 %res3 = add <8 x i64> %res, %res1
%res4 = add <8 x i64> %res3, %res2 %res4 = add <8 x i64> %res3, %res2
ret <8 x i64> %res4 ret <8 x i64> %res4
} }
declare <8 x double> @llvm.x86.avx512.mask.permvar.df.512(<8 x double>, <8 x i64>, <8 x double>, i8) declare <8 x double> @llvm.x86.avx512.mask.permvar.df.512(<8 x double>, <8 x i64>, <8 x double>, i8)
define <8 x double>@test_int_x86_avx512_mask_permvar_df_512(<8 x double> %x0, <8 x i64> %x1, <8 x double> %x2, i8 %x3) { define <8 x double>@test_int_x86_avx512_mask_permvar_df_512(<8 x double> %x0, <8 x i64> %x1, <8 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_permvar_df_512: ; CHECK-LABEL: test_int_x86_avx512_mask_permvar_df_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpermpd %zmm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vpermpd %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vpermpd %zmm1, %zmm0, %zmm3 {%k1} {z} ; CHECK-NEXT: vpermpd %zmm1, %zmm0, %zmm3 {%k1} {z}
; CHECK-NEXT: vpermpd %zmm1, %zmm0, %zmm0 ; CHECK-NEXT: vpermpd %zmm1, %zmm0, %zmm0
; CHECK-NEXT: vaddpd %zmm3, %zmm2, %zmm1 ; CHECK-NEXT: vaddpd %zmm3, %zmm2, %zmm1
; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x double> @llvm.x86.avx512.mask.permvar.df.512(<8 x double> %x0, <8 x i64> %x1, <8 x double> %x2, i8 %x3) %res = call <8 x double> @llvm.x86.avx512.mask.permvar.df.512(<8 x double> %x0, <8 x i64> %x1, <8 x double> %x2, i8 %x3)
%res1 = call <8 x double> @llvm.x86.avx512.mask.permvar.df.512(<8 x double> %x0, <8 x i64> %x1, <8 x double> zeroinitializer, i8 %x3) %res1 = call <8 x double> @llvm.x86.avx512.mask.permvar.df.512(<8 x double> %x0, <8 x i64> %x1, <8 x double> zeroinitializer, i8 %x3)
%res2 = call <8 x double> @llvm.x86.avx512.mask.permvar.df.512(<8 x double> %x0, <8 x i64> %x1, <8 x double> %x2, i8 -1) %res2 = call <8 x double> @llvm.x86.avx512.mask.permvar.df.512(<8 x double> %x0, <8 x i64> %x1, <8 x double> %x2, i8 -1)
%res3 = fadd <8 x double> %res, %res1 %res3 = fadd <8 x double> %res, %res1
%res4 = fadd <8 x double> %res3, %res2 %res4 = fadd <8 x double> %res3, %res2
ret <8 x double> %res4 ret <8 x double> %res4
} }
declare <8 x i64> @llvm.x86.avx512.mask.permvar.di.512(<8 x i64>, <8 x i64>, <8 x i64>, i8) declare <8 x i64> @llvm.x86.avx512.mask.permvar.di.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
define <8 x i64>@test_int_x86_avx512_mask_permvar_di_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) { define <8 x i64>@test_int_x86_avx512_mask_permvar_di_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_permvar_di_512: ; CHECK-LABEL: test_int_x86_avx512_mask_permvar_di_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpermq %zmm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vpermq %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vpermq %zmm1, %zmm0, %zmm3 {%k1} {z} ; CHECK-NEXT: vpermq %zmm1, %zmm0, %zmm3 {%k1} {z}
; CHECK-NEXT: vpermq %zmm1, %zmm0, %zmm0 ; CHECK-NEXT: vpermq %zmm1, %zmm0, %zmm0
; CHECK-NEXT: vpaddq %zmm3, %zmm2, %zmm1 ; CHECK-NEXT: vpaddq %zmm3, %zmm2, %zmm1
; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.mask.permvar.di.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) %res = call <8 x i64> @llvm.x86.avx512.mask.permvar.di.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3)
%res1 = call <8 x i64> @llvm.x86.avx512.mask.permvar.di.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> zeroinitializer, i8 %x3) %res1 = call <8 x i64> @llvm.x86.avx512.mask.permvar.di.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> zeroinitializer, i8 %x3)
%res2 = call <8 x i64> @llvm.x86.avx512.mask.permvar.di.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1) %res2 = call <8 x i64> @llvm.x86.avx512.mask.permvar.di.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1)
%res3 = add <8 x i64> %res, %res1 %res3 = add <8 x i64> %res, %res1
%res4 = add <8 x i64> %res3, %res2 %res4 = add <8 x i64> %res3, %res2
ret <8 x i64> %res4 ret <8 x i64> %res4
} }
declare <16 x float> @llvm.x86.avx512.mask.permvar.sf.512(<16 x float>, <16 x i32>, <16 x float>, i16) declare <16 x float> @llvm.x86.avx512.mask.permvar.sf.512(<16 x float>, <16 x i32>, <16 x float>, i16)
define <16 x float>@test_int_x86_avx512_mask_permvar_sf_512(<16 x float> %x0, <16 x i32> %x1, <16 x float> %x2, i16 %x3) { define <16 x float>@test_int_x86_avx512_mask_permvar_sf_512(<16 x float> %x0, <16 x i32> %x1, <16 x float> %x2, i16 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_permvar_sf_512: ; CHECK-LABEL: test_int_x86_avx512_mask_permvar_sf_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vpermps %zmm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vpermps %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vpermps %zmm1, %zmm0, %zmm3 {%k1} {z} ; CHECK-NEXT: vpermps %zmm1, %zmm0, %zmm3 {%k1} {z}
; CHECK-NEXT: vpermps %zmm1, %zmm0, %zmm0 ; CHECK-NEXT: vpermps %zmm1, %zmm0, %zmm0
; CHECK-NEXT: vaddps %zmm3, %zmm2, %zmm1 ; CHECK-NEXT: vaddps %zmm3, %zmm2, %zmm1
; CHECK-NEXT: vaddps %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vaddps %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <16 x float> @llvm.x86.avx512.mask.permvar.sf.512(<16 x float> %x0, <16 x i32> %x1, <16 x float> %x2, i16 %x3) %res = call <16 x float> @llvm.x86.avx512.mask.permvar.sf.512(<16 x float> %x0, <16 x i32> %x1, <16 x float> %x2, i16 %x3)
%res1 = call <16 x float> @llvm.x86.avx512.mask.permvar.sf.512(<16 x float> %x0, <16 x i32> %x1, <16 x float> zeroinitializer, i16 %x3) %res1 = call <16 x float> @llvm.x86.avx512.mask.permvar.sf.512(<16 x float> %x0, <16 x i32> %x1, <16 x float> zeroinitializer, i16 %x3)
%res2 = call <16 x float> @llvm.x86.avx512.mask.permvar.sf.512(<16 x float> %x0, <16 x i32> %x1, <16 x float> %x2, i16 -1) %res2 = call <16 x float> @llvm.x86.avx512.mask.permvar.sf.512(<16 x float> %x0, <16 x i32> %x1, <16 x float> %x2, i16 -1)
%res3 = fadd <16 x float> %res, %res1 %res3 = fadd <16 x float> %res, %res1
%res4 = fadd <16 x float> %res3, %res2 %res4 = fadd <16 x float> %res3, %res2
ret <16 x float> %res4 ret <16 x float> %res4
} }
declare <16 x i32> @llvm.x86.avx512.mask.permvar.si.512(<16 x i32>, <16 x i32>, <16 x i32>, i8) declare <16 x i32> @llvm.x86.avx512.mask.permvar.si.512(<16 x i32>, <16 x i32>, <16 x i32>, i8)
define <16 x i32>@test_int_x86_avx512_mask_permvar_si_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i8 %x3) { define <16 x i32>@test_int_x86_avx512_mask_permvar_si_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_permvar_si_512: ; CHECK-LABEL: test_int_x86_avx512_mask_permvar_si_512:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: vpermd %zmm1, %zmm0, %zmm2 {%k1} ; CHECK-NEXT: vpermd %zmm1, %zmm0, %zmm2 {%k1}
; CHECK-NEXT: vpermd %zmm1, %zmm0, %zmm3 {%k1} {z} ; CHECK-NEXT: vpermd %zmm1, %zmm0, %zmm3 {%k1} {z}
; CHECK-NEXT: vpermd %zmm1, %zmm0, %zmm0 ; CHECK-NEXT: vpermd %zmm1, %zmm0, %zmm0
; CHECK-NEXT: vpaddd %zmm3, %zmm2, %zmm1 ; CHECK-NEXT: vpaddd %zmm3, %zmm2, %zmm1
; CHECK-NEXT: vpaddd %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vpaddd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <16 x i32> @llvm.x86.avx512.mask.permvar.si.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i8 %x3) %res = call <16 x i32> @llvm.x86.avx512.mask.permvar.si.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i8 %x3)
%res1 = call <16 x i32> @llvm.x86.avx512.mask.permvar.si.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> zeroinitializer, i8 %x3) %res1 = call <16 x i32> @llvm.x86.avx512.mask.permvar.si.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> zeroinitializer, i8 %x3)
%res2 = call <16 x i32> @llvm.x86.avx512.mask.permvar.si.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i8 -1) %res2 = call <16 x i32> @llvm.x86.avx512.mask.permvar.si.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i8 -1)
%res3 = add <16 x i32> %res, %res1 %res3 = add <16 x i32> %res, %res1
%res4 = add <16 x i32> %res3, %res2 %res4 = add <16 x i32> %res3, %res2
ret <16 x i32> %res4 ret <16 x i32> %res4
} }

llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll

Show All 12 Lines; CHECK-NEXT: retq
%m1 = xor <16 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1> %m1 = xor <16 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>
%ret = bitcast <16 x i1> %m1 to i16 %ret = bitcast <16 x i1> %m1 to i16
ret i16 %ret ret i16 %ret
} }
define i8 @mask8(i8 %x) { define i8 @mask8(i8 %x) {
; KNL-LABEL: mask8: ; KNL-LABEL: mask8:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: movzbl %dil, %eax ; KNL-NEXT: kmovw %edi, %k0
; KNL-NEXT: kmovw %eax, %k0
; KNL-NEXT: knotw %k0, %k0 ; KNL-NEXT: knotw %k0, %k0
; KNL-NEXT: kmovw %k0, %eax ; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: mask8: ; SKX-LABEL: mask8:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: kmovb %edi, %k0 ; SKX-NEXT: kmovb %edi, %k0
; SKX-NEXT: knotb %k0, %k0 ; SKX-NEXT: knotb %k0, %k0
▲ Show 20 Lines • Show All 196 Lines • ▼ Show 20 Lines
} }
define void @test7(<8 x i1> %mask) { define void @test7(<8 x i1> %mask) {
; KNL-LABEL: test7: ; KNL-LABEL: test7:
; KNL: ## BB#0: ## %allocas ; KNL: ## BB#0: ## %allocas
; KNL-NEXT: vpmovsxwq %xmm0, %zmm0 ; KNL-NEXT: vpmovsxwq %xmm0, %zmm0
; KNL-NEXT: vpsllq $63, %zmm0, %zmm0 ; KNL-NEXT: vpsllq $63, %zmm0, %zmm0
; KNL-NEXT: vptestmq %zmm0, %zmm0, %k0 ; KNL-NEXT: vptestmq %zmm0, %zmm0, %k0
; KNL-NEXT: movb $85, %al ; KNL-NEXT: movb $85, %al
; KNL-NEXT: movzbl %al, %eax
; KNL-NEXT: kmovw %eax, %k1 ; KNL-NEXT: kmovw %eax, %k1
; KNL-NEXT: korw %k1, %k0, %k0 ; KNL-NEXT: korw %k1, %k0, %k0
; KNL-NEXT: kmovw %k0, %eax ; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: testb %al, %al ; KNL-NEXT: testb %al, %al
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test7: ; SKX-LABEL: test7:
; SKX: ## BB#0: ## %allocas ; SKX: ## BB#0: ## %allocas
▲ Show 20 Lines • Show All 1,088 Lines • ▼ Show 20 Lines; SKX-NEXT: retq
%c = insertelement <64 x i1>%a, i1 %b, i32 5 %c = insertelement <64 x i1>%a, i1 %b, i32 5
%d = sext <64 x i1>%c to <64 x i8> %d = sext <64 x i1>%c to <64 x i8>
ret <64 x i8>%d ret <64 x i8>%d
} }
define <8 x i1> @test18(i8 %a, i16 %y) { define <8 x i1> @test18(i8 %a, i16 %y) {
; KNL-LABEL: test18: ; KNL-LABEL: test18:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: movzbl %dil, %eax ; KNL-NEXT: kmovw %edi, %k0
; KNL-NEXT: kmovw %eax, %k0
; KNL-NEXT: kmovw %esi, %k1 ; KNL-NEXT: kmovw %esi, %k1
; KNL-NEXT: kshiftlw $7, %k1, %k2 ; KNL-NEXT: kshiftlw $7, %k1, %k2
; KNL-NEXT: kshiftrw $15, %k2, %k2 ; KNL-NEXT: kshiftrw $15, %k2, %k2
; KNL-NEXT: kshiftlw $6, %k1, %k1 ; KNL-NEXT: kshiftlw $6, %k1, %k1
; KNL-NEXT: kshiftrw $15, %k1, %k1 ; KNL-NEXT: kshiftrw $15, %k1, %k1
; KNL-NEXT: kshiftlw $6, %k1, %k1 ; KNL-NEXT: kshiftlw $6, %k1, %k1
; KNL-NEXT: korw %k1, %k0, %k0 ; KNL-NEXT: korw %k1, %k0, %k0
; KNL-NEXT: kshiftlw $7, %k2, %k1 ; KNL-NEXT: kshiftlw $7, %k2, %k1
▲ Show 20 Lines • Show All 100 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/avx512-select.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
; CHECK-LABEL: select00
; CHECK: vmovaps
; CHECK-NEXT: LBB
define <16 x i32> @select00(i32 %a, <16 x i32> %b) nounwind { define <16 x i32> @select00(i32 %a, <16 x i32> %b) nounwind {
; CHECK-LABEL: select00:
; CHECK: ## BB#0:
; CHECK-NEXT: vpxord %zmm1, %zmm1, %zmm1
; CHECK-NEXT: cmpl $255, %edi
; CHECK-NEXT: je LBB0_2
; CHECK-NEXT: ## BB#1:
; CHECK-NEXT: vmovaps %zmm0, %zmm1
; CHECK-NEXT: LBB0_2:
; CHECK-NEXT: vpxord %zmm1, %zmm0, %zmm0
; CHECK-NEXT: retq
%cmpres = icmp eq i32 %a, 255 %cmpres = icmp eq i32 %a, 255
%selres = select i1 %cmpres, <16 x i32> zeroinitializer, <16 x i32> %b %selres = select i1 %cmpres, <16 x i32> zeroinitializer, <16 x i32> %b
%res = xor <16 x i32> %b, %selres %res = xor <16 x i32> %b, %selres
ret <16 x i32> %res ret <16 x i32> %res
} }
; CHECK-LABEL: select01
; CHECK: vmovaps
; CHECK-NEXT: LBB
define <8 x i64> @select01(i32 %a, <8 x i64> %b) nounwind { define <8 x i64> @select01(i32 %a, <8 x i64> %b) nounwind {
; CHECK-LABEL: select01:
; CHECK: ## BB#0:
; CHECK-NEXT: vpxord %zmm1, %zmm1, %zmm1
; CHECK-NEXT: cmpl $255, %edi
; CHECK-NEXT: je LBB1_2
; CHECK-NEXT: ## BB#1:
; CHECK-NEXT: vmovaps %zmm0, %zmm1
; CHECK-NEXT: LBB1_2:
; CHECK-NEXT: vpxorq %zmm1, %zmm0, %zmm0
; CHECK-NEXT: retq
%cmpres = icmp eq i32 %a, 255 %cmpres = icmp eq i32 %a, 255
%selres = select i1 %cmpres, <8 x i64> zeroinitializer, <8 x i64> %b %selres = select i1 %cmpres, <8 x i64> zeroinitializer, <8 x i64> %b
%res = xor <8 x i64> %b, %selres %res = xor <8 x i64> %b, %selres
ret <8 x i64> %res ret <8 x i64> %res
} }
; CHECK-LABEL: @select02
; CHECK: cmpless %xmm0, %xmm3, %k1
; CHECK-NEXT: vmovss %xmm2, {{.*}}%xmm1 {%k1}
; CHECK: ret
define float @select02(float %a, float %b, float %c, float %eps) { define float @select02(float %a, float %b, float %c, float %eps) {
; CHECK-LABEL: select02:
; CHECK: ## BB#0:
; CHECK-NEXT: vcmpless %xmm0, %xmm3, %k1
; CHECK-NEXT: vmovss %xmm2, %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vmovaps %zmm1, %zmm0
; CHECK-NEXT: retq
%cmp = fcmp oge float %a, %eps %cmp = fcmp oge float %a, %eps
%cond = select i1 %cmp, float %c, float %b %cond = select i1 %cmp, float %c, float %b
ret float %cond ret float %cond
} }
; CHECK-LABEL: @select03
; CHECK: cmplesd %xmm0, %xmm3, %k1
; CHECK-NEXT: vmovsd %xmm2, {{.*}}%xmm1 {%k1}
; CHECK: ret
define double @select03(double %a, double %b, double %c, double %eps) { define double @select03(double %a, double %b, double %c, double %eps) {
; CHECK-LABEL: select03:
; CHECK: ## BB#0:
; CHECK-NEXT: vcmplesd %xmm0, %xmm3, %k1
; CHECK-NEXT: vmovsd %xmm2, %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vmovaps %zmm1, %zmm0
; CHECK-NEXT: retq
%cmp = fcmp oge double %a, %eps %cmp = fcmp oge double %a, %eps
%cond = select i1 %cmp, double %c, double %b %cond = select i1 %cmp, double %c, double %b
ret double %cond ret double %cond
} }
; CHECK-LABEL: @select04
; CHECK: vmovaps %zmm3, %zmm1
; CHECK-NEXT: ret
; PR20677
define <16 x double> @select04(<16 x double> %a, <16 x double> %b) { define <16 x double> @select04(<16 x double> %a, <16 x double> %b) {
; CHECK-LABEL: select04:
; CHECK: ## BB#0:
; CHECK-NEXT: vmovaps %zmm3, %zmm1
; CHECK-NEXT: retq
%sel = select <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <16 x double> %a, <16 x double> %b %sel = select <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <16 x double> %a, <16 x double> %b
ret <16 x double> %sel ret <16 x double> %sel
} }
; CHECK-LABEL: select05 define i8 @select05(i8 %a.0, i8 %m) {
; CHECK: movzbl %sil, %eax ; CHECK-LABEL: select05:
; CHECK: kmovw %eax, %k0 ; CHECK: ## BB#0:
; CHECK: movzbl %dil, %eax ; CHECK-NEXT: kmovw %esi, %k0
; CHECK: kmovw %eax, %k1 ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: korw %k1, %k0, %k0 ; CHECK-NEXT: korw %k1, %k0, %k0
; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: kmovw %k0, %eax
define i8 @select05(i8 %a.0, i8 %m) { ; CHECK-NEXT: retq
%mask = bitcast i8 %m to <8 x i1> %mask = bitcast i8 %m to <8 x i1>
%a = bitcast i8 %a.0 to <8 x i1> %a = bitcast i8 %a.0 to <8 x i1>
%r = select <8 x i1> %mask, <8 x i1> <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>, <8 x i1> %a %r = select <8 x i1> %mask, <8 x i1> <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>, <8 x i1> %a
%res = bitcast <8 x i1> %r to i8 %res = bitcast <8 x i1> %r to i8
ret i8 %res; ret i8 %res;
} }
; CHECK-LABEL: select06 define i8 @select06(i8 %a.0, i8 %m) {
; CHECK: movzbl %sil, %eax ; CHECK-LABEL: select06:
; CHECK: kmovw %eax, %k0 ; CHECK: ## BB#0:
; CHECK: movzbl %dil, %eax ; CHECK-NEXT: kmovw %esi, %k0
; CHECK: kmovw %eax, %k1 ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kandw %k1, %k0, %k0 ; CHECK-NEXT: kandw %k1, %k0, %k0
; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: kmovw %k0, %eax
define i8 @select06(i8 %a.0, i8 %m) { ; CHECK-NEXT: retq
%mask = bitcast i8 %m to <8 x i1> %mask = bitcast i8 %m to <8 x i1>
%a = bitcast i8 %a.0 to <8 x i1> %a = bitcast i8 %a.0 to <8 x i1>
%r = select <8 x i1> %mask, <8 x i1> %a, <8 x i1> zeroinitializer %r = select <8 x i1> %mask, <8 x i1> %a, <8 x i1> zeroinitializer
%res = bitcast <8 x i1> %r to i8 %res = bitcast <8 x i1> %r to i8
ret i8 %res; ret i8 %res;
} }
; CHECK-LABEL: select07 define i8 @select07(i8 %a.0, i8 %b.0, i8 %m) {
; CHECK-DAG: movzbl %dl, %eax ; CHECK-LABEL: select07:
; CHECK-DAG: kmovw %eax, %k0 ; CHECK: ## BB#0:
; CHECK-DAG: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edx, %k0
; CHECK-DAG: kmovw %eax, %k1 ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-DAG: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k2
; CHECK-DAG: kmovw %eax, %k2 ; CHECK-NEXT: kandw %k0, %k1, %k1
; CHECK: kandw %k0, %k1, %k1
; CHECK-NEXT: knotw %k0, %k0 ; CHECK-NEXT: knotw %k0, %k0
; CHECK-NEXT: kandw %k0, %k2, %k0 ; CHECK-NEXT: kandw %k0, %k2, %k0
; CHECK-NEXT: korw %k0, %k1, %k0 ; CHECK-NEXT: korw %k0, %k1, %k0
; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: kmovw %k0, %eax
define i8 @select07(i8 %a.0, i8 %b.0, i8 %m) { ; CHECK-NEXT: retq
%mask = bitcast i8 %m to <8 x i1> %mask = bitcast i8 %m to <8 x i1>
%a = bitcast i8 %a.0 to <8 x i1> %a = bitcast i8 %a.0 to <8 x i1>
%b = bitcast i8 %b.0 to <8 x i1> %b = bitcast i8 %b.0 to <8 x i1>
%r = select <8 x i1> %mask, <8 x i1> %a, <8 x i1> %b %r = select <8 x i1> %mask, <8 x i1> %a, <8 x i1> %b
%res = bitcast <8 x i1> %r to i8 %res = bitcast <8 x i1> %r to i8
ret i8 %res; ret i8 %res;
} }

llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll

Show First 20 Lines • Show All 645 Lines • ▼ Show 20 Lines
; CHECK: vfmadd213pd %xmm2, %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x09,0xa8,0xc2] ; CHECK: vfmadd213pd %xmm2, %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x09,0xa8,0xc2]
%res = call <2 x double> @llvm.x86.avx512.mask.vfmadd.pd.128(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) %res = call <2 x double> @llvm.x86.avx512.mask.vfmadd.pd.128(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask)
ret <2 x double> %res ret <2 x double> %res
} }
define <2 x double>@test_int_x86_avx512_mask_vfmadd_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) { define <2 x double>@test_int_x86_avx512_mask_vfmadd_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vfmadd_pd_128: ; CHECK-LABEL: test_int_x86_avx512_mask_vfmadd_pd_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfmadd213pd %xmm2, %xmm1, %xmm3 {%k1} ; CHECK-NEXT: vfmadd213pd %xmm2, %xmm1, %xmm3 {%k1}
; CHECK-NEXT: vfmadd213pd %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vfmadd213pd %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.vfmadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) %res = call <2 x double> @llvm.x86.avx512.mask.vfmadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3)
%res1 = call <2 x double> @llvm.x86.avx512.mask.vfmadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1) %res1 = call <2 x double> @llvm.x86.avx512.mask.vfmadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1)
%res2 = fadd <2 x double> %res, %res1 %res2 = fadd <2 x double> %res, %res1
ret <2 x double> %res2 ret <2 x double> %res2
} }
declare <2 x double> @llvm.x86.avx512.mask3.vfmadd.pd.128(<2 x double>, <2 x double>, <2 x double>, i8) declare <2 x double> @llvm.x86.avx512.mask3.vfmadd.pd.128(<2 x double>, <2 x double>, <2 x double>, i8)
define <2 x double>@test_int_x86_avx512_mask3_vfmadd_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) { define <2 x double>@test_int_x86_avx512_mask3_vfmadd_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask3_vfmadd_pd_128: ; CHECK-LABEL: test_int_x86_avx512_mask3_vfmadd_pd_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm2, %zmm3 ; CHECK-NEXT: vmovaps %zmm2, %zmm3
; CHECK-NEXT: vfmadd231pd %xmm1, %xmm0, %xmm3 {%k1} ; CHECK-NEXT: vfmadd231pd %xmm1, %xmm0, %xmm3 {%k1}
; CHECK-NEXT: vfmadd213pd %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vfmadd213pd %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask3.vfmadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) %res = call <2 x double> @llvm.x86.avx512.mask3.vfmadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3)
%res1 = call <2 x double> @llvm.x86.avx512.mask3.vfmadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1) %res1 = call <2 x double> @llvm.x86.avx512.mask3.vfmadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1)
%res2 = fadd <2 x double> %res, %res1 %res2 = fadd <2 x double> %res, %res1
ret <2 x double> %res2 ret <2 x double> %res2
} }
declare <2 x double> @llvm.x86.avx512.maskz.vfmadd.pd.128(<2 x double>, <2 x double>, <2 x double>, i8) declare <2 x double> @llvm.x86.avx512.maskz.vfmadd.pd.128(<2 x double>, <2 x double>, <2 x double>, i8)
define <2 x double>@test_int_x86_avx512_maskz_vfmadd_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) { define <2 x double>@test_int_x86_avx512_maskz_vfmadd_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_maskz_vfmadd_pd_128: ; CHECK-LABEL: test_int_x86_avx512_maskz_vfmadd_pd_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfmadd213pd %xmm2, %xmm1, %xmm3 {%k1} {z} ; CHECK-NEXT: vfmadd213pd %xmm2, %xmm1, %xmm3 {%k1} {z}
; CHECK-NEXT: vfmadd213pd %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vfmadd213pd %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.maskz.vfmadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) %res = call <2 x double> @llvm.x86.avx512.maskz.vfmadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3)
%res1 = call <2 x double> @llvm.x86.avx512.maskz.vfmadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1) %res1 = call <2 x double> @llvm.x86.avx512.maskz.vfmadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1)
%res2 = fadd <2 x double> %res, %res1 %res2 = fadd <2 x double> %res, %res1
ret <2 x double> %res2 ret <2 x double> %res2
} }
define <4 x double>@test_int_x86_avx512_mask_vfmadd_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) { define <4 x double>@test_int_x86_avx512_mask_vfmadd_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vfmadd_pd_256: ; CHECK-LABEL: test_int_x86_avx512_mask_vfmadd_pd_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfmadd213pd %ymm2, %ymm1, %ymm3 {%k1} ; CHECK-NEXT: vfmadd213pd %ymm2, %ymm1, %ymm3 {%k1}
; CHECK-NEXT: vfmadd213pd %ymm2, %ymm1, %ymm0 ; CHECK-NEXT: vfmadd213pd %ymm2, %ymm1, %ymm0
; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x double> @llvm.x86.avx512.mask.vfmadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) %res = call <4 x double> @llvm.x86.avx512.mask.vfmadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3)
%res1 = call <4 x double> @llvm.x86.avx512.mask.vfmadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1) %res1 = call <4 x double> @llvm.x86.avx512.mask.vfmadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1)
%res2 = fadd <4 x double> %res, %res1 %res2 = fadd <4 x double> %res, %res1
ret <4 x double> %res2 ret <4 x double> %res2
} }
declare <4 x double> @llvm.x86.avx512.mask3.vfmadd.pd.256(<4 x double>, <4 x double>, <4 x double>, i8) declare <4 x double> @llvm.x86.avx512.mask3.vfmadd.pd.256(<4 x double>, <4 x double>, <4 x double>, i8)
define <4 x double>@test_int_x86_avx512_mask3_vfmadd_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) { define <4 x double>@test_int_x86_avx512_mask3_vfmadd_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask3_vfmadd_pd_256: ; CHECK-LABEL: test_int_x86_avx512_mask3_vfmadd_pd_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm2, %zmm3 ; CHECK-NEXT: vmovaps %zmm2, %zmm3
; CHECK-NEXT: vfmadd231pd %ymm1, %ymm0, %ymm3 {%k1} ; CHECK-NEXT: vfmadd231pd %ymm1, %ymm0, %ymm3 {%k1}
; CHECK-NEXT: vfmadd213pd %ymm2, %ymm1, %ymm0 ; CHECK-NEXT: vfmadd213pd %ymm2, %ymm1, %ymm0
; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x double> @llvm.x86.avx512.mask3.vfmadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) %res = call <4 x double> @llvm.x86.avx512.mask3.vfmadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3)
%res1 = call <4 x double> @llvm.x86.avx512.mask3.vfmadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1) %res1 = call <4 x double> @llvm.x86.avx512.mask3.vfmadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1)
%res2 = fadd <4 x double> %res, %res1 %res2 = fadd <4 x double> %res, %res1
ret <4 x double> %res2 ret <4 x double> %res2
} }
declare <4 x double> @llvm.x86.avx512.maskz.vfmadd.pd.256(<4 x double>, <4 x double>, <4 x double>, i8) declare <4 x double> @llvm.x86.avx512.maskz.vfmadd.pd.256(<4 x double>, <4 x double>, <4 x double>, i8)
define <4 x double>@test_int_x86_avx512_maskz_vfmadd_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) { define <4 x double>@test_int_x86_avx512_maskz_vfmadd_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_maskz_vfmadd_pd_256: ; CHECK-LABEL: test_int_x86_avx512_maskz_vfmadd_pd_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfmadd213pd %ymm2, %ymm1, %ymm3 {%k1} {z} ; CHECK-NEXT: vfmadd213pd %ymm2, %ymm1, %ymm3 {%k1} {z}
; CHECK-NEXT: vfmadd213pd %ymm2, %ymm1, %ymm0 ; CHECK-NEXT: vfmadd213pd %ymm2, %ymm1, %ymm0
; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x double> @llvm.x86.avx512.maskz.vfmadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) %res = call <4 x double> @llvm.x86.avx512.maskz.vfmadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3)
%res1 = call <4 x double> @llvm.x86.avx512.maskz.vfmadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1) %res1 = call <4 x double> @llvm.x86.avx512.maskz.vfmadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1)
%res2 = fadd <4 x double> %res, %res1 %res2 = fadd <4 x double> %res, %res1
ret <4 x double> %res2 ret <4 x double> %res2
} }
define <4 x float>@test_int_x86_avx512_mask_vfmadd_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) { define <4 x float>@test_int_x86_avx512_mask_vfmadd_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vfmadd_ps_128: ; CHECK-LABEL: test_int_x86_avx512_mask_vfmadd_ps_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfmadd213ps %xmm2, %xmm1, %xmm3 {%k1} ; CHECK-NEXT: vfmadd213ps %xmm2, %xmm1, %xmm3 {%k1}
; CHECK-NEXT: vfmadd213ps %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vfmadd213ps %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.vfmadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) %res = call <4 x float> @llvm.x86.avx512.mask.vfmadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3)
%res1 = call <4 x float> @llvm.x86.avx512.mask.vfmadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1) %res1 = call <4 x float> @llvm.x86.avx512.mask.vfmadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1)
%res2 = fadd <4 x float> %res, %res1 %res2 = fadd <4 x float> %res, %res1
ret <4 x float> %res2 ret <4 x float> %res2
} }
declare <4 x float> @llvm.x86.avx512.mask3.vfmadd.ps.128(<4 x float>, <4 x float>, <4 x float>, i8) declare <4 x float> @llvm.x86.avx512.mask3.vfmadd.ps.128(<4 x float>, <4 x float>, <4 x float>, i8)
define <4 x float>@test_int_x86_avx512_mask3_vfmadd_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) { define <4 x float>@test_int_x86_avx512_mask3_vfmadd_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask3_vfmadd_ps_128: ; CHECK-LABEL: test_int_x86_avx512_mask3_vfmadd_ps_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm2, %zmm3 ; CHECK-NEXT: vmovaps %zmm2, %zmm3
; CHECK-NEXT: vfmadd231ps %xmm1, %xmm0, %xmm3 {%k1} ; CHECK-NEXT: vfmadd231ps %xmm1, %xmm0, %xmm3 {%k1}
; CHECK-NEXT: vfmadd213ps %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vfmadd213ps %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask3.vfmadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) %res = call <4 x float> @llvm.x86.avx512.mask3.vfmadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3)
%res1 = call <4 x float> @llvm.x86.avx512.mask3.vfmadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1) %res1 = call <4 x float> @llvm.x86.avx512.mask3.vfmadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1)
%res2 = fadd <4 x float> %res, %res1 %res2 = fadd <4 x float> %res, %res1
ret <4 x float> %res2 ret <4 x float> %res2
} }
declare <4 x float> @llvm.x86.avx512.maskz.vfmadd.ps.128(<4 x float>, <4 x float>, <4 x float>, i8) declare <4 x float> @llvm.x86.avx512.maskz.vfmadd.ps.128(<4 x float>, <4 x float>, <4 x float>, i8)
define <4 x float>@test_int_x86_avx512_maskz_vfmadd_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) { define <4 x float>@test_int_x86_avx512_maskz_vfmadd_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_maskz_vfmadd_ps_128: ; CHECK-LABEL: test_int_x86_avx512_maskz_vfmadd_ps_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfmadd213ps %xmm2, %xmm1, %xmm3 {%k1} {z} ; CHECK-NEXT: vfmadd213ps %xmm2, %xmm1, %xmm3 {%k1} {z}
; CHECK-NEXT: vfmadd213ps %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vfmadd213ps %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.maskz.vfmadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) %res = call <4 x float> @llvm.x86.avx512.maskz.vfmadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3)
%res1 = call <4 x float> @llvm.x86.avx512.maskz.vfmadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1) %res1 = call <4 x float> @llvm.x86.avx512.maskz.vfmadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1)
%res2 = fadd <4 x float> %res, %res1 %res2 = fadd <4 x float> %res, %res1
ret <4 x float> %res2 ret <4 x float> %res2
} }
define <8 x float>@test_int_x86_avx512_mask_vfmadd_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) { define <8 x float>@test_int_x86_avx512_mask_vfmadd_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vfmadd_ps_256: ; CHECK-LABEL: test_int_x86_avx512_mask_vfmadd_ps_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfmadd213ps %ymm2, %ymm1, %ymm3 {%k1} ; CHECK-NEXT: vfmadd213ps %ymm2, %ymm1, %ymm3 {%k1}
; CHECK-NEXT: vfmadd213ps %ymm2, %ymm1, %ymm0 ; CHECK-NEXT: vfmadd213ps %ymm2, %ymm1, %ymm0
; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx512.mask.vfmadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) %res = call <8 x float> @llvm.x86.avx512.mask.vfmadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3)
%res1 = call <8 x float> @llvm.x86.avx512.mask.vfmadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1) %res1 = call <8 x float> @llvm.x86.avx512.mask.vfmadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1)
%res2 = fadd <8 x float> %res, %res1 %res2 = fadd <8 x float> %res, %res1
ret <8 x float> %res2 ret <8 x float> %res2
} }
declare <8 x float> @llvm.x86.avx512.mask3.vfmadd.ps.256(<8 x float>, <8 x float>, <8 x float>, i8) declare <8 x float> @llvm.x86.avx512.mask3.vfmadd.ps.256(<8 x float>, <8 x float>, <8 x float>, i8)
define <8 x float>@test_int_x86_avx512_mask3_vfmadd_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) { define <8 x float>@test_int_x86_avx512_mask3_vfmadd_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask3_vfmadd_ps_256: ; CHECK-LABEL: test_int_x86_avx512_mask3_vfmadd_ps_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm2, %zmm3 ; CHECK-NEXT: vmovaps %zmm2, %zmm3
; CHECK-NEXT: vfmadd231ps %ymm1, %ymm0, %ymm3 {%k1} ; CHECK-NEXT: vfmadd231ps %ymm1, %ymm0, %ymm3 {%k1}
; CHECK-NEXT: vfmadd213ps %ymm2, %ymm1, %ymm0 ; CHECK-NEXT: vfmadd213ps %ymm2, %ymm1, %ymm0
; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx512.mask3.vfmadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) %res = call <8 x float> @llvm.x86.avx512.mask3.vfmadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3)
%res1 = call <8 x float> @llvm.x86.avx512.mask3.vfmadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1) %res1 = call <8 x float> @llvm.x86.avx512.mask3.vfmadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1)
%res2 = fadd <8 x float> %res, %res1 %res2 = fadd <8 x float> %res, %res1
ret <8 x float> %res2 ret <8 x float> %res2
} }
declare <8 x float> @llvm.x86.avx512.maskz.vfmadd.ps.256(<8 x float>, <8 x float>, <8 x float>, i8) declare <8 x float> @llvm.x86.avx512.maskz.vfmadd.ps.256(<8 x float>, <8 x float>, <8 x float>, i8)
define <8 x float>@test_int_x86_avx512_maskz_vfmadd_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) { define <8 x float>@test_int_x86_avx512_maskz_vfmadd_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_maskz_vfmadd_ps_256: ; CHECK-LABEL: test_int_x86_avx512_maskz_vfmadd_ps_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfmadd213ps %ymm2, %ymm1, %ymm3 {%k1} {z} ; CHECK-NEXT: vfmadd213ps %ymm2, %ymm1, %ymm3 {%k1} {z}
; CHECK-NEXT: vfmadd213ps %ymm2, %ymm1, %ymm0 ; CHECK-NEXT: vfmadd213ps %ymm2, %ymm1, %ymm0
; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx512.maskz.vfmadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) %res = call <8 x float> @llvm.x86.avx512.maskz.vfmadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3)
%res1 = call <8 x float> @llvm.x86.avx512.maskz.vfmadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1) %res1 = call <8 x float> @llvm.x86.avx512.maskz.vfmadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1)
%res2 = fadd <8 x float> %res, %res1 %res2 = fadd <8 x float> %res, %res1
ret <8 x float> %res2 ret <8 x float> %res2
} }
declare <2 x double> @llvm.x86.avx512.mask3.vfmsub.pd.128(<2 x double>, <2 x double>, <2 x double>, i8) declare <2 x double> @llvm.x86.avx512.mask3.vfmsub.pd.128(<2 x double>, <2 x double>, <2 x double>, i8)
define <2 x double>@test_int_x86_avx512_mask3_vfmsub_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) { define <2 x double>@test_int_x86_avx512_mask3_vfmsub_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsub_pd_128: ; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsub_pd_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm2, %zmm3 ; CHECK-NEXT: vmovaps %zmm2, %zmm3
; CHECK-NEXT: vfmsub231pd %xmm1, %xmm0, %xmm3 {%k1} ; CHECK-NEXT: vfmsub231pd %xmm1, %xmm0, %xmm3 {%k1}
; CHECK-NEXT: vfmsub213pd %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vfmsub213pd %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask3.vfmsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) %res = call <2 x double> @llvm.x86.avx512.mask3.vfmsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3)
%res1 = call <2 x double> @llvm.x86.avx512.mask3.vfmsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1) %res1 = call <2 x double> @llvm.x86.avx512.mask3.vfmsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1)
%res2 = fadd <2 x double> %res, %res1 %res2 = fadd <2 x double> %res, %res1
ret <2 x double> %res2 ret <2 x double> %res2
} }
declare <4 x double> @llvm.x86.avx512.mask3.vfmsub.pd.256(<4 x double>, <4 x double>, <4 x double>, i8) declare <4 x double> @llvm.x86.avx512.mask3.vfmsub.pd.256(<4 x double>, <4 x double>, <4 x double>, i8)
define <4 x double>@test_int_x86_avx512_mask3_vfmsub_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) { define <4 x double>@test_int_x86_avx512_mask3_vfmsub_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsub_pd_256: ; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsub_pd_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm2, %zmm3 ; CHECK-NEXT: vmovaps %zmm2, %zmm3
; CHECK-NEXT: vfmsub231pd %ymm1, %ymm0, %ymm3 {%k1} ; CHECK-NEXT: vfmsub231pd %ymm1, %ymm0, %ymm3 {%k1}
; CHECK-NEXT: vfmsub213pd %ymm2, %ymm1, %ymm0 ; CHECK-NEXT: vfmsub213pd %ymm2, %ymm1, %ymm0
; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x double> @llvm.x86.avx512.mask3.vfmsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) %res = call <4 x double> @llvm.x86.avx512.mask3.vfmsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3)
%res1 = call <4 x double> @llvm.x86.avx512.mask3.vfmsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1) %res1 = call <4 x double> @llvm.x86.avx512.mask3.vfmsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1)
%res2 = fadd <4 x double> %res, %res1 %res2 = fadd <4 x double> %res, %res1
ret <4 x double> %res2 ret <4 x double> %res2
} }
declare <4 x float> @llvm.x86.avx512.mask3.vfmsub.ps.128(<4 x float>, <4 x float>, <4 x float>, i8) declare <4 x float> @llvm.x86.avx512.mask3.vfmsub.ps.128(<4 x float>, <4 x float>, <4 x float>, i8)
define <4 x float>@test_int_x86_avx512_mask3_vfmsub_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) { define <4 x float>@test_int_x86_avx512_mask3_vfmsub_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsub_ps_128: ; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsub_ps_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm2, %zmm3 ; CHECK-NEXT: vmovaps %zmm2, %zmm3
; CHECK-NEXT: vfmsub231ps %xmm1, %xmm0, %xmm3 {%k1} ; CHECK-NEXT: vfmsub231ps %xmm1, %xmm0, %xmm3 {%k1}
; CHECK-NEXT: vfmsub213ps %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vfmsub213ps %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask3.vfmsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) %res = call <4 x float> @llvm.x86.avx512.mask3.vfmsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3)
%res1 = call <4 x float> @llvm.x86.avx512.mask3.vfmsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1) %res1 = call <4 x float> @llvm.x86.avx512.mask3.vfmsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1)
%res2 = fadd <4 x float> %res, %res1 %res2 = fadd <4 x float> %res, %res1
ret <4 x float> %res2 ret <4 x float> %res2
} }
declare <8 x float> @llvm.x86.avx512.mask3.vfmsub.ps.256(<8 x float>, <8 x float>, <8 x float>, i8) declare <8 x float> @llvm.x86.avx512.mask3.vfmsub.ps.256(<8 x float>, <8 x float>, <8 x float>, i8)
define <8 x float>@test_int_x86_avx512_mask3_vfmsub_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) { define <8 x float>@test_int_x86_avx512_mask3_vfmsub_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsub_ps_256: ; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsub_ps_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm2, %zmm3 ; CHECK-NEXT: vmovaps %zmm2, %zmm3
; CHECK-NEXT: vfmsub231ps %ymm1, %ymm0, %ymm3 {%k1} ; CHECK-NEXT: vfmsub231ps %ymm1, %ymm0, %ymm3 {%k1}
; CHECK-NEXT: vfmsub213ps %ymm2, %ymm1, %ymm0 ; CHECK-NEXT: vfmsub213ps %ymm2, %ymm1, %ymm0
; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx512.mask3.vfmsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) %res = call <8 x float> @llvm.x86.avx512.mask3.vfmsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3)
%res1 = call <8 x float> @llvm.x86.avx512.mask3.vfmsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1) %res1 = call <8 x float> @llvm.x86.avx512.mask3.vfmsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1)
%res2 = fadd <8 x float> %res, %res1 %res2 = fadd <8 x float> %res, %res1
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Linesdefine <2 x double> @test_mask_vfnmsub128_pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {
%res = call <2 x double> @llvm.x86.avx512.mask.vfnmsub.pd.128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) nounwind %res = call <2 x double> @llvm.x86.avx512.mask.vfnmsub.pd.128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) nounwind
ret <2 x double> %res ret <2 x double> %res
} }
define <2 x double>@test_int_x86_avx512_mask_vfnmsub_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) { define <2 x double>@test_int_x86_avx512_mask_vfnmsub_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vfnmsub_pd_128: ; CHECK-LABEL: test_int_x86_avx512_mask_vfnmsub_pd_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfnmsub213pd %xmm2, %xmm1, %xmm3 {%k1} ; CHECK-NEXT: vfnmsub213pd %xmm2, %xmm1, %xmm3 {%k1}
; CHECK-NEXT: vfnmsub213pd %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vfnmsub213pd %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.vfnmsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) %res = call <2 x double> @llvm.x86.avx512.mask.vfnmsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3)
%res1 = call <2 x double> @llvm.x86.avx512.mask.vfnmsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1) %res1 = call <2 x double> @llvm.x86.avx512.mask.vfnmsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1)
%res2 = fadd <2 x double> %res, %res1 %res2 = fadd <2 x double> %res, %res1
ret <2 x double> %res2 ret <2 x double> %res2
} }
declare <2 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.128(<2 x double>, <2 x double>, <2 x double>, i8) declare <2 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.128(<2 x double>, <2 x double>, <2 x double>, i8)
define <2 x double>@test_int_x86_avx512_mask3_vfnmsub_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) { define <2 x double>@test_int_x86_avx512_mask3_vfnmsub_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask3_vfnmsub_pd_128: ; CHECK-LABEL: test_int_x86_avx512_mask3_vfnmsub_pd_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm2, %zmm3 ; CHECK-NEXT: vmovaps %zmm2, %zmm3
; CHECK-NEXT: vfnmsub231pd %xmm1, %xmm0, %xmm3 {%k1} ; CHECK-NEXT: vfnmsub231pd %xmm1, %xmm0, %xmm3 {%k1}
; CHECK-NEXT: vfnmsub213pd %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vfnmsub213pd %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) %res = call <2 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3)
%res1 = call <2 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1) %res1 = call <2 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1)
%res2 = fadd <2 x double> %res, %res1 %res2 = fadd <2 x double> %res, %res1
ret <2 x double> %res2 ret <2 x double> %res2
} }
define <4 x double>@test_int_x86_avx512_mask_vfnmsub_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) { define <4 x double>@test_int_x86_avx512_mask_vfnmsub_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vfnmsub_pd_256: ; CHECK-LABEL: test_int_x86_avx512_mask_vfnmsub_pd_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfnmsub213pd %ymm2, %ymm1, %ymm3 {%k1} ; CHECK-NEXT: vfnmsub213pd %ymm2, %ymm1, %ymm3 {%k1}
; CHECK-NEXT: vfnmsub213pd %ymm2, %ymm1, %ymm0 ; CHECK-NEXT: vfnmsub213pd %ymm2, %ymm1, %ymm0
; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x double> @llvm.x86.avx512.mask.vfnmsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) %res = call <4 x double> @llvm.x86.avx512.mask.vfnmsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3)
%res1 = call <4 x double> @llvm.x86.avx512.mask.vfnmsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1) %res1 = call <4 x double> @llvm.x86.avx512.mask.vfnmsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1)
%res2 = fadd <4 x double> %res, %res1 %res2 = fadd <4 x double> %res, %res1
ret <4 x double> %res2 ret <4 x double> %res2
} }
declare <4 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.256(<4 x double>, <4 x double>, <4 x double>, i8) declare <4 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.256(<4 x double>, <4 x double>, <4 x double>, i8)
define <4 x double>@test_int_x86_avx512_mask3_vfnmsub_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) { define <4 x double>@test_int_x86_avx512_mask3_vfnmsub_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask3_vfnmsub_pd_256: ; CHECK-LABEL: test_int_x86_avx512_mask3_vfnmsub_pd_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm2, %zmm3 ; CHECK-NEXT: vmovaps %zmm2, %zmm3
; CHECK-NEXT: vfnmsub231pd %ymm1, %ymm0, %ymm3 {%k1} ; CHECK-NEXT: vfnmsub231pd %ymm1, %ymm0, %ymm3 {%k1}
; CHECK-NEXT: vfnmsub213pd %ymm2, %ymm1, %ymm0 ; CHECK-NEXT: vfnmsub213pd %ymm2, %ymm1, %ymm0
; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) %res = call <4 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3)
%res1 = call <4 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1) %res1 = call <4 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1)
%res2 = fadd <4 x double> %res, %res1 %res2 = fadd <4 x double> %res, %res1
ret <4 x double> %res2 ret <4 x double> %res2
} }
define <4 x float>@test_int_x86_avx512_mask_vfnmsub_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) { define <4 x float>@test_int_x86_avx512_mask_vfnmsub_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vfnmsub_ps_128: ; CHECK-LABEL: test_int_x86_avx512_mask_vfnmsub_ps_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfnmsub213ps %xmm2, %xmm1, %xmm3 {%k1} ; CHECK-NEXT: vfnmsub213ps %xmm2, %xmm1, %xmm3 {%k1}
; CHECK-NEXT: vfnmsub213ps %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vfnmsub213ps %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.vfnmsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) %res = call <4 x float> @llvm.x86.avx512.mask.vfnmsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3)
%res1 = call <4 x float> @llvm.x86.avx512.mask.vfnmsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1) %res1 = call <4 x float> @llvm.x86.avx512.mask.vfnmsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1)
%res2 = fadd <4 x float> %res, %res1 %res2 = fadd <4 x float> %res, %res1
ret <4 x float> %res2 ret <4 x float> %res2
} }
declare <4 x float> @llvm.x86.avx512.mask3.vfnmsub.ps.128(<4 x float>, <4 x float>, <4 x float>, i8) declare <4 x float> @llvm.x86.avx512.mask3.vfnmsub.ps.128(<4 x float>, <4 x float>, <4 x float>, i8)
define <4 x float>@test_int_x86_avx512_mask3_vfnmsub_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) { define <4 x float>@test_int_x86_avx512_mask3_vfnmsub_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask3_vfnmsub_ps_128: ; CHECK-LABEL: test_int_x86_avx512_mask3_vfnmsub_ps_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm2, %zmm3 ; CHECK-NEXT: vmovaps %zmm2, %zmm3
; CHECK-NEXT: vfnmsub231ps %xmm1, %xmm0, %xmm3 {%k1} ; CHECK-NEXT: vfnmsub231ps %xmm1, %xmm0, %xmm3 {%k1}
; CHECK-NEXT: vfnmsub213ps %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vfnmsub213ps %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask3.vfnmsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) %res = call <4 x float> @llvm.x86.avx512.mask3.vfnmsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3)
%res1 = call <4 x float> @llvm.x86.avx512.mask3.vfnmsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1) %res1 = call <4 x float> @llvm.x86.avx512.mask3.vfnmsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1)
%res2 = fadd <4 x float> %res, %res1 %res2 = fadd <4 x float> %res, %res1
ret <4 x float> %res2 ret <4 x float> %res2
} }
define <8 x float>@test_int_x86_avx512_mask_vfnmsub_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) { define <8 x float>@test_int_x86_avx512_mask_vfnmsub_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vfnmsub_ps_256: ; CHECK-LABEL: test_int_x86_avx512_mask_vfnmsub_ps_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfnmsub213ps %ymm2, %ymm1, %ymm3 {%k1} ; CHECK-NEXT: vfnmsub213ps %ymm2, %ymm1, %ymm3 {%k1}
; CHECK-NEXT: vfnmsub213ps %ymm2, %ymm1, %ymm0 ; CHECK-NEXT: vfnmsub213ps %ymm2, %ymm1, %ymm0
; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx512.mask.vfnmsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) %res = call <8 x float> @llvm.x86.avx512.mask.vfnmsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3)
%res1 = call <8 x float> @llvm.x86.avx512.mask.vfnmsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1) %res1 = call <8 x float> @llvm.x86.avx512.mask.vfnmsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1)
%res2 = fadd <8 x float> %res, %res1 %res2 = fadd <8 x float> %res, %res1
ret <8 x float> %res2 ret <8 x float> %res2
} }
declare <8 x float> @llvm.x86.avx512.mask3.vfnmsub.ps.256(<8 x float>, <8 x float>, <8 x float>, i8) declare <8 x float> @llvm.x86.avx512.mask3.vfnmsub.ps.256(<8 x float>, <8 x float>, <8 x float>, i8)
define <8 x float>@test_int_x86_avx512_mask3_vfnmsub_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) { define <8 x float>@test_int_x86_avx512_mask3_vfnmsub_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask3_vfnmsub_ps_256: ; CHECK-LABEL: test_int_x86_avx512_mask3_vfnmsub_ps_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm2, %zmm3 ; CHECK-NEXT: vmovaps %zmm2, %zmm3
; CHECK-NEXT: vfnmsub231ps %ymm1, %ymm0, %ymm3 {%k1} ; CHECK-NEXT: vfnmsub231ps %ymm1, %ymm0, %ymm3 {%k1}
; CHECK-NEXT: vfnmsub213ps %ymm2, %ymm1, %ymm0 ; CHECK-NEXT: vfnmsub213ps %ymm2, %ymm1, %ymm0
; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx512.mask3.vfnmsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) %res = call <8 x float> @llvm.x86.avx512.mask3.vfnmsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3)
%res1 = call <8 x float> @llvm.x86.avx512.mask3.vfnmsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1) %res1 = call <8 x float> @llvm.x86.avx512.mask3.vfnmsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1)
%res2 = fadd <8 x float> %res, %res1 %res2 = fadd <8 x float> %res, %res1
ret <8 x float> %res2 ret <8 x float> %res2
} }
define <2 x double>@test_int_x86_avx512_mask_vfnmadd_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) { define <2 x double>@test_int_x86_avx512_mask_vfnmadd_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vfnmadd_pd_128: ; CHECK-LABEL: test_int_x86_avx512_mask_vfnmadd_pd_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfnmadd213pd %xmm2, %xmm1, %xmm3 {%k1} ; CHECK-NEXT: vfnmadd213pd %xmm2, %xmm1, %xmm3 {%k1}
; CHECK-NEXT: vfnmadd213pd %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vfnmadd213pd %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.vfnmadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) %res = call <2 x double> @llvm.x86.avx512.mask.vfnmadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3)
%res1 = call <2 x double> @llvm.x86.avx512.mask.vfnmadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1) %res1 = call <2 x double> @llvm.x86.avx512.mask.vfnmadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1)
%res2 = fadd <2 x double> %res, %res1 %res2 = fadd <2 x double> %res, %res1
ret <2 x double> %res2 ret <2 x double> %res2
} }
define <4 x double>@test_int_x86_avx512_mask_vfnmadd_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) { define <4 x double>@test_int_x86_avx512_mask_vfnmadd_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vfnmadd_pd_256: ; CHECK-LABEL: test_int_x86_avx512_mask_vfnmadd_pd_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfnmadd213pd %ymm2, %ymm1, %ymm3 {%k1} ; CHECK-NEXT: vfnmadd213pd %ymm2, %ymm1, %ymm3 {%k1}
; CHECK-NEXT: vfnmadd213pd %ymm2, %ymm1, %ymm0 ; CHECK-NEXT: vfnmadd213pd %ymm2, %ymm1, %ymm0
; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x double> @llvm.x86.avx512.mask.vfnmadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) %res = call <4 x double> @llvm.x86.avx512.mask.vfnmadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3)
%res1 = call <4 x double> @llvm.x86.avx512.mask.vfnmadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1) %res1 = call <4 x double> @llvm.x86.avx512.mask.vfnmadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1)
%res2 = fadd <4 x double> %res, %res1 %res2 = fadd <4 x double> %res, %res1
ret <4 x double> %res2 ret <4 x double> %res2
} }
define <4 x float>@test_int_x86_avx512_mask_vfnmadd_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) { define <4 x float>@test_int_x86_avx512_mask_vfnmadd_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vfnmadd_ps_128: ; CHECK-LABEL: test_int_x86_avx512_mask_vfnmadd_ps_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfnmadd213ps %xmm2, %xmm1, %xmm3 {%k1} ; CHECK-NEXT: vfnmadd213ps %xmm2, %xmm1, %xmm3 {%k1}
; CHECK-NEXT: vfnmadd213ps %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vfnmadd213ps %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.vfnmadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) %res = call <4 x float> @llvm.x86.avx512.mask.vfnmadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3)
%res1 = call <4 x float> @llvm.x86.avx512.mask.vfnmadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1) %res1 = call <4 x float> @llvm.x86.avx512.mask.vfnmadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1)
%res2 = fadd <4 x float> %res, %res1 %res2 = fadd <4 x float> %res, %res1
ret <4 x float> %res2 ret <4 x float> %res2
} }
define <8 x float>@test_int_x86_avx512_mask_vfnmadd_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) { define <8 x float>@test_int_x86_avx512_mask_vfnmadd_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vfnmadd_ps_256: ; CHECK-LABEL: test_int_x86_avx512_mask_vfnmadd_ps_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfnmadd213ps %ymm2, %ymm1, %ymm3 {%k1} ; CHECK-NEXT: vfnmadd213ps %ymm2, %ymm1, %ymm3 {%k1}
; CHECK-NEXT: vfnmadd213ps %ymm2, %ymm1, %ymm0 ; CHECK-NEXT: vfnmadd213ps %ymm2, %ymm1, %ymm0
; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx512.mask.vfnmadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) %res = call <8 x float> @llvm.x86.avx512.mask.vfnmadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3)
%res1 = call <8 x float> @llvm.x86.avx512.mask.vfnmadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1) %res1 = call <8 x float> @llvm.x86.avx512.mask.vfnmadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1)
%res2 = fadd <8 x float> %res, %res1 %res2 = fadd <8 x float> %res, %res1
Show All 34 Linesdefine <2 x double> @test_mask_vfmaddsub128_pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {
; CHECK: vfmaddsub213pd %xmm2, %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x09,0xa6,0xc2] ; CHECK: vfmaddsub213pd %xmm2, %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x09,0xa6,0xc2]
%res = call <2 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) nounwind %res = call <2 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) nounwind
ret <2 x double> %res ret <2 x double> %res
} }
define <2 x double>@test_int_x86_avx512_mask_vfmaddsub_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) { define <2 x double>@test_int_x86_avx512_mask_vfmaddsub_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vfmaddsub_pd_128: ; CHECK-LABEL: test_int_x86_avx512_mask_vfmaddsub_pd_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfmaddsub213pd %xmm2, %xmm1, %xmm3 {%k1} ; CHECK-NEXT: vfmaddsub213pd %xmm2, %xmm1, %xmm3 {%k1}
; CHECK-NEXT: vfmaddsub213pd %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vfmaddsub213pd %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) %res = call <2 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3)
%res1 = call <2 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1) %res1 = call <2 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1)
%res2 = fadd <2 x double> %res, %res1 %res2 = fadd <2 x double> %res, %res1
ret <2 x double> %res2 ret <2 x double> %res2
} }
declare <2 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.128(<2 x double>, <2 x double>, <2 x double>, i8) declare <2 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.128(<2 x double>, <2 x double>, <2 x double>, i8)
define <2 x double>@test_int_x86_avx512_mask3_vfmaddsub_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) { define <2 x double>@test_int_x86_avx512_mask3_vfmaddsub_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask3_vfmaddsub_pd_128: ; CHECK-LABEL: test_int_x86_avx512_mask3_vfmaddsub_pd_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm2, %zmm3 ; CHECK-NEXT: vmovaps %zmm2, %zmm3
; CHECK-NEXT: vfmaddsub231pd %xmm1, %xmm0, %xmm3 {%k1} ; CHECK-NEXT: vfmaddsub231pd %xmm1, %xmm0, %xmm3 {%k1}
; CHECK-NEXT: vfmaddsub213pd %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vfmaddsub213pd %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) %res = call <2 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3)
%res1 = call <2 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1) %res1 = call <2 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1)
%res2 = fadd <2 x double> %res, %res1 %res2 = fadd <2 x double> %res, %res1
ret <2 x double> %res2 ret <2 x double> %res2
} }
declare <2 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.128(<2 x double>, <2 x double>, <2 x double>, i8) declare <2 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.128(<2 x double>, <2 x double>, <2 x double>, i8)
define <2 x double>@test_int_x86_avx512_maskz_vfmaddsub_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) { define <2 x double>@test_int_x86_avx512_maskz_vfmaddsub_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_maskz_vfmaddsub_pd_128: ; CHECK-LABEL: test_int_x86_avx512_maskz_vfmaddsub_pd_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfmaddsub213pd %xmm2, %xmm1, %xmm3 {%k1} {z} ; CHECK-NEXT: vfmaddsub213pd %xmm2, %xmm1, %xmm3 {%k1} {z}
; CHECK-NEXT: vfmaddsub213pd %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vfmaddsub213pd %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) %res = call <2 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3)
%res1 = call <2 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1) %res1 = call <2 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1)
%res2 = fadd <2 x double> %res, %res1 %res2 = fadd <2 x double> %res, %res1
ret <2 x double> %res2 ret <2 x double> %res2
} }
define <4 x double>@test_int_x86_avx512_mask_vfmaddsub_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) { define <4 x double>@test_int_x86_avx512_mask_vfmaddsub_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vfmaddsub_pd_256: ; CHECK-LABEL: test_int_x86_avx512_mask_vfmaddsub_pd_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfmaddsub213pd %ymm2, %ymm1, %ymm3 {%k1} ; CHECK-NEXT: vfmaddsub213pd %ymm2, %ymm1, %ymm3 {%k1}
; CHECK-NEXT: vfmaddsub213pd %ymm2, %ymm1, %ymm0 ; CHECK-NEXT: vfmaddsub213pd %ymm2, %ymm1, %ymm0
; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) %res = call <4 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3)
%res1 = call <4 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1) %res1 = call <4 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1)
%res2 = fadd <4 x double> %res, %res1 %res2 = fadd <4 x double> %res, %res1
ret <4 x double> %res2 ret <4 x double> %res2
} }
declare <4 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.256(<4 x double>, <4 x double>, <4 x double>, i8) declare <4 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.256(<4 x double>, <4 x double>, <4 x double>, i8)
define <4 x double>@test_int_x86_avx512_mask3_vfmaddsub_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) { define <4 x double>@test_int_x86_avx512_mask3_vfmaddsub_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask3_vfmaddsub_pd_256: ; CHECK-LABEL: test_int_x86_avx512_mask3_vfmaddsub_pd_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm2, %zmm3 ; CHECK-NEXT: vmovaps %zmm2, %zmm3
; CHECK-NEXT: vfmaddsub231pd %ymm1, %ymm0, %ymm3 {%k1} ; CHECK-NEXT: vfmaddsub231pd %ymm1, %ymm0, %ymm3 {%k1}
; CHECK-NEXT: vfmaddsub213pd %ymm2, %ymm1, %ymm0 ; CHECK-NEXT: vfmaddsub213pd %ymm2, %ymm1, %ymm0
; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) %res = call <4 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3)
%res1 = call <4 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1) %res1 = call <4 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1)
%res2 = fadd <4 x double> %res, %res1 %res2 = fadd <4 x double> %res, %res1
ret <4 x double> %res2 ret <4 x double> %res2
} }
declare <4 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.256(<4 x double>, <4 x double>, <4 x double>, i8) declare <4 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.256(<4 x double>, <4 x double>, <4 x double>, i8)
define <4 x double>@test_int_x86_avx512_maskz_vfmaddsub_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) { define <4 x double>@test_int_x86_avx512_maskz_vfmaddsub_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_maskz_vfmaddsub_pd_256: ; CHECK-LABEL: test_int_x86_avx512_maskz_vfmaddsub_pd_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfmaddsub213pd %ymm2, %ymm1, %ymm3 {%k1} {z} ; CHECK-NEXT: vfmaddsub213pd %ymm2, %ymm1, %ymm3 {%k1} {z}
; CHECK-NEXT: vfmaddsub213pd %ymm2, %ymm1, %ymm0 ; CHECK-NEXT: vfmaddsub213pd %ymm2, %ymm1, %ymm0
; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) %res = call <4 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3)
%res1 = call <4 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1) %res1 = call <4 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1)
%res2 = fadd <4 x double> %res, %res1 %res2 = fadd <4 x double> %res, %res1
ret <4 x double> %res2 ret <4 x double> %res2
} }
define <4 x float>@test_int_x86_avx512_mask_vfmaddsub_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) { define <4 x float>@test_int_x86_avx512_mask_vfmaddsub_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vfmaddsub_ps_128: ; CHECK-LABEL: test_int_x86_avx512_mask_vfmaddsub_ps_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfmaddsub213ps %xmm2, %xmm1, %xmm3 {%k1} ; CHECK-NEXT: vfmaddsub213ps %xmm2, %xmm1, %xmm3 {%k1}
; CHECK-NEXT: vfmaddsub213ps %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vfmaddsub213ps %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) %res = call <4 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3)
%res1 = call <4 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1) %res1 = call <4 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1)
%res2 = fadd <4 x float> %res, %res1 %res2 = fadd <4 x float> %res, %res1
ret <4 x float> %res2 ret <4 x float> %res2
} }
declare <4 x float> @llvm.x86.avx512.mask3.vfmaddsub.ps.128(<4 x float>, <4 x float>, <4 x float>, i8) declare <4 x float> @llvm.x86.avx512.mask3.vfmaddsub.ps.128(<4 x float>, <4 x float>, <4 x float>, i8)
define <4 x float>@test_int_x86_avx512_mask3_vfmaddsub_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) { define <4 x float>@test_int_x86_avx512_mask3_vfmaddsub_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask3_vfmaddsub_ps_128: ; CHECK-LABEL: test_int_x86_avx512_mask3_vfmaddsub_ps_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm2, %zmm3 ; CHECK-NEXT: vmovaps %zmm2, %zmm3
; CHECK-NEXT: vfmaddsub231ps %xmm1, %xmm0, %xmm3 {%k1} ; CHECK-NEXT: vfmaddsub231ps %xmm1, %xmm0, %xmm3 {%k1}
; CHECK-NEXT: vfmaddsub213ps %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vfmaddsub213ps %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask3.vfmaddsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) %res = call <4 x float> @llvm.x86.avx512.mask3.vfmaddsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3)
%res1 = call <4 x float> @llvm.x86.avx512.mask3.vfmaddsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1) %res1 = call <4 x float> @llvm.x86.avx512.mask3.vfmaddsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1)
%res2 = fadd <4 x float> %res, %res1 %res2 = fadd <4 x float> %res, %res1
ret <4 x float> %res2 ret <4 x float> %res2
} }
declare <4 x float> @llvm.x86.avx512.maskz.vfmaddsub.ps.128(<4 x float>, <4 x float>, <4 x float>, i8) declare <4 x float> @llvm.x86.avx512.maskz.vfmaddsub.ps.128(<4 x float>, <4 x float>, <4 x float>, i8)
define <4 x float>@test_int_x86_avx512_maskz_vfmaddsub_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) { define <4 x float>@test_int_x86_avx512_maskz_vfmaddsub_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_maskz_vfmaddsub_ps_128: ; CHECK-LABEL: test_int_x86_avx512_maskz_vfmaddsub_ps_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfmaddsub213ps %xmm2, %xmm1, %xmm3 {%k1} {z} ; CHECK-NEXT: vfmaddsub213ps %xmm2, %xmm1, %xmm3 {%k1} {z}
; CHECK-NEXT: vfmaddsub213ps %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vfmaddsub213ps %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.maskz.vfmaddsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) %res = call <4 x float> @llvm.x86.avx512.maskz.vfmaddsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3)
%res1 = call <4 x float> @llvm.x86.avx512.maskz.vfmaddsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1) %res1 = call <4 x float> @llvm.x86.avx512.maskz.vfmaddsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1)
%res2 = fadd <4 x float> %res, %res1 %res2 = fadd <4 x float> %res, %res1
ret <4 x float> %res2 ret <4 x float> %res2
} }
define <8 x float>@test_int_x86_avx512_mask_vfmaddsub_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) { define <8 x float>@test_int_x86_avx512_mask_vfmaddsub_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vfmaddsub_ps_256: ; CHECK-LABEL: test_int_x86_avx512_mask_vfmaddsub_ps_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfmaddsub213ps %ymm2, %ymm1, %ymm3 {%k1} ; CHECK-NEXT: vfmaddsub213ps %ymm2, %ymm1, %ymm3 {%k1}
; CHECK-NEXT: vfmaddsub213ps %ymm2, %ymm1, %ymm0 ; CHECK-NEXT: vfmaddsub213ps %ymm2, %ymm1, %ymm0
; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) %res = call <8 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3)
%res1 = call <8 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1) %res1 = call <8 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1)
%res2 = fadd <8 x float> %res, %res1 %res2 = fadd <8 x float> %res, %res1
ret <8 x float> %res2 ret <8 x float> %res2
} }
declare <8 x float> @llvm.x86.avx512.mask3.vfmaddsub.ps.256(<8 x float>, <8 x float>, <8 x float>, i8) declare <8 x float> @llvm.x86.avx512.mask3.vfmaddsub.ps.256(<8 x float>, <8 x float>, <8 x float>, i8)
define <8 x float>@test_int_x86_avx512_mask3_vfmaddsub_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) { define <8 x float>@test_int_x86_avx512_mask3_vfmaddsub_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask3_vfmaddsub_ps_256: ; CHECK-LABEL: test_int_x86_avx512_mask3_vfmaddsub_ps_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm2, %zmm3 ; CHECK-NEXT: vmovaps %zmm2, %zmm3
; CHECK-NEXT: vfmaddsub231ps %ymm1, %ymm0, %ymm3 {%k1} ; CHECK-NEXT: vfmaddsub231ps %ymm1, %ymm0, %ymm3 {%k1}
; CHECK-NEXT: vfmaddsub213ps %ymm2, %ymm1, %ymm0 ; CHECK-NEXT: vfmaddsub213ps %ymm2, %ymm1, %ymm0
; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx512.mask3.vfmaddsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) %res = call <8 x float> @llvm.x86.avx512.mask3.vfmaddsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3)
%res1 = call <8 x float> @llvm.x86.avx512.mask3.vfmaddsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1) %res1 = call <8 x float> @llvm.x86.avx512.mask3.vfmaddsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1)
%res2 = fadd <8 x float> %res, %res1 %res2 = fadd <8 x float> %res, %res1
ret <8 x float> %res2 ret <8 x float> %res2
} }
declare <8 x float> @llvm.x86.avx512.maskz.vfmaddsub.ps.256(<8 x float>, <8 x float>, <8 x float>, i8) declare <8 x float> @llvm.x86.avx512.maskz.vfmaddsub.ps.256(<8 x float>, <8 x float>, <8 x float>, i8)
define <8 x float>@test_int_x86_avx512_maskz_vfmaddsub_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) { define <8 x float>@test_int_x86_avx512_maskz_vfmaddsub_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_maskz_vfmaddsub_ps_256: ; CHECK-LABEL: test_int_x86_avx512_maskz_vfmaddsub_ps_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vfmaddsub213ps %ymm2, %ymm1, %ymm3 {%k1} {z} ; CHECK-NEXT: vfmaddsub213ps %ymm2, %ymm1, %ymm3 {%k1} {z}
; CHECK-NEXT: vfmaddsub213ps %ymm2, %ymm1, %ymm0 ; CHECK-NEXT: vfmaddsub213ps %ymm2, %ymm1, %ymm0
; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx512.maskz.vfmaddsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) %res = call <8 x float> @llvm.x86.avx512.maskz.vfmaddsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3)
%res1 = call <8 x float> @llvm.x86.avx512.maskz.vfmaddsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1) %res1 = call <8 x float> @llvm.x86.avx512.maskz.vfmaddsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1)
%res2 = fadd <8 x float> %res, %res1 %res2 = fadd <8 x float> %res, %res1
ret <8 x float> %res2 ret <8 x float> %res2
} }
declare <2 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.128(<2 x double>, <2 x double>, <2 x double>, i8) declare <2 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.128(<2 x double>, <2 x double>, <2 x double>, i8)
define <2 x double>@test_int_x86_avx512_mask3_vfmsubadd_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) { define <2 x double>@test_int_x86_avx512_mask3_vfmsubadd_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsubadd_pd_128: ; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsubadd_pd_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm2, %zmm3 ; CHECK-NEXT: vmovaps %zmm2, %zmm3
; CHECK-NEXT: vfmsubadd231pd %xmm1, %xmm0, %xmm3 {%k1} ; CHECK-NEXT: vfmsubadd231pd %xmm1, %xmm0, %xmm3 {%k1}
; CHECK-NEXT: vfmsubadd213pd %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vfmsubadd213pd %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) %res = call <2 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3)
%res1 = call <2 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1) %res1 = call <2 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1)
%res2=fadd <2 x double> %res, %res1 %res2=fadd <2 x double> %res, %res1
ret <2 x double> %res2 ret <2 x double> %res2
} }
declare <4 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.256(<4 x double>, <4 x double>, <4 x double>, i8) declare <4 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.256(<4 x double>, <4 x double>, <4 x double>, i8)
define <4 x double>@test_int_x86_avx512_mask3_vfmsubadd_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) { define <4 x double>@test_int_x86_avx512_mask3_vfmsubadd_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsubadd_pd_256: ; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsubadd_pd_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm2, %zmm3 ; CHECK-NEXT: vmovaps %zmm2, %zmm3
; CHECK-NEXT: vfmsubadd231pd %ymm1, %ymm0, %ymm3 {%k1} ; CHECK-NEXT: vfmsubadd231pd %ymm1, %ymm0, %ymm3 {%k1}
; CHECK-NEXT: vfmsubadd213pd %ymm2, %ymm1, %ymm0 ; CHECK-NEXT: vfmsubadd213pd %ymm2, %ymm1, %ymm0
; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) %res = call <4 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3)
%res1 = call <4 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1) %res1 = call <4 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1)
%res2=fadd <4 x double> %res, %res1 %res2=fadd <4 x double> %res, %res1
ret <4 x double> %res2 ret <4 x double> %res2
} }
declare <4 x float> @llvm.x86.avx512.mask3.vfmsubadd.ps.128(<4 x float>, <4 x float>, <4 x float>, i8) declare <4 x float> @llvm.x86.avx512.mask3.vfmsubadd.ps.128(<4 x float>, <4 x float>, <4 x float>, i8)
define <4 x float>@test_int_x86_avx512_mask3_vfmsubadd_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) { define <4 x float>@test_int_x86_avx512_mask3_vfmsubadd_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsubadd_ps_128: ; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsubadd_ps_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm2, %zmm3 ; CHECK-NEXT: vmovaps %zmm2, %zmm3
; CHECK-NEXT: vfmsubadd231ps %xmm1, %xmm0, %xmm3 {%k1} ; CHECK-NEXT: vfmsubadd231ps %xmm1, %xmm0, %xmm3 {%k1}
; CHECK-NEXT: vfmsubadd213ps %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vfmsubadd213ps %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask3.vfmsubadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) %res = call <4 x float> @llvm.x86.avx512.mask3.vfmsubadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3)
%res1 = call <4 x float> @llvm.x86.avx512.mask3.vfmsubadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1) %res1 = call <4 x float> @llvm.x86.avx512.mask3.vfmsubadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1)
%res2=fadd <4 x float> %res, %res1 %res2=fadd <4 x float> %res, %res1
ret <4 x float> %res2 ret <4 x float> %res2
} }
declare <8 x float> @llvm.x86.avx512.mask3.vfmsubadd.ps.256(<8 x float>, <8 x float>, <8 x float>, i8) declare <8 x float> @llvm.x86.avx512.mask3.vfmsubadd.ps.256(<8 x float>, <8 x float>, <8 x float>, i8)
define <8 x float>@test_int_x86_avx512_mask3_vfmsubadd_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) { define <8 x float>@test_int_x86_avx512_mask3_vfmsubadd_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsubadd_ps_256: ; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsubadd_ps_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm2, %zmm3 ; CHECK-NEXT: vmovaps %zmm2, %zmm3
; CHECK-NEXT: vfmsubadd231ps %ymm1, %ymm0, %ymm3 {%k1} ; CHECK-NEXT: vfmsubadd231ps %ymm1, %ymm0, %ymm3 {%k1}
; CHECK-NEXT: vfmsubadd213ps %ymm2, %ymm1, %ymm0 ; CHECK-NEXT: vfmsubadd213ps %ymm2, %ymm1, %ymm0
; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx512.mask3.vfmsubadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) %res = call <8 x float> @llvm.x86.avx512.mask3.vfmsubadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3)
%res1 = call <8 x float> @llvm.x86.avx512.mask3.vfmsubadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1) %res1 = call <8 x float> @llvm.x86.avx512.mask3.vfmsubadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1)
%res2=fadd <8 x float> %res, %res1 %res2=fadd <8 x float> %res, %res1
▲ Show 20 Lines • Show All 2,513 Lines • ▼ Show 20 Lines; CHECK: vpmovuswb %ymm0, (%rdi) {%k1}
ret void ret void
} }
declare <4 x i32> @llvm.x86.avx512.mask.pmaddw.d.128(<8 x i16>, <8 x i16>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.pmaddw.d.128(<8 x i16>, <8 x i16>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_pmaddw_d_128(<8 x i16> %x0, <8 x i16> %x1, <4 x i32> %x2, i8 %x3) { define <4 x i32>@test_int_x86_avx512_mask_pmaddw_d_128(<8 x i16> %x0, <8 x i16> %x1, <4 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmaddw_d_128: ; CHECK-LABEL: test_int_x86_avx512_mask_pmaddw_d_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmaddwd %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vpmaddwd %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vpmaddwd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpmaddwd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.pmaddw.d.128(<8 x i16> %x0, <8 x i16> %x1, <4 x i32> %x2, i8 %x3) %res = call <4 x i32> @llvm.x86.avx512.mask.pmaddw.d.128(<8 x i16> %x0, <8 x i16> %x1, <4 x i32> %x2, i8 %x3)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.pmaddw.d.128(<8 x i16> %x0, <8 x i16> %x1, <4 x i32> %x2, i8 -1) %res1 = call <4 x i32> @llvm.x86.avx512.mask.pmaddw.d.128(<8 x i16> %x0, <8 x i16> %x1, <4 x i32> %x2, i8 -1)
%res2 = add <4 x i32> %res, %res1 %res2 = add <4 x i32> %res, %res1
ret <4 x i32> %res2 ret <4 x i32> %res2
} }
declare <8 x i32> @llvm.x86.avx512.mask.pmaddw.d.256(<16 x i16>, <16 x i16>, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.pmaddw.d.256(<16 x i16>, <16 x i16>, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_pmaddw_d_256(<16 x i16> %x0, <16 x i16> %x1, <8 x i32> %x2, i8 %x3) { define <8 x i32>@test_int_x86_avx512_mask_pmaddw_d_256(<16 x i16> %x0, <16 x i16> %x1, <8 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmaddw_d_256: ; CHECK-LABEL: test_int_x86_avx512_mask_pmaddw_d_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmaddwd %ymm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vpmaddwd %ymm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: vpmaddwd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vpmaddwd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm0, %ymm2, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm2, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.pmaddw.d.256(<16 x i16> %x0, <16 x i16> %x1, <8 x i32> %x2, i8 %x3) %res = call <8 x i32> @llvm.x86.avx512.mask.pmaddw.d.256(<16 x i16> %x0, <16 x i16> %x1, <8 x i32> %x2, i8 %x3)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.pmaddw.d.256(<16 x i16> %x0, <16 x i16> %x1, <8 x i32> %x2, i8 -1) %res1 = call <8 x i32> @llvm.x86.avx512.mask.pmaddw.d.256(<16 x i16> %x0, <16 x i16> %x1, <8 x i32> %x2, i8 -1)
%res2 = add <8 x i32> %res, %res1 %res2 = add <8 x i32> %res, %res1
ret <8 x i32> %res2 ret <8 x i32> %res2
} }
declare <8 x i16> @llvm.x86.avx512.mask.pmaddubs.w.128(<16 x i8>, <16 x i8>, <8 x i16>, i8) declare <8 x i16> @llvm.x86.avx512.mask.pmaddubs.w.128(<16 x i8>, <16 x i8>, <8 x i16>, i8)
define <8 x i16>@test_int_x86_avx512_mask_pmaddubs_w_128(<16 x i8> %x0, <16 x i8> %x1, <8 x i16> %x2, i8 %x3) { define <8 x i16>@test_int_x86_avx512_mask_pmaddubs_w_128(<16 x i8> %x0, <16 x i8> %x1, <8 x i16> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmaddubs_w_128: ; CHECK-LABEL: test_int_x86_avx512_mask_pmaddubs_w_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmaddubsw %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vpmaddubsw %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vpmaddubsw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpmaddubsw %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddw %xmm0, %xmm2, %xmm0 ; CHECK-NEXT: vpaddw %xmm0, %xmm2, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i16> @llvm.x86.avx512.mask.pmaddubs.w.128(<16 x i8> %x0, <16 x i8> %x1, <8 x i16> %x2, i8 %x3) %res = call <8 x i16> @llvm.x86.avx512.mask.pmaddubs.w.128(<16 x i8> %x0, <16 x i8> %x1, <8 x i16> %x2, i8 %x3)
%res1 = call <8 x i16> @llvm.x86.avx512.mask.pmaddubs.w.128(<16 x i8> %x0, <16 x i8> %x1, <8 x i16> %x2, i8 -1) %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmaddubs.w.128(<16 x i8> %x0, <16 x i8> %x1, <8 x i16> %x2, i8 -1)
%res2 = add <8 x i16> %res, %res1 %res2 = add <8 x i16> %res, %res1
ret <8 x i16> %res2 ret <8 x i16> %res2
▲ Show 20 Lines • Show All 167 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
ret <32 x i8> %res4 ret <32 x i8> %res4
} }
declare <8 x i16> @llvm.x86.avx512.mask.dbpsadbw.128(<16 x i8>, <16 x i8>, i32, <8 x i16>, i8) declare <8 x i16> @llvm.x86.avx512.mask.dbpsadbw.128(<16 x i8>, <16 x i8>, i32, <8 x i16>, i8)
define <8 x i16>@test_int_x86_avx512_mask_dbpsadbw_128(<16 x i8> %x0, <16 x i8> %x1, <8 x i16> %x3, i8 %x4) { define <8 x i16>@test_int_x86_avx512_mask_dbpsadbw_128(<16 x i8> %x0, <16 x i8> %x1, <8 x i16> %x3, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_dbpsadbw_128: ; CHECK-LABEL: test_int_x86_avx512_mask_dbpsadbw_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vdbpsadbw $2, %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vdbpsadbw $2, %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vdbpsadbw $2, %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: vdbpsadbw $2, %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: vdbpsadbw $2, %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vdbpsadbw $2, %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddw %xmm3, %xmm2, %xmm1 ; CHECK-NEXT: vpaddw %xmm3, %xmm2, %xmm1
; CHECK-NEXT: vpaddw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpaddw %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i16> @llvm.x86.avx512.mask.dbpsadbw.128(<16 x i8> %x0, <16 x i8> %x1, i32 2, <8 x i16> %x3, i8 %x4) %res = call <8 x i16> @llvm.x86.avx512.mask.dbpsadbw.128(<16 x i8> %x0, <16 x i8> %x1, i32 2, <8 x i16> %x3, i8 %x4)
%res1 = call <8 x i16> @llvm.x86.avx512.mask.dbpsadbw.128(<16 x i8> %x0, <16 x i8> %x1, i32 2, <8 x i16> zeroinitializer, i8 %x4) %res1 = call <8 x i16> @llvm.x86.avx512.mask.dbpsadbw.128(<16 x i8> %x0, <16 x i8> %x1, i32 2, <8 x i16> zeroinitializer, i8 %x4)
▲ Show 20 Lines • Show All 83 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
ret <16 x i16> %res4 ret <16 x i16> %res4
} }
declare <8 x i16> @llvm.x86.avx512.pbroadcastw.128(<8 x i16>, <8 x i16>, i8) declare <8 x i16> @llvm.x86.avx512.pbroadcastw.128(<8 x i16>, <8 x i16>, i8)
define <8 x i16>@test_int_x86_avx512_pbroadcastw_128(<8 x i16> %x0, <8 x i16> %x1, i8 %mask) { define <8 x i16>@test_int_x86_avx512_pbroadcastw_128(<8 x i16> %x0, <8 x i16> %x1, i8 %mask) {
; CHECK-LABEL: test_int_x86_avx512_pbroadcastw_128: ; CHECK-LABEL: test_int_x86_avx512_pbroadcastw_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpbroadcastw %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpbroadcastw %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpbroadcastw %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpbroadcastw %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpbroadcastw %xmm0, %xmm0 ; CHECK-NEXT: vpbroadcastw %xmm0, %xmm0
; CHECK-NEXT: vpaddw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpaddw %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddw %xmm0, %xmm2, %xmm0 ; CHECK-NEXT: vpaddw %xmm0, %xmm2, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i16> @llvm.x86.avx512.pbroadcastw.128(<8 x i16> %x0, <8 x i16> %x1, i8 -1) %res = call <8 x i16> @llvm.x86.avx512.pbroadcastw.128(<8 x i16> %x0, <8 x i16> %x1, i8 -1)
%res1 = call <8 x i16> @llvm.x86.avx512.pbroadcastw.128(<8 x i16> %x0, <8 x i16> %x1, i8 %mask) %res1 = call <8 x i16> @llvm.x86.avx512.pbroadcastw.128(<8 x i16> %x0, <8 x i16> %x1, i8 %mask)
▲ Show 20 Lines • Show All 115 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
ret <32 x i8> %res ret <32 x i8> %res
} }
declare <8 x i16> @llvm.x86.avx512.cvtmask2w.128(i8) declare <8 x i16> @llvm.x86.avx512.cvtmask2w.128(i8)
define <8 x i16>@test_int_x86_avx512_cvtmask2w_128(i8 %x0) { define <8 x i16>@test_int_x86_avx512_cvtmask2w_128(i8 %x0) {
; CHECK-LABEL: test_int_x86_avx512_cvtmask2w_128: ; CHECK-LABEL: test_int_x86_avx512_cvtmask2w_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k0
; CHECK-NEXT: kmovw %eax, %k0
; CHECK-NEXT: vpmovm2w %k0, %xmm0 ; CHECK-NEXT: vpmovm2w %k0, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i16> @llvm.x86.avx512.cvtmask2w.128(i8 %x0) %res = call <8 x i16> @llvm.x86.avx512.cvtmask2w.128(i8 %x0)
ret <8 x i16> %res ret <8 x i16> %res
} }
declare <16 x i16> @llvm.x86.avx512.cvtmask2w.256(i16) declare <16 x i16> @llvm.x86.avx512.cvtmask2w.256(i16)
define <16 x i16>@test_int_x86_avx512_cvtmask2w_256(i16 %x0) { define <16 x i16>@test_int_x86_avx512_cvtmask2w_256(i16 %x0) {
; CHECK-LABEL: test_int_x86_avx512_cvtmask2w_256: ; CHECK-LABEL: test_int_x86_avx512_cvtmask2w_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k0 ; CHECK-NEXT: kmovw %edi, %k0
; CHECK-NEXT: vpmovm2w %k0, %ymm0 ; CHECK-NEXT: vpmovm2w %k0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <16 x i16> @llvm.x86.avx512.cvtmask2w.256(i16 %x0) %res = call <16 x i16> @llvm.x86.avx512.cvtmask2w.256(i16 %x0)
ret <16 x i16> %res ret <16 x i16> %res
} }
declare <8 x i16> @llvm.x86.avx512.mask.psrl.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8) declare <8 x i16> @llvm.x86.avx512.mask.psrl.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)
define <8 x i16>@test_int_x86_avx512_mask_psrl_w_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) { define <8 x i16>@test_int_x86_avx512_mask_psrl_w_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psrl_w_128: ; CHECK-LABEL: test_int_x86_avx512_mask_psrl_w_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsrlw %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vpsrlw %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vpsrlw %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: vpsrlw %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: vpsrlw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpsrlw %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddw %xmm0, %xmm2, %xmm0 ; CHECK-NEXT: vpaddw %xmm0, %xmm2, %xmm0
; CHECK-NEXT: vpaddw %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vpaddw %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i16> @llvm.x86.avx512.mask.psrl.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) %res = call <8 x i16> @llvm.x86.avx512.mask.psrl.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3)
%res1 = call <8 x i16> @llvm.x86.avx512.mask.psrl.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1) %res1 = call <8 x i16> @llvm.x86.avx512.mask.psrl.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1)
Show All 23 Lines; CHECK-NEXT: retq
ret <16 x i16> %res4 ret <16 x i16> %res4
} }
declare <8 x i16> @llvm.x86.avx512.mask.psrl.wi.128(<8 x i16>, i8, <8 x i16>, i8) declare <8 x i16> @llvm.x86.avx512.mask.psrl.wi.128(<8 x i16>, i8, <8 x i16>, i8)
define <8 x i16>@test_int_x86_avx512_mask_psrl_wi_128(<8 x i16> %x0, i8 %x1, <8 x i16> %x2, i8 %x3) { define <8 x i16>@test_int_x86_avx512_mask_psrl_wi_128(<8 x i16> %x0, i8 %x1, <8 x i16> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psrl_wi_128: ; CHECK-LABEL: test_int_x86_avx512_mask_psrl_wi_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsrlw $3, %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpsrlw $3, %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpsrlw $3, %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpsrlw $3, %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpsrlw $3, %xmm0, %xmm0 ; CHECK-NEXT: vpsrlw $3, %xmm0, %xmm0
; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0
; CHECK-NEXT: vpaddw %xmm0, %xmm2, %xmm0 ; CHECK-NEXT: vpaddw %xmm0, %xmm2, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i16> @llvm.x86.avx512.mask.psrl.wi.128(<8 x i16> %x0, i8 3, <8 x i16> %x2, i8 %x3) %res = call <8 x i16> @llvm.x86.avx512.mask.psrl.wi.128(<8 x i16> %x0, i8 3, <8 x i16> %x2, i8 %x3)
%res1 = call <8 x i16> @llvm.x86.avx512.mask.psrl.wi.128(<8 x i16> %x0, i8 3, <8 x i16> %x2, i8 -1) %res1 = call <8 x i16> @llvm.x86.avx512.mask.psrl.wi.128(<8 x i16> %x0, i8 3, <8 x i16> %x2, i8 -1)
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
ret <16 x i16> %res4 ret <16 x i16> %res4
} }
declare <8 x i16> @llvm.x86.avx512.mask.psrlv8.hi(<8 x i16>, <8 x i16>, <8 x i16>, i8) declare <8 x i16> @llvm.x86.avx512.mask.psrlv8.hi(<8 x i16>, <8 x i16>, <8 x i16>, i8)
define <8 x i16>@test_int_x86_avx512_mask_psrlv8_hi(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) { define <8 x i16>@test_int_x86_avx512_mask_psrlv8_hi(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psrlv8_hi: ; CHECK-LABEL: test_int_x86_avx512_mask_psrlv8_hi:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsrlvw %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vpsrlvw %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vpsrlvw %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: vpsrlvw %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: vpsrlvw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpsrlvw %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddw %xmm3, %xmm2, %xmm1 ; CHECK-NEXT: vpaddw %xmm3, %xmm2, %xmm1
; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i16> @llvm.x86.avx512.mask.psrlv8.hi(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) %res = call <8 x i16> @llvm.x86.avx512.mask.psrlv8.hi(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3)
%res1 = call <8 x i16> @llvm.x86.avx512.mask.psrlv8.hi(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> zeroinitializer, i8 %x3) %res1 = call <8 x i16> @llvm.x86.avx512.mask.psrlv8.hi(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> zeroinitializer, i8 %x3)
%res2 = call <8 x i16> @llvm.x86.avx512.mask.psrlv8.hi(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1) %res2 = call <8 x i16> @llvm.x86.avx512.mask.psrlv8.hi(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1)
%res3 = add <8 x i16> %res, %res1 %res3 = add <8 x i16> %res, %res1
%res4 = add <8 x i16> %res3, %res2 %res4 = add <8 x i16> %res3, %res2
ret <8 x i16> %res4 ret <8 x i16> %res4
} }
declare <8 x i16> @llvm.x86.avx512.mask.psra.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8) declare <8 x i16> @llvm.x86.avx512.mask.psra.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)
define <8 x i16>@test_int_x86_avx512_mask_psra_w_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) { define <8 x i16>@test_int_x86_avx512_mask_psra_w_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psra_w_128: ; CHECK-LABEL: test_int_x86_avx512_mask_psra_w_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsraw %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vpsraw %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vpsraw %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: vpsraw %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: vpsraw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpsraw %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddw %xmm3, %xmm2, %xmm1 ; CHECK-NEXT: vpaddw %xmm3, %xmm2, %xmm1
; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i16> @llvm.x86.avx512.mask.psra.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) %res = call <8 x i16> @llvm.x86.avx512.mask.psra.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3)
%res1 = call <8 x i16> @llvm.x86.avx512.mask.psra.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> zeroinitializer, i8 %x3) %res1 = call <8 x i16> @llvm.x86.avx512.mask.psra.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> zeroinitializer, i8 %x3)
%res2 = call <8 x i16> @llvm.x86.avx512.mask.psra.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1) %res2 = call <8 x i16> @llvm.x86.avx512.mask.psra.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1)
%res3 = add <8 x i16> %res, %res1 %res3 = add <8 x i16> %res, %res1
%res4 = add <8 x i16> %res3, %res2 %res4 = add <8 x i16> %res3, %res2
ret <8 x i16> %res4 ret <8 x i16> %res4
} }
declare <8 x i16> @llvm.x86.avx512.mask.psra.wi.128(<8 x i16>, i8, <8 x i16>, i8) declare <8 x i16> @llvm.x86.avx512.mask.psra.wi.128(<8 x i16>, i8, <8 x i16>, i8)
define <8 x i16>@test_int_x86_avx512_mask_psra_wi_128(<8 x i16> %x0, i8 %x1, <8 x i16> %x2, i8 %x3) { define <8 x i16>@test_int_x86_avx512_mask_psra_wi_128(<8 x i16> %x0, i8 %x1, <8 x i16> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psra_wi_128: ; CHECK-LABEL: test_int_x86_avx512_mask_psra_wi_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsraw $3, %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpsraw $3, %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpsraw $3, %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpsraw $3, %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpsraw $3, %xmm0, %xmm0 ; CHECK-NEXT: vpsraw $3, %xmm0, %xmm0
; CHECK-NEXT: vpaddw %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpaddw %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i16> @llvm.x86.avx512.mask.psra.wi.128(<8 x i16> %x0, i8 3, <8 x i16> %x2, i8 %x3) %res = call <8 x i16> @llvm.x86.avx512.mask.psra.wi.128(<8 x i16> %x0, i8 3, <8 x i16> %x2, i8 %x3)
%res1 = call <8 x i16> @llvm.x86.avx512.mask.psra.wi.128(<8 x i16> %x0, i8 3, <8 x i16> zeroinitializer, i8 %x3) %res1 = call <8 x i16> @llvm.x86.avx512.mask.psra.wi.128(<8 x i16> %x0, i8 3, <8 x i16> zeroinitializer, i8 %x3)
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
ret <16 x i16> %res4 ret <16 x i16> %res4
} }
declare <4 x i32> @llvm.x86.avx512.mask.pshuf.d.128(<4 x i32>, i16, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.pshuf.d.128(<4 x i32>, i16, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_pshuf_d_128(<4 x i32> %x0, i16 %x1, <4 x i32> %x2, i8 %x3) { define <4 x i32>@test_int_x86_avx512_mask_pshuf_d_128(<4 x i32> %x0, i16 %x1, <4 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_pshuf_d_128: ; CHECK-LABEL: test_int_x86_avx512_mask_pshuf_d_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpshufd $3, %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpshufd $3, %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpshufd $3, %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpshufd $3, %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpshufd $3, %xmm0, %xmm0 ; CHECK-NEXT: vpshufd $3, %xmm0, %xmm0
; CHECK-NEXT: ## xmm0 = xmm0[3,0,0,0] ; CHECK-NEXT: ## xmm0 = xmm0[3,0,0,0]
; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.pshuf.d.128(<4 x i32> %x0, i16 3, <4 x i32> %x2, i8 %x3) %res = call <4 x i32> @llvm.x86.avx512.mask.pshuf.d.128(<4 x i32> %x0, i16 3, <4 x i32> %x2, i8 %x3)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.pshuf.d.128(<4 x i32> %x0, i16 3, <4 x i32> zeroinitializer, i8 %x3) %res1 = call <4 x i32> @llvm.x86.avx512.mask.pshuf.d.128(<4 x i32> %x0, i16 3, <4 x i32> zeroinitializer, i8 %x3)
%res2 = call <4 x i32> @llvm.x86.avx512.mask.pshuf.d.128(<4 x i32> %x0, i16 3, <4 x i32> %x2, i8 -1) %res2 = call <4 x i32> @llvm.x86.avx512.mask.pshuf.d.128(<4 x i32> %x0, i16 3, <4 x i32> %x2, i8 -1)
%res3 = add <4 x i32> %res, %res1 %res3 = add <4 x i32> %res, %res1
%res4 = add <4 x i32> %res3, %res2 %res4 = add <4 x i32> %res3, %res2
ret <4 x i32> %res4 ret <4 x i32> %res4
} }
declare <8 x i32> @llvm.x86.avx512.mask.pshuf.d.256(<8 x i32>, i16, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.pshuf.d.256(<8 x i32>, i16, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_pshuf_d_256(<8 x i32> %x0, i16 %x1, <8 x i32> %x2, i8 %x3) { define <8 x i32>@test_int_x86_avx512_mask_pshuf_d_256(<8 x i32> %x0, i16 %x1, <8 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_pshuf_d_256: ; CHECK-LABEL: test_int_x86_avx512_mask_pshuf_d_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpshufd $3, %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vpshufd $3, %ymm0, %ymm1 {%k1}
; CHECK-NEXT: vpshufd $3, %ymm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpshufd $3, %ymm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vpshufd $3, %ymm0, %ymm0 ; CHECK-NEXT: vpshufd $3, %ymm0, %ymm0
; CHECK-NEXT: ## ymm0 = ymm0[3,0,0,0,7,4,4,4] ; CHECK-NEXT: ## ymm0 = ymm0[3,0,0,0,7,4,4,4]
; CHECK-NEXT: vpaddd %ymm2, %ymm1, %ymm1 ; CHECK-NEXT: vpaddd %ymm2, %ymm1, %ymm1
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.pshuf.d.256(<8 x i32> %x0, i16 3, <8 x i32> %x2, i8 %x3) %res = call <8 x i32> @llvm.x86.avx512.mask.pshuf.d.256(<8 x i32> %x0, i16 3, <8 x i32> %x2, i8 %x3)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.pshuf.d.256(<8 x i32> %x0, i16 3, <8 x i32> zeroinitializer, i8 %x3) %res1 = call <8 x i32> @llvm.x86.avx512.mask.pshuf.d.256(<8 x i32> %x0, i16 3, <8 x i32> zeroinitializer, i8 %x3)
%res2 = call <8 x i32> @llvm.x86.avx512.mask.pshuf.d.256(<8 x i32> %x0, i16 3, <8 x i32> %x2, i8 -1) %res2 = call <8 x i32> @llvm.x86.avx512.mask.pshuf.d.256(<8 x i32> %x0, i16 3, <8 x i32> %x2, i8 -1)
%res3 = add <8 x i32> %res, %res1 %res3 = add <8 x i32> %res, %res1
%res4 = add <8 x i32> %res3, %res2 %res4 = add <8 x i32> %res3, %res2
ret <8 x i32> %res4 ret <8 x i32> %res4
} }
declare <8 x i16> @llvm.x86.avx512.mask.pshufh.w.128(<8 x i16>, i8, <8 x i16>, i8) declare <8 x i16> @llvm.x86.avx512.mask.pshufh.w.128(<8 x i16>, i8, <8 x i16>, i8)
define <8 x i16>@test_int_x86_avx512_mask_pshufh_w_128(<8 x i16> %x0, i8 %x1, <8 x i16> %x2, i8 %x3) { define <8 x i16>@test_int_x86_avx512_mask_pshufh_w_128(<8 x i16> %x0, i8 %x1, <8 x i16> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_pshufh_w_128: ; CHECK-LABEL: test_int_x86_avx512_mask_pshufh_w_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpshufhw $3, %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpshufhw $3, %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpshufhw $3, %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpshufhw $3, %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpshufhw $3, %xmm0, %xmm0 ; CHECK-NEXT: vpshufhw $3, %xmm0, %xmm0
; CHECK-NEXT: ## xmm0 = xmm0[0,1,2,3,7,4,4,4] ; CHECK-NEXT: ## xmm0 = xmm0[0,1,2,3,7,4,4,4]
; CHECK-NEXT: vpaddw %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpaddw %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i16> @llvm.x86.avx512.mask.pshufh.w.128(<8 x i16> %x0, i8 3, <8 x i16> %x2, i8 %x3) %res = call <8 x i16> @llvm.x86.avx512.mask.pshufh.w.128(<8 x i16> %x0, i8 3, <8 x i16> %x2, i8 %x3)
Show All 25 Lines; CHECK-NEXT: retq
ret <16 x i16> %res4 ret <16 x i16> %res4
} }
declare <8 x i16> @llvm.x86.avx512.mask.pshufl.w.128(<8 x i16>, i8, <8 x i16>, i8) declare <8 x i16> @llvm.x86.avx512.mask.pshufl.w.128(<8 x i16>, i8, <8 x i16>, i8)
define <8 x i16>@test_int_x86_avx512_mask_pshufl_w_128(<8 x i16> %x0, i8 %x1, <8 x i16> %x2, i8 %x3) { define <8 x i16>@test_int_x86_avx512_mask_pshufl_w_128(<8 x i16> %x0, i8 %x1, <8 x i16> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_pshufl_w_128: ; CHECK-LABEL: test_int_x86_avx512_mask_pshufl_w_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpshuflw $3, %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpshuflw $3, %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpshuflw $3, %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpshuflw $3, %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpshuflw $3, %xmm0, %xmm0 ; CHECK-NEXT: vpshuflw $3, %xmm0, %xmm0
; CHECK-NEXT: ## xmm0 = xmm0[3,0,0,0,4,5,6,7] ; CHECK-NEXT: ## xmm0 = xmm0[3,0,0,0,4,5,6,7]
; CHECK-NEXT: vpaddw %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpaddw %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i16> @llvm.x86.avx512.mask.pshufl.w.128(<8 x i16> %x0, i8 3, <8 x i16> %x2, i8 %x3) %res = call <8 x i16> @llvm.x86.avx512.mask.pshufl.w.128(<8 x i16> %x0, i8 3, <8 x i16> %x2, i8 %x3)
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
ret <16 x i16> %res4 ret <16 x i16> %res4
} }
declare <8 x i16> @llvm.x86.avx512.mask.psrav8.hi(<8 x i16>, <8 x i16>, <8 x i16>, i8) declare <8 x i16> @llvm.x86.avx512.mask.psrav8.hi(<8 x i16>, <8 x i16>, <8 x i16>, i8)
define <8 x i16>@test_int_x86_avx512_mask_psrav8_hi(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) { define <8 x i16>@test_int_x86_avx512_mask_psrav8_hi(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psrav8_hi: ; CHECK-LABEL: test_int_x86_avx512_mask_psrav8_hi:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsravw %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vpsravw %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vpsravw %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: vpsravw %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: vpsravw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpsravw %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddw %xmm3, %xmm2, %xmm1 ; CHECK-NEXT: vpaddw %xmm3, %xmm2, %xmm1
; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i16> @llvm.x86.avx512.mask.psrav8.hi(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) %res = call <8 x i16> @llvm.x86.avx512.mask.psrav8.hi(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3)
%res1 = call <8 x i16> @llvm.x86.avx512.mask.psrav8.hi(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> zeroinitializer, i8 %x3) %res1 = call <8 x i16> @llvm.x86.avx512.mask.psrav8.hi(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> zeroinitializer, i8 %x3)
%res2 = call <8 x i16> @llvm.x86.avx512.mask.psrav8.hi(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1) %res2 = call <8 x i16> @llvm.x86.avx512.mask.psrav8.hi(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1)
%res3 = add <8 x i16> %res, %res1 %res3 = add <8 x i16> %res, %res1
%res4 = add <8 x i16> %res3, %res2 %res4 = add <8 x i16> %res3, %res2
ret <8 x i16> %res4 ret <8 x i16> %res4
} }
declare <8 x i16> @llvm.x86.avx512.mask.psll.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8) declare <8 x i16> @llvm.x86.avx512.mask.psll.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)
define <8 x i16>@test_int_x86_avx512_mask_psll_w_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) { define <8 x i16>@test_int_x86_avx512_mask_psll_w_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psll_w_128: ; CHECK-LABEL: test_int_x86_avx512_mask_psll_w_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsllw %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vpsllw %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vpsllw %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: vpsllw %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: vpsllw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpsllw %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddw %xmm3, %xmm2, %xmm1 ; CHECK-NEXT: vpaddw %xmm3, %xmm2, %xmm1
; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i16> @llvm.x86.avx512.mask.psll.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) %res = call <8 x i16> @llvm.x86.avx512.mask.psll.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3)
%res1 = call <8 x i16> @llvm.x86.avx512.mask.psll.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> zeroinitializer, i8 %x3) %res1 = call <8 x i16> @llvm.x86.avx512.mask.psll.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> zeroinitializer, i8 %x3)
Show All 23 Lines; CHECK-NEXT: retq
ret <16 x i16> %res4 ret <16 x i16> %res4
} }
declare <8 x i16> @llvm.x86.avx512.mask.psll.wi.128(<8 x i16>, i8, <8 x i16>, i8) declare <8 x i16> @llvm.x86.avx512.mask.psll.wi.128(<8 x i16>, i8, <8 x i16>, i8)
define <8 x i16>@test_int_x86_avx512_mask_psll_wi_128(<8 x i16> %x0, i8 %x1, <8 x i16> %x2, i8 %x3) { define <8 x i16>@test_int_x86_avx512_mask_psll_wi_128(<8 x i16> %x0, i8 %x1, <8 x i16> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psll_wi_128: ; CHECK-LABEL: test_int_x86_avx512_mask_psll_wi_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsllw $3, %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpsllw $3, %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpsllw $3, %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpsllw $3, %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpsllw $3, %xmm0, %xmm0 ; CHECK-NEXT: vpsllw $3, %xmm0, %xmm0
; CHECK-NEXT: vpaddw %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpaddw %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i16> @llvm.x86.avx512.mask.psll.wi.128(<8 x i16> %x0, i8 3, <8 x i16> %x2, i8 %x3) %res = call <8 x i16> @llvm.x86.avx512.mask.psll.wi.128(<8 x i16> %x0, i8 3, <8 x i16> %x2, i8 %x3)
%res1 = call <8 x i16> @llvm.x86.avx512.mask.psll.wi.128(<8 x i16> %x0, i8 3, <8 x i16> zeroinitializer, i8 %x3) %res1 = call <8 x i16> @llvm.x86.avx512.mask.psll.wi.128(<8 x i16> %x0, i8 3, <8 x i16> zeroinitializer, i8 %x3)
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
ret <16 x i16> %res4 ret <16 x i16> %res4
} }
declare <8 x i16> @llvm.x86.avx512.mask.psllv8.hi(<8 x i16>, <8 x i16>, <8 x i16>, i8) declare <8 x i16> @llvm.x86.avx512.mask.psllv8.hi(<8 x i16>, <8 x i16>, <8 x i16>, i8)
define <8 x i16>@test_int_x86_avx512_mask_psllv8_hi(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) { define <8 x i16>@test_int_x86_avx512_mask_psllv8_hi(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psllv8_hi: ; CHECK-LABEL: test_int_x86_avx512_mask_psllv8_hi:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsllvw %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vpsllvw %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vpsllvw %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: vpsllvw %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: vpsllvw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpsllvw %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddw %xmm3, %xmm2, %xmm1 ; CHECK-NEXT: vpaddw %xmm3, %xmm2, %xmm1
; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i16> @llvm.x86.avx512.mask.psllv8.hi(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) %res = call <8 x i16> @llvm.x86.avx512.mask.psllv8.hi(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3)
%res1 = call <8 x i16> @llvm.x86.avx512.mask.psllv8.hi(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> zeroinitializer, i8 %x3) %res1 = call <8 x i16> @llvm.x86.avx512.mask.psllv8.hi(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> zeroinitializer, i8 %x3)
%res2 = call <8 x i16> @llvm.x86.avx512.mask.psllv8.hi(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1) %res2 = call <8 x i16> @llvm.x86.avx512.mask.psllv8.hi(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1)
%res3 = add <8 x i16> %res, %res1 %res3 = add <8 x i16> %res, %res1
%res4 = add <8 x i16> %res3, %res2 %res4 = add <8 x i16> %res3, %res2
ret <8 x i16> %res4 ret <8 x i16> %res4
} }
declare <8 x i16> @llvm.x86.avx512.mask.pmovzxb.w.128(<16 x i8>, <8 x i16>, i8) declare <8 x i16> @llvm.x86.avx512.mask.pmovzxb.w.128(<16 x i8>, <8 x i16>, i8)
define <8 x i16>@test_int_x86_avx512_mask_pmovzxb_w_128(<16 x i8> %x0, <8 x i16> %x1, i8 %x2) { define <8 x i16>@test_int_x86_avx512_mask_pmovzxb_w_128(<16 x i8> %x0, <8 x i16> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxb_w_128: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxb_w_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovzxbw %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpmovzxbw %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpmovzxbw %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpmovzxbw %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpmovzxbw %xmm0, %xmm0 ; CHECK-NEXT: vpmovzxbw %xmm0, %xmm0
; CHECK-NEXT: vpaddw %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpaddw %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i16> @llvm.x86.avx512.mask.pmovzxb.w.128(<16 x i8> %x0, <8 x i16> %x1, i8 %x2) %res = call <8 x i16> @llvm.x86.avx512.mask.pmovzxb.w.128(<16 x i8> %x0, <8 x i16> %x1, i8 %x2)
%res1 = call <8 x i16> @llvm.x86.avx512.mask.pmovzxb.w.128(<16 x i8> %x0, <8 x i16> zeroinitializer, i8 %x2) %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmovzxb.w.128(<16 x i8> %x0, <8 x i16> zeroinitializer, i8 %x2)
Show All 24 Lines
} }
declare <8 x i16> @llvm.x86.avx512.mask.pmovsxb.w.128(<16 x i8>, <8 x i16>, i8) declare <8 x i16> @llvm.x86.avx512.mask.pmovsxb.w.128(<16 x i8>, <8 x i16>, i8)
define <8 x i16>@test_int_x86_avx512_mask_pmovsxb_w_128(<16 x i8> %x0, <8 x i16> %x1, i8 %x2) { define <8 x i16>@test_int_x86_avx512_mask_pmovsxb_w_128(<16 x i8> %x0, <8 x i16> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxb_w_128: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxb_w_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovsxbw %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpmovsxbw %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpmovsxbw %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpmovsxbw %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpmovsxbw %xmm0, %xmm0 ; CHECK-NEXT: vpmovsxbw %xmm0, %xmm0
; CHECK-NEXT: vpaddw %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpaddw %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i16> @llvm.x86.avx512.mask.pmovsxb.w.128(<16 x i8> %x0, <8 x i16> %x1, i8 %x2) %res = call <8 x i16> @llvm.x86.avx512.mask.pmovsxb.w.128(<16 x i8> %x0, <8 x i16> %x1, i8 %x2)
%res1 = call <8 x i16> @llvm.x86.avx512.mask.pmovsxb.w.128(<16 x i8> %x0, <8 x i16> zeroinitializer, i8 %x2) %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmovsxb.w.128(<16 x i8> %x0, <8 x i16> zeroinitializer, i8 %x2)
Show All 23 Lines; CHECK-NEXT: retq
ret <16 x i16> %res4 ret <16 x i16> %res4
} }
declare <2 x i64> @llvm.x86.avx512.mask.pmovsxd.q.128(<4 x i32>, <2 x i64>, i8) declare <2 x i64> @llvm.x86.avx512.mask.pmovsxd.q.128(<4 x i32>, <2 x i64>, i8)
define <2 x i64>@test_int_x86_avx512_mask_pmovsxd_q_128(<4 x i32> %x0, <2 x i64> %x1, i8 %x2) { define <2 x i64>@test_int_x86_avx512_mask_pmovsxd_q_128(<4 x i32> %x0, <2 x i64> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxd_q_128: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxd_q_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovsxdq %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpmovsxdq %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpmovsxdq %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpmovsxdq %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpmovsxdq %xmm0, %xmm0 ; CHECK-NEXT: vpmovsxdq %xmm0, %xmm0
; CHECK-NEXT: vpaddq %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpaddq %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.mask.pmovsxd.q.128(<4 x i32> %x0, <2 x i64> %x1, i8 %x2) %res = call <2 x i64> @llvm.x86.avx512.mask.pmovsxd.q.128(<4 x i32> %x0, <2 x i64> %x1, i8 %x2)
%res1 = call <2 x i64> @llvm.x86.avx512.mask.pmovsxd.q.128(<4 x i32> %x0, <2 x i64> zeroinitializer, i8 %x2) %res1 = call <2 x i64> @llvm.x86.avx512.mask.pmovsxd.q.128(<4 x i32> %x0, <2 x i64> zeroinitializer, i8 %x2)
%res2 = call <2 x i64> @llvm.x86.avx512.mask.pmovsxd.q.128(<4 x i32> %x0, <2 x i64> %x1, i8 -1) %res2 = call <2 x i64> @llvm.x86.avx512.mask.pmovsxd.q.128(<4 x i32> %x0, <2 x i64> %x1, i8 -1)
%res3 = add <2 x i64> %res, %res1 %res3 = add <2 x i64> %res, %res1
%res4 = add <2 x i64> %res3, %res2 %res4 = add <2 x i64> %res3, %res2
ret <2 x i64> %res4 ret <2 x i64> %res4
} }
declare <4 x i64> @llvm.x86.avx512.mask.pmovsxd.q.256(<4 x i32>, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.pmovsxd.q.256(<4 x i32>, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_mask_pmovsxd_q_256(<4 x i32> %x0, <4 x i64> %x1, i8 %x2) { define <4 x i64>@test_int_x86_avx512_mask_pmovsxd_q_256(<4 x i32> %x0, <4 x i64> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxd_q_256: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxd_q_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovsxdq %xmm0, %ymm1 {%k1} ; CHECK-NEXT: vpmovsxdq %xmm0, %ymm1 {%k1}
; CHECK-NEXT: vpmovsxdq %xmm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpmovsxdq %xmm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vpmovsxdq %xmm0, %ymm0 ; CHECK-NEXT: vpmovsxdq %xmm0, %ymm0
; CHECK-NEXT: vpaddq %ymm2, %ymm1, %ymm1 ; CHECK-NEXT: vpaddq %ymm2, %ymm1, %ymm1
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.pmovsxd.q.256(<4 x i32> %x0, <4 x i64> %x1, i8 %x2) %res = call <4 x i64> @llvm.x86.avx512.mask.pmovsxd.q.256(<4 x i32> %x0, <4 x i64> %x1, i8 %x2)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.pmovsxd.q.256(<4 x i32> %x0, <4 x i64> zeroinitializer, i8 %x2) %res1 = call <4 x i64> @llvm.x86.avx512.mask.pmovsxd.q.256(<4 x i32> %x0, <4 x i64> zeroinitializer, i8 %x2)
%res2 = call <4 x i64> @llvm.x86.avx512.mask.pmovsxd.q.256(<4 x i32> %x0, <4 x i64> %x1, i8 -1) %res2 = call <4 x i64> @llvm.x86.avx512.mask.pmovsxd.q.256(<4 x i32> %x0, <4 x i64> %x1, i8 -1)
%res3 = add <4 x i64> %res, %res1 %res3 = add <4 x i64> %res, %res1
%res4 = add <4 x i64> %res3, %res2 %res4 = add <4 x i64> %res3, %res2
ret <4 x i64> %res4 ret <4 x i64> %res4
} }
declare <8 x i16> @llvm.x86.avx512.mask.permvar.hi.128(<8 x i16>, <8 x i16>, <8 x i16>, i8) declare <8 x i16> @llvm.x86.avx512.mask.permvar.hi.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)
define <8 x i16>@test_int_x86_avx512_mask_permvar_hi_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) { define <8 x i16>@test_int_x86_avx512_mask_permvar_hi_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_permvar_hi_128: ; CHECK-LABEL: test_int_x86_avx512_mask_permvar_hi_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpermw %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vpermw %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vpermw %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: vpermw %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: vpermw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpermw %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddw %xmm3, %xmm2, %xmm1 ; CHECK-NEXT: vpaddw %xmm3, %xmm2, %xmm1
; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i16> @llvm.x86.avx512.mask.permvar.hi.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) %res = call <8 x i16> @llvm.x86.avx512.mask.permvar.hi.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3)
%res1 = call <8 x i16> @llvm.x86.avx512.mask.permvar.hi.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> zeroinitializer, i8 %x3) %res1 = call <8 x i16> @llvm.x86.avx512.mask.permvar.hi.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> zeroinitializer, i8 %x3)
Show All 25 Lines

llvm/trunk/test/CodeGen/X86/avx512cdvl-intrinsics.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512cd -mattr=+avx512vl| FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512cd -mattr=+avx512vl| FileCheck %s
declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readonly declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readonly
declare <4 x i32> @llvm.x86.avx512.mask.lzcnt.d.128(<4 x i32>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.lzcnt.d.128(<4 x i32>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_vplzcnt_d_128(<4 x i32> %x0, <4 x i32> %x1, i8 %x2) { define <4 x i32>@test_int_x86_avx512_mask_vplzcnt_d_128(<4 x i32> %x0, <4 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_vplzcnt_d_128: ; CHECK-LABEL: test_int_x86_avx512_mask_vplzcnt_d_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vplzcntd %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vplzcntd %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vplzcntd %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vplzcntd %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vplzcntd %xmm0, %xmm0 ; CHECK-NEXT: vplzcntd %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: vpaddd %xmm2, %xmm0, %xmm0 ; CHECK-NEXT: vpaddd %xmm2, %xmm0, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.lzcnt.d.128(<4 x i32> %x0, <4 x i32> %x1, i8 %x2) %res = call <4 x i32> @llvm.x86.avx512.mask.lzcnt.d.128(<4 x i32> %x0, <4 x i32> %x1, i8 %x2)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.lzcnt.d.128(<4 x i32> %x0, <4 x i32> %x1, i8 -1) %res1 = call <4 x i32> @llvm.x86.avx512.mask.lzcnt.d.128(<4 x i32> %x0, <4 x i32> %x1, i8 -1)
%res3 = call <4 x i32> @llvm.x86.avx512.mask.lzcnt.d.128(<4 x i32> %x0, <4 x i32> zeroinitializer, i8 %x2) %res3 = call <4 x i32> @llvm.x86.avx512.mask.lzcnt.d.128(<4 x i32> %x0, <4 x i32> zeroinitializer, i8 %x2)
%res2 = add <4 x i32> %res, %res1 %res2 = add <4 x i32> %res, %res1
%res4 = add <4 x i32> %res2, %res3 %res4 = add <4 x i32> %res2, %res3
ret <4 x i32> %res4 ret <4 x i32> %res4
} }
declare <8 x i32> @llvm.x86.avx512.mask.lzcnt.d.256(<8 x i32>, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.lzcnt.d.256(<8 x i32>, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_vplzcnt_d_256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2) { define <8 x i32>@test_int_x86_avx512_mask_vplzcnt_d_256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_vplzcnt_d_256: ; CHECK-LABEL: test_int_x86_avx512_mask_vplzcnt_d_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vplzcntd %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vplzcntd %ymm0, %ymm1 {%k1}
; CHECK-NEXT: vplzcntd %ymm0, %ymm0 ; CHECK-NEXT: vplzcntd %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.lzcnt.d.256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2) %res = call <8 x i32> @llvm.x86.avx512.mask.lzcnt.d.256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.lzcnt.d.256(<8 x i32> %x0, <8 x i32> %x1, i8 -1) %res1 = call <8 x i32> @llvm.x86.avx512.mask.lzcnt.d.256(<8 x i32> %x0, <8 x i32> %x1, i8 -1)
%res2 = add <8 x i32> %res, %res1 %res2 = add <8 x i32> %res, %res1
ret <8 x i32> %res2 ret <8 x i32> %res2
} }
declare <2 x i64> @llvm.x86.avx512.mask.lzcnt.q.128(<2 x i64>, <2 x i64>, i8) declare <2 x i64> @llvm.x86.avx512.mask.lzcnt.q.128(<2 x i64>, <2 x i64>, i8)
define <2 x i64>@test_int_x86_avx512_mask_vplzcnt_q_128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2) { define <2 x i64>@test_int_x86_avx512_mask_vplzcnt_q_128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_vplzcnt_q_128: ; CHECK-LABEL: test_int_x86_avx512_mask_vplzcnt_q_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vplzcntq %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vplzcntq %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vplzcntq %xmm0, %xmm0 ; CHECK-NEXT: vplzcntq %xmm0, %xmm0
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.mask.lzcnt.q.128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2) %res = call <2 x i64> @llvm.x86.avx512.mask.lzcnt.q.128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2)
%res1 = call <2 x i64> @llvm.x86.avx512.mask.lzcnt.q.128(<2 x i64> %x0, <2 x i64> %x1, i8 -1) %res1 = call <2 x i64> @llvm.x86.avx512.mask.lzcnt.q.128(<2 x i64> %x0, <2 x i64> %x1, i8 -1)
%res2 = add <2 x i64> %res, %res1 %res2 = add <2 x i64> %res, %res1
ret <2 x i64> %res2 ret <2 x i64> %res2
} }
declare <4 x i64> @llvm.x86.avx512.mask.lzcnt.q.256(<4 x i64>, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.lzcnt.q.256(<4 x i64>, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_mask_vplzcnt_q_256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2) { define <4 x i64>@test_int_x86_avx512_mask_vplzcnt_q_256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_vplzcnt_q_256: ; CHECK-LABEL: test_int_x86_avx512_mask_vplzcnt_q_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vplzcntq %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vplzcntq %ymm0, %ymm1 {%k1}
; CHECK-NEXT: vplzcntq %ymm0, %ymm0 ; CHECK-NEXT: vplzcntq %ymm0, %ymm0
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.lzcnt.q.256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2) %res = call <4 x i64> @llvm.x86.avx512.mask.lzcnt.q.256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.lzcnt.q.256(<4 x i64> %x0, <4 x i64> %x1, i8 -1) %res1 = call <4 x i64> @llvm.x86.avx512.mask.lzcnt.q.256(<4 x i64> %x0, <4 x i64> %x1, i8 -1)
%res2 = add <4 x i64> %res, %res1 %res2 = add <4 x i64> %res, %res1
ret <4 x i64> %res2 ret <4 x i64> %res2
} }
declare <4 x i32> @llvm.x86.avx512.mask.conflict.d.128(<4 x i32>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.conflict.d.128(<4 x i32>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_vpconflict_d_128(<4 x i32> %x0, <4 x i32> %x1, i8 %x2) { define <4 x i32>@test_int_x86_avx512_mask_vpconflict_d_128(<4 x i32> %x0, <4 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_vpconflict_d_128: ; CHECK-LABEL: test_int_x86_avx512_mask_vpconflict_d_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpconflictd %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpconflictd %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpconflictd %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpconflictd %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpconflictd %xmm0, %xmm0 ; CHECK-NEXT: vpconflictd %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: vpaddd %xmm2, %xmm0, %xmm0 ; CHECK-NEXT: vpaddd %xmm2, %xmm0, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.conflict.d.128(<4 x i32> %x0, <4 x i32> %x1, i8 %x2) %res = call <4 x i32> @llvm.x86.avx512.mask.conflict.d.128(<4 x i32> %x0, <4 x i32> %x1, i8 %x2)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.conflict.d.128(<4 x i32> %x0, <4 x i32> %x1, i8 -1) %res1 = call <4 x i32> @llvm.x86.avx512.mask.conflict.d.128(<4 x i32> %x0, <4 x i32> %x1, i8 -1)
%res3 = call <4 x i32> @llvm.x86.avx512.mask.conflict.d.128(<4 x i32> %x0, <4 x i32> zeroinitializer, i8 %x2) %res3 = call <4 x i32> @llvm.x86.avx512.mask.conflict.d.128(<4 x i32> %x0, <4 x i32> zeroinitializer, i8 %x2)
%res2 = add <4 x i32> %res, %res1 %res2 = add <4 x i32> %res, %res1
%res4 = add <4 x i32> %res2, %res3 %res4 = add <4 x i32> %res2, %res3
ret <4 x i32> %res4 ret <4 x i32> %res4
} }
declare <8 x i32> @llvm.x86.avx512.mask.conflict.d.256(<8 x i32>, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.conflict.d.256(<8 x i32>, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_vpconflict_d_256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2) { define <8 x i32>@test_int_x86_avx512_mask_vpconflict_d_256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_vpconflict_d_256: ; CHECK-LABEL: test_int_x86_avx512_mask_vpconflict_d_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpconflictd %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vpconflictd %ymm0, %ymm1 {%k1}
; CHECK-NEXT: vpconflictd %ymm0, %ymm0 ; CHECK-NEXT: vpconflictd %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.conflict.d.256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2) %res = call <8 x i32> @llvm.x86.avx512.mask.conflict.d.256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.conflict.d.256(<8 x i32> %x0, <8 x i32> %x1, i8 -1) %res1 = call <8 x i32> @llvm.x86.avx512.mask.conflict.d.256(<8 x i32> %x0, <8 x i32> %x1, i8 -1)
%res2 = add <8 x i32> %res, %res1 %res2 = add <8 x i32> %res, %res1
ret <8 x i32> %res2 ret <8 x i32> %res2
} }
declare <2 x i64> @llvm.x86.avx512.mask.conflict.q.128(<2 x i64>, <2 x i64>, i8) declare <2 x i64> @llvm.x86.avx512.mask.conflict.q.128(<2 x i64>, <2 x i64>, i8)
define <2 x i64>@test_int_x86_avx512_mask_vpconflict_q_128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2) { define <2 x i64>@test_int_x86_avx512_mask_vpconflict_q_128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_vpconflict_q_128: ; CHECK-LABEL: test_int_x86_avx512_mask_vpconflict_q_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpconflictq %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpconflictq %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpconflictq %xmm0, %xmm0 ; CHECK-NEXT: vpconflictq %xmm0, %xmm0
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.mask.conflict.q.128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2) %res = call <2 x i64> @llvm.x86.avx512.mask.conflict.q.128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2)
%res1 = call <2 x i64> @llvm.x86.avx512.mask.conflict.q.128(<2 x i64> %x0, <2 x i64> %x1, i8 -1) %res1 = call <2 x i64> @llvm.x86.avx512.mask.conflict.q.128(<2 x i64> %x0, <2 x i64> %x1, i8 -1)
%res2 = add <2 x i64> %res, %res1 %res2 = add <2 x i64> %res, %res1
ret <2 x i64> %res2 ret <2 x i64> %res2
} }
declare <4 x i64> @llvm.x86.avx512.mask.conflict.q.256(<4 x i64>, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.conflict.q.256(<4 x i64>, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_mask_vpconflict_q_256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2) { define <4 x i64>@test_int_x86_avx512_mask_vpconflict_q_256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_vpconflict_q_256: ; CHECK-LABEL: test_int_x86_avx512_mask_vpconflict_q_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpconflictq %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vpconflictq %ymm0, %ymm1 {%k1}
; CHECK-NEXT: vpconflictq %ymm0, %ymm0 ; CHECK-NEXT: vpconflictq %ymm0, %ymm0
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.conflict.q.256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2) %res = call <4 x i64> @llvm.x86.avx512.mask.conflict.q.256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.conflict.q.256(<4 x i64> %x0, <4 x i64> %x1, i8 -1) %res1 = call <4 x i64> @llvm.x86.avx512.mask.conflict.q.256(<4 x i64> %x0, <4 x i64> %x1, i8 -1)
%res2 = add <4 x i64> %res, %res1 %res2 = add <4 x i64> %res, %res1
ret <4 x i64> %res2 ret <4 x i64> %res2
} }
define <8 x i32> @test_x86_vbroadcastmw_256(i16 %a0) { define <8 x i32> @test_x86_vbroadcastmw_256(i16 %a0) {
; CHECK: test_x86_vbroadcastmw_256 ; CHECK-LABEL: test_x86_vbroadcastmw_256:
; CHECK: vpbroadcastmw2d %k0, %ymm0 ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k0
; CHECK-NEXT: vpbroadcastmw2d %k0, %ymm0
; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.broadcastmw.256(i16 %a0) ; %res = call <8 x i32> @llvm.x86.avx512.broadcastmw.256(i16 %a0) ;
ret <8 x i32> %res ret <8 x i32> %res
} }
declare <8 x i32> @llvm.x86.avx512.broadcastmw.256(i16) declare <8 x i32> @llvm.x86.avx512.broadcastmw.256(i16)
define <4 x i32> @test_x86_vbroadcastmw_128(i16 %a0) { define <4 x i32> @test_x86_vbroadcastmw_128(i16 %a0) {
; CHECK: test_x86_vbroadcastmw_128 ; CHECK-LABEL: test_x86_vbroadcastmw_128:
; CHECK: vpbroadcastmw2d %k0, %xmm0 ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k0
; CHECK-NEXT: vpbroadcastmw2d %k0, %xmm0
; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.broadcastmw.128(i16 %a0) ; %res = call <4 x i32> @llvm.x86.avx512.broadcastmw.128(i16 %a0) ;
ret <4 x i32> %res ret <4 x i32> %res
} }
declare <4 x i32> @llvm.x86.avx512.broadcastmw.128(i16) declare <4 x i32> @llvm.x86.avx512.broadcastmw.128(i16)
define <4 x i64> @test_x86_broadcastmb_256(i8 %a0) { define <4 x i64> @test_x86_broadcastmb_256(i8 %a0) {
; CHECK: test_x86_broadcastmb_256 ; CHECK-LABEL: test_x86_broadcastmb_256:
; CHECK: vpbroadcastmb2q %k0, %ymm0 ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k0
; CHECK-NEXT: vpbroadcastmb2q %k0, %ymm0
; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.broadcastmb.256(i8 %a0) ; %res = call <4 x i64> @llvm.x86.avx512.broadcastmb.256(i8 %a0) ;
ret <4 x i64> %res ret <4 x i64> %res
} }
declare <4 x i64> @llvm.x86.avx512.broadcastmb.256(i8) declare <4 x i64> @llvm.x86.avx512.broadcastmb.256(i8)
define <2 x i64> @test_x86_broadcastmb_128(i8 %a0) { define <2 x i64> @test_x86_broadcastmb_128(i8 %a0) {
; CHECK: test_x86_broadcastmb_128 ; CHECK-LABEL: test_x86_broadcastmb_128:
; CHECK: vpbroadcastmb2q %k0, %xmm0 ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k0
; CHECK-NEXT: vpbroadcastmb2q %k0, %xmm0
; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.broadcastmb.128(i8 %a0) ; %res = call <2 x i64> @llvm.x86.avx512.broadcastmb.128(i8 %a0) ;
ret <2 x i64> %res ret <2 x i64> %res
} }
declare <2 x i64> @llvm.x86.avx512.broadcastmb.128(i8) declare <2 x i64> @llvm.x86.avx512.broadcastmb.128(i8)

llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll

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Show First 20 Lines • Show All 4,010 Lines • ▼ Show 20 Lines; CHECK: vpmovusdw %ymm0, (%rdi) {%k1}
ret void ret void
} }
declare <2 x double> @llvm.x86.avx512.mask.cvtdq2pd.128(<4 x i32>, <2 x double>, i8) declare <2 x double> @llvm.x86.avx512.mask.cvtdq2pd.128(<4 x i32>, <2 x double>, i8)
define <2 x double>@test_int_x86_avx512_mask_cvt_dq2pd_128(<4 x i32> %x0, <2 x double> %x1, i8 %x2) { define <2 x double>@test_int_x86_avx512_mask_cvt_dq2pd_128(<4 x i32> %x0, <2 x double> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_dq2pd_128: ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_dq2pd_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvtdq2pd %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vcvtdq2pd %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vcvtdq2pd %xmm0, %xmm0 ; CHECK-NEXT: vcvtdq2pd %xmm0, %xmm0
; CHECK-NEXT: vaddpd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vaddpd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.cvtdq2pd.128(<4 x i32> %x0, <2 x double> %x1, i8 %x2) %res = call <2 x double> @llvm.x86.avx512.mask.cvtdq2pd.128(<4 x i32> %x0, <2 x double> %x1, i8 %x2)
%res1 = call <2 x double> @llvm.x86.avx512.mask.cvtdq2pd.128(<4 x i32> %x0, <2 x double> %x1, i8 -1) %res1 = call <2 x double> @llvm.x86.avx512.mask.cvtdq2pd.128(<4 x i32> %x0, <2 x double> %x1, i8 -1)
%res2 = fadd <2 x double> %res, %res1 %res2 = fadd <2 x double> %res, %res1
ret <2 x double> %res2 ret <2 x double> %res2
} }
declare <4 x double> @llvm.x86.avx512.mask.cvtdq2pd.256(<4 x i32>, <4 x double>, i8) declare <4 x double> @llvm.x86.avx512.mask.cvtdq2pd.256(<4 x i32>, <4 x double>, i8)
define <4 x double>@test_int_x86_avx512_mask_cvt_dq2pd_256(<4 x i32> %x0, <4 x double> %x1, i8 %x2) { define <4 x double>@test_int_x86_avx512_mask_cvt_dq2pd_256(<4 x i32> %x0, <4 x double> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_dq2pd_256: ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_dq2pd_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvtdq2pd %xmm0, %ymm1 {%k1} ; CHECK-NEXT: vcvtdq2pd %xmm0, %ymm1 {%k1}
; CHECK-NEXT: vcvtdq2pd %xmm0, %ymm0 ; CHECK-NEXT: vcvtdq2pd %xmm0, %ymm0
; CHECK-NEXT: vaddpd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vaddpd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x double> @llvm.x86.avx512.mask.cvtdq2pd.256(<4 x i32> %x0, <4 x double> %x1, i8 %x2) %res = call <4 x double> @llvm.x86.avx512.mask.cvtdq2pd.256(<4 x i32> %x0, <4 x double> %x1, i8 %x2)
%res1 = call <4 x double> @llvm.x86.avx512.mask.cvtdq2pd.256(<4 x i32> %x0, <4 x double> %x1, i8 -1) %res1 = call <4 x double> @llvm.x86.avx512.mask.cvtdq2pd.256(<4 x i32> %x0, <4 x double> %x1, i8 -1)
%res2 = fadd <4 x double> %res, %res1 %res2 = fadd <4 x double> %res, %res1
ret <4 x double> %res2 ret <4 x double> %res2
} }
declare <4 x float> @llvm.x86.avx512.mask.cvtdq2ps.128(<4 x i32>, <4 x float>, i8) declare <4 x float> @llvm.x86.avx512.mask.cvtdq2ps.128(<4 x i32>, <4 x float>, i8)
define <4 x float>@test_int_x86_avx512_mask_cvt_dq2ps_128(<4 x i32> %x0, <4 x float> %x1, i8 %x2) { define <4 x float>@test_int_x86_avx512_mask_cvt_dq2ps_128(<4 x i32> %x0, <4 x float> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_dq2ps_128: ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_dq2ps_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm0 ; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm0
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.cvtdq2ps.128(<4 x i32> %x0, <4 x float> %x1, i8 %x2) %res = call <4 x float> @llvm.x86.avx512.mask.cvtdq2ps.128(<4 x i32> %x0, <4 x float> %x1, i8 %x2)
%res1 = call <4 x float> @llvm.x86.avx512.mask.cvtdq2ps.128(<4 x i32> %x0, <4 x float> %x1, i8 -1) %res1 = call <4 x float> @llvm.x86.avx512.mask.cvtdq2ps.128(<4 x i32> %x0, <4 x float> %x1, i8 -1)
%res2 = fadd <4 x float> %res, %res1 %res2 = fadd <4 x float> %res, %res1
ret <4 x float> %res2 ret <4 x float> %res2
} }
declare <8 x float> @llvm.x86.avx512.mask.cvtdq2ps.256(<8 x i32>, <8 x float>, i8) declare <8 x float> @llvm.x86.avx512.mask.cvtdq2ps.256(<8 x i32>, <8 x float>, i8)
define <8 x float>@test_int_x86_avx512_mask_cvt_dq2ps_256(<8 x i32> %x0, <8 x float> %x1, i8 %x2) { define <8 x float>@test_int_x86_avx512_mask_cvt_dq2ps_256(<8 x i32> %x0, <8 x float> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_dq2ps_256: ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_dq2ps_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvtdq2ps %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vcvtdq2ps %ymm0, %ymm1 {%k1}
; CHECK-NEXT: vcvtdq2ps %ymm0, %ymm0 ; CHECK-NEXT: vcvtdq2ps %ymm0, %ymm0
; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx512.mask.cvtdq2ps.256(<8 x i32> %x0, <8 x float> %x1, i8 %x2) %res = call <8 x float> @llvm.x86.avx512.mask.cvtdq2ps.256(<8 x i32> %x0, <8 x float> %x1, i8 %x2)
%res1 = call <8 x float> @llvm.x86.avx512.mask.cvtdq2ps.256(<8 x i32> %x0, <8 x float> %x1, i8 -1) %res1 = call <8 x float> @llvm.x86.avx512.mask.cvtdq2ps.256(<8 x i32> %x0, <8 x float> %x1, i8 -1)
%res2 = fadd <8 x float> %res, %res1 %res2 = fadd <8 x float> %res, %res1
ret <8 x float> %res2 ret <8 x float> %res2
} }
declare <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.128(<2 x double>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.128(<2 x double>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_cvt_pd2dq_128(<2 x double> %x0, <4 x i32> %x1, i8 %x2) { define <4 x i32>@test_int_x86_avx512_mask_cvt_pd2dq_128(<2 x double> %x0, <4 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2dq_128: ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2dq_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvtpd2dq %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vcvtpd2dq %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vcvtpd2dq %xmm0, %xmm0 ; CHECK-NEXT: vcvtpd2dq %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.128(<2 x double> %x0, <4 x i32> %x1, i8 %x2) %res = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.128(<2 x double> %x0, <4 x i32> %x1, i8 %x2)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.128(<2 x double> %x0, <4 x i32> %x1, i8 -1) %res1 = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.128(<2 x double> %x0, <4 x i32> %x1, i8 -1)
%res2 = add <4 x i32> %res, %res1 %res2 = add <4 x i32> %res, %res1
ret <4 x i32> %res2 ret <4 x i32> %res2
} }
declare <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.256(<4 x double>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.256(<4 x double>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_cvt_pd2dq_256(<4 x double> %x0, <4 x i32> %x1, i8 %x2) { define <4 x i32>@test_int_x86_avx512_mask_cvt_pd2dq_256(<4 x double> %x0, <4 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2dq_256: ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2dq_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvtpd2dq %ymm0, %xmm1 {%k1} ; CHECK-NEXT: vcvtpd2dq %ymm0, %xmm1 {%k1}
; CHECK-NEXT: vcvtpd2dq %ymm0, %xmm0 ; CHECK-NEXT: vcvtpd2dq %ymm0, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.256(<4 x double> %x0, <4 x i32> %x1, i8 %x2) %res = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.256(<4 x double> %x0, <4 x i32> %x1, i8 %x2)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.256(<4 x double> %x0, <4 x i32> %x1, i8 -1) %res1 = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.256(<4 x double> %x0, <4 x i32> %x1, i8 -1)
%res2 = add <4 x i32> %res, %res1 %res2 = add <4 x i32> %res, %res1
ret <4 x i32> %res2 ret <4 x i32> %res2
} }
declare <4 x float> @llvm.x86.avx512.mask.cvtpd2ps.256(<4 x double>, <4 x float>, i8) declare <4 x float> @llvm.x86.avx512.mask.cvtpd2ps.256(<4 x double>, <4 x float>, i8)
define <4 x float>@test_int_x86_avx512_mask_cvt_pd2ps_256(<4 x double> %x0, <4 x float> %x1, i8 %x2) { define <4 x float>@test_int_x86_avx512_mask_cvt_pd2ps_256(<4 x double> %x0, <4 x float> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2ps_256: ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2ps_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvtpd2ps %ymm0, %xmm1 {%k1} ; CHECK-NEXT: vcvtpd2ps %ymm0, %xmm1 {%k1}
; CHECK-NEXT: vcvtpd2ps %ymm0, %xmm0 ; CHECK-NEXT: vcvtpd2ps %ymm0, %xmm0
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.cvtpd2ps.256(<4 x double> %x0, <4 x float> %x1, i8 %x2) %res = call <4 x float> @llvm.x86.avx512.mask.cvtpd2ps.256(<4 x double> %x0, <4 x float> %x1, i8 %x2)
%res1 = call <4 x float> @llvm.x86.avx512.mask.cvtpd2ps.256(<4 x double> %x0, <4 x float> %x1, i8 -1) %res1 = call <4 x float> @llvm.x86.avx512.mask.cvtpd2ps.256(<4 x double> %x0, <4 x float> %x1, i8 -1)
%res2 = fadd <4 x float> %res, %res1 %res2 = fadd <4 x float> %res, %res1
ret <4 x float> %res2 ret <4 x float> %res2
} }
declare <4 x float> @llvm.x86.avx512.mask.cvtpd2ps(<2 x double>, <4 x float>, i8) declare <4 x float> @llvm.x86.avx512.mask.cvtpd2ps(<2 x double>, <4 x float>, i8)
define <4 x float>@test_int_x86_avx512_mask_cvt_pd2ps(<2 x double> %x0, <4 x float> %x1, i8 %x2) { define <4 x float>@test_int_x86_avx512_mask_cvt_pd2ps(<2 x double> %x0, <4 x float> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2ps: ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2ps:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvtpd2ps %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vcvtpd2ps %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vcvtpd2ps %xmm0, %xmm0 ; CHECK-NEXT: vcvtpd2ps %xmm0, %xmm0
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.cvtpd2ps(<2 x double> %x0, <4 x float> %x1, i8 %x2) %res = call <4 x float> @llvm.x86.avx512.mask.cvtpd2ps(<2 x double> %x0, <4 x float> %x1, i8 %x2)
%res1 = call <4 x float> @llvm.x86.avx512.mask.cvtpd2ps(<2 x double> %x0, <4 x float> %x1, i8 -1) %res1 = call <4 x float> @llvm.x86.avx512.mask.cvtpd2ps(<2 x double> %x0, <4 x float> %x1, i8 -1)
%res2 = fadd <4 x float> %res, %res1 %res2 = fadd <4 x float> %res, %res1
ret <4 x float> %res2 ret <4 x float> %res2
} }
declare <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.128(<2 x double>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.128(<2 x double>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_cvt_pd2udq_128(<2 x double> %x0, <4 x i32> %x1, i8 %x2) { define <4 x i32>@test_int_x86_avx512_mask_cvt_pd2udq_128(<2 x double> %x0, <4 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2udq_128: ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2udq_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvtpd2udq %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vcvtpd2udq %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vcvtpd2udq %xmm0, %xmm0 ; CHECK-NEXT: vcvtpd2udq %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.128(<2 x double> %x0, <4 x i32> %x1, i8 %x2) %res = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.128(<2 x double> %x0, <4 x i32> %x1, i8 %x2)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.128(<2 x double> %x0, <4 x i32> %x1, i8 -1) %res1 = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.128(<2 x double> %x0, <4 x i32> %x1, i8 -1)
%res2 = add <4 x i32> %res, %res1 %res2 = add <4 x i32> %res, %res1
ret <4 x i32> %res2 ret <4 x i32> %res2
} }
declare <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.256(<4 x double>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.256(<4 x double>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_cvt_pd2udq_256(<4 x double> %x0, <4 x i32> %x1, i8 %x2) { define <4 x i32>@test_int_x86_avx512_mask_cvt_pd2udq_256(<4 x double> %x0, <4 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2udq_256: ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2udq_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvtpd2udq %ymm0, %xmm1 {%k1} ; CHECK-NEXT: vcvtpd2udq %ymm0, %xmm1 {%k1}
; CHECK-NEXT: vcvtpd2udq %ymm0, %xmm0 ; CHECK-NEXT: vcvtpd2udq %ymm0, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.256(<4 x double> %x0, <4 x i32> %x1, i8 %x2) %res = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.256(<4 x double> %x0, <4 x i32> %x1, i8 %x2)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.256(<4 x double> %x0, <4 x i32> %x1, i8 -1) %res1 = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.256(<4 x double> %x0, <4 x i32> %x1, i8 -1)
%res2 = add <4 x i32> %res, %res1 %res2 = add <4 x i32> %res, %res1
ret <4 x i32> %res2 ret <4 x i32> %res2
} }
declare <4 x i32> @llvm.x86.avx512.mask.cvtps2dq.128(<4 x float>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.cvtps2dq.128(<4 x float>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_cvt_ps2dq_128(<4 x float> %x0, <4 x i32> %x1, i8 %x2) { define <4 x i32>@test_int_x86_avx512_mask_cvt_ps2dq_128(<4 x float> %x0, <4 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2dq_128: ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2dq_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvtps2dq %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vcvtps2dq %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vcvtps2dq %xmm0, %xmm0 ; CHECK-NEXT: vcvtps2dq %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.cvtps2dq.128(<4 x float> %x0, <4 x i32> %x1, i8 %x2) %res = call <4 x i32> @llvm.x86.avx512.mask.cvtps2dq.128(<4 x float> %x0, <4 x i32> %x1, i8 %x2)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvtps2dq.128(<4 x float> %x0, <4 x i32> %x1, i8 -1) %res1 = call <4 x i32> @llvm.x86.avx512.mask.cvtps2dq.128(<4 x float> %x0, <4 x i32> %x1, i8 -1)
%res2 = add <4 x i32> %res, %res1 %res2 = add <4 x i32> %res, %res1
ret <4 x i32> %res2 ret <4 x i32> %res2
} }
declare <8 x i32> @llvm.x86.avx512.mask.cvtps2dq.256(<8 x float>, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.cvtps2dq.256(<8 x float>, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_cvt_ps2dq_256(<8 x float> %x0, <8 x i32> %x1, i8 %x2) { define <8 x i32>@test_int_x86_avx512_mask_cvt_ps2dq_256(<8 x float> %x0, <8 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2dq_256: ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2dq_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvtps2dq %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vcvtps2dq %ymm0, %ymm1 {%k1}
; CHECK-NEXT: vcvtps2dq %ymm0, %ymm0 ; CHECK-NEXT: vcvtps2dq %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.cvtps2dq.256(<8 x float> %x0, <8 x i32> %x1, i8 %x2) %res = call <8 x i32> @llvm.x86.avx512.mask.cvtps2dq.256(<8 x float> %x0, <8 x i32> %x1, i8 %x2)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.cvtps2dq.256(<8 x float> %x0, <8 x i32> %x1, i8 -1) %res1 = call <8 x i32> @llvm.x86.avx512.mask.cvtps2dq.256(<8 x float> %x0, <8 x i32> %x1, i8 -1)
%res2 = add <8 x i32> %res, %res1 %res2 = add <8 x i32> %res, %res1
ret <8 x i32> %res2 ret <8 x i32> %res2
} }
declare <2 x double> @llvm.x86.avx512.mask.cvtps2pd.128(<4 x float>, <2 x double>, i8) declare <2 x double> @llvm.x86.avx512.mask.cvtps2pd.128(<4 x float>, <2 x double>, i8)
define <2 x double>@test_int_x86_avx512_mask_cvt_ps2pd_128(<4 x float> %x0, <2 x double> %x1, i8 %x2) { define <2 x double>@test_int_x86_avx512_mask_cvt_ps2pd_128(<4 x float> %x0, <2 x double> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2pd_128: ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2pd_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvtps2pd %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vcvtps2pd %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vcvtps2pd %xmm0, %xmm0 ; CHECK-NEXT: vcvtps2pd %xmm0, %xmm0
; CHECK-NEXT: vaddpd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vaddpd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.cvtps2pd.128(<4 x float> %x0, <2 x double> %x1, i8 %x2) %res = call <2 x double> @llvm.x86.avx512.mask.cvtps2pd.128(<4 x float> %x0, <2 x double> %x1, i8 %x2)
%res1 = call <2 x double> @llvm.x86.avx512.mask.cvtps2pd.128(<4 x float> %x0, <2 x double> %x1, i8 -1) %res1 = call <2 x double> @llvm.x86.avx512.mask.cvtps2pd.128(<4 x float> %x0, <2 x double> %x1, i8 -1)
%res2 = fadd <2 x double> %res, %res1 %res2 = fadd <2 x double> %res, %res1
ret <2 x double> %res2 ret <2 x double> %res2
} }
declare <4 x double> @llvm.x86.avx512.mask.cvtps2pd.256(<4 x float>, <4 x double>, i8) declare <4 x double> @llvm.x86.avx512.mask.cvtps2pd.256(<4 x float>, <4 x double>, i8)
define <4 x double>@test_int_x86_avx512_mask_cvt_ps2pd_256(<4 x float> %x0, <4 x double> %x1, i8 %x2) { define <4 x double>@test_int_x86_avx512_mask_cvt_ps2pd_256(<4 x float> %x0, <4 x double> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2pd_256: ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2pd_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvtps2pd %xmm0, %ymm1 {%k1} ; CHECK-NEXT: vcvtps2pd %xmm0, %ymm1 {%k1}
; CHECK-NEXT: vcvtps2pd %xmm0, %ymm0 ; CHECK-NEXT: vcvtps2pd %xmm0, %ymm0
; CHECK-NEXT: vaddpd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vaddpd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x double> @llvm.x86.avx512.mask.cvtps2pd.256(<4 x float> %x0, <4 x double> %x1, i8 %x2) %res = call <4 x double> @llvm.x86.avx512.mask.cvtps2pd.256(<4 x float> %x0, <4 x double> %x1, i8 %x2)
%res1 = call <4 x double> @llvm.x86.avx512.mask.cvtps2pd.256(<4 x float> %x0, <4 x double> %x1, i8 -1) %res1 = call <4 x double> @llvm.x86.avx512.mask.cvtps2pd.256(<4 x float> %x0, <4 x double> %x1, i8 -1)
%res2 = fadd <4 x double> %res, %res1 %res2 = fadd <4 x double> %res, %res1
ret <4 x double> %res2 ret <4 x double> %res2
} }
declare <4 x i32> @llvm.x86.avx512.mask.cvtps2udq.128(<4 x float>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.cvtps2udq.128(<4 x float>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_cvt_ps2udq_128(<4 x float> %x0, <4 x i32> %x1, i8 %x2) { define <4 x i32>@test_int_x86_avx512_mask_cvt_ps2udq_128(<4 x float> %x0, <4 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2udq_128: ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2udq_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvtps2udq %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vcvtps2udq %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vcvtps2udq %xmm0, %xmm0 ; CHECK-NEXT: vcvtps2udq %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.cvtps2udq.128(<4 x float> %x0, <4 x i32> %x1, i8 %x2) %res = call <4 x i32> @llvm.x86.avx512.mask.cvtps2udq.128(<4 x float> %x0, <4 x i32> %x1, i8 %x2)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvtps2udq.128(<4 x float> %x0, <4 x i32> %x1, i8 -1) %res1 = call <4 x i32> @llvm.x86.avx512.mask.cvtps2udq.128(<4 x float> %x0, <4 x i32> %x1, i8 -1)
%res2 = add <4 x i32> %res, %res1 %res2 = add <4 x i32> %res, %res1
ret <4 x i32> %res2 ret <4 x i32> %res2
} }
declare <8 x i32> @llvm.x86.avx512.mask.cvtps2udq.256(<8 x float>, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.cvtps2udq.256(<8 x float>, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_cvt_ps2udq_256(<8 x float> %x0, <8 x i32> %x1, i8 %x2) { define <8 x i32>@test_int_x86_avx512_mask_cvt_ps2udq_256(<8 x float> %x0, <8 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2udq_256: ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2udq_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvtps2udq %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vcvtps2udq %ymm0, %ymm1 {%k1}
; CHECK-NEXT: vcvtps2udq %ymm0, %ymm0 ; CHECK-NEXT: vcvtps2udq %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.cvtps2udq.256(<8 x float> %x0, <8 x i32> %x1, i8 %x2) %res = call <8 x i32> @llvm.x86.avx512.mask.cvtps2udq.256(<8 x float> %x0, <8 x i32> %x1, i8 %x2)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.cvtps2udq.256(<8 x float> %x0, <8 x i32> %x1, i8 -1) %res1 = call <8 x i32> @llvm.x86.avx512.mask.cvtps2udq.256(<8 x float> %x0, <8 x i32> %x1, i8 -1)
%res2 = add <8 x i32> %res, %res1 %res2 = add <8 x i32> %res, %res1
ret <8 x i32> %res2 ret <8 x i32> %res2
} }
declare <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.128(<2 x double>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.128(<2 x double>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_cvtt_pd2dq_128(<2 x double> %x0, <4 x i32> %x1, i8 %x2) { define <4 x i32>@test_int_x86_avx512_mask_cvtt_pd2dq_128(<2 x double> %x0, <4 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2dq_128: ; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2dq_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvttpd2dq %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vcvttpd2dq %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vcvttpd2dq %xmm0, %xmm0 ; CHECK-NEXT: vcvttpd2dq %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.128(<2 x double> %x0, <4 x i32> %x1, i8 %x2) %res = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.128(<2 x double> %x0, <4 x i32> %x1, i8 %x2)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.128(<2 x double> %x0, <4 x i32> %x1, i8 -1) %res1 = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.128(<2 x double> %x0, <4 x i32> %x1, i8 -1)
%res2 = add <4 x i32> %res, %res1 %res2 = add <4 x i32> %res, %res1
ret <4 x i32> %res2 ret <4 x i32> %res2
} }
declare <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.256(<4 x double>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.256(<4 x double>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_cvtt_pd2dq_256(<4 x double> %x0, <4 x i32> %x1, i8 %x2) { define <4 x i32>@test_int_x86_avx512_mask_cvtt_pd2dq_256(<4 x double> %x0, <4 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2dq_256: ; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2dq_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvttpd2dq %ymm0, %xmm1 {%k1} ; CHECK-NEXT: vcvttpd2dq %ymm0, %xmm1 {%k1}
; CHECK-NEXT: vcvttpd2dq %ymm0, %xmm0 ; CHECK-NEXT: vcvttpd2dq %ymm0, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.256(<4 x double> %x0, <4 x i32> %x1, i8 %x2) %res = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.256(<4 x double> %x0, <4 x i32> %x1, i8 %x2)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.256(<4 x double> %x0, <4 x i32> %x1, i8 -1) %res1 = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.256(<4 x double> %x0, <4 x i32> %x1, i8 -1)
%res2 = add <4 x i32> %res, %res1 %res2 = add <4 x i32> %res, %res1
ret <4 x i32> %res2 ret <4 x i32> %res2
} }
declare <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.128(<2 x double>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.128(<2 x double>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_cvtt_pd2udq_128(<2 x double> %x0, <4 x i32> %x1, i8 %x2) { define <4 x i32>@test_int_x86_avx512_mask_cvtt_pd2udq_128(<2 x double> %x0, <4 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2udq_128: ; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2udq_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvttpd2udq %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vcvttpd2udq %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vcvttpd2udq %xmm0, %xmm0 ; CHECK-NEXT: vcvttpd2udq %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.128(<2 x double> %x0, <4 x i32> %x1, i8 %x2) %res = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.128(<2 x double> %x0, <4 x i32> %x1, i8 %x2)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.128(<2 x double> %x0, <4 x i32> %x1, i8 -1) %res1 = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.128(<2 x double> %x0, <4 x i32> %x1, i8 -1)
%res2 = add <4 x i32> %res, %res1 %res2 = add <4 x i32> %res, %res1
ret <4 x i32> %res2 ret <4 x i32> %res2
} }
declare <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.256(<4 x double>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.256(<4 x double>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_cvtt_pd2udq_256(<4 x double> %x0, <4 x i32> %x1, i8 %x2) { define <4 x i32>@test_int_x86_avx512_mask_cvtt_pd2udq_256(<4 x double> %x0, <4 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2udq_256: ; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2udq_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvttpd2udq %ymm0, %xmm1 {%k1} ; CHECK-NEXT: vcvttpd2udq %ymm0, %xmm1 {%k1}
; CHECK-NEXT: vcvttpd2udq %ymm0, %xmm0 ; CHECK-NEXT: vcvttpd2udq %ymm0, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.256(<4 x double> %x0, <4 x i32> %x1, i8 %x2) %res = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.256(<4 x double> %x0, <4 x i32> %x1, i8 %x2)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.256(<4 x double> %x0, <4 x i32> %x1, i8 -1) %res1 = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.256(<4 x double> %x0, <4 x i32> %x1, i8 -1)
%res2 = add <4 x i32> %res, %res1 %res2 = add <4 x i32> %res, %res1
ret <4 x i32> %res2 ret <4 x i32> %res2
} }
declare <4 x i32> @llvm.x86.avx512.mask.cvttps2dq.128(<4 x float>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.cvttps2dq.128(<4 x float>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_cvtt_ps2dq_128(<4 x float> %x0, <4 x i32> %x1, i8 %x2) { define <4 x i32>@test_int_x86_avx512_mask_cvtt_ps2dq_128(<4 x float> %x0, <4 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_ps2dq_128: ; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_ps2dq_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvttps2dq %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vcvttps2dq %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vcvttps2dq %xmm0, %xmm0 ; CHECK-NEXT: vcvttps2dq %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.cvttps2dq.128(<4 x float> %x0, <4 x i32> %x1, i8 %x2) %res = call <4 x i32> @llvm.x86.avx512.mask.cvttps2dq.128(<4 x float> %x0, <4 x i32> %x1, i8 %x2)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvttps2dq.128(<4 x float> %x0, <4 x i32> %x1, i8 -1) %res1 = call <4 x i32> @llvm.x86.avx512.mask.cvttps2dq.128(<4 x float> %x0, <4 x i32> %x1, i8 -1)
%res2 = add <4 x i32> %res, %res1 %res2 = add <4 x i32> %res, %res1
ret <4 x i32> %res2 ret <4 x i32> %res2
} }
declare <8 x i32> @llvm.x86.avx512.mask.cvttps2dq.256(<8 x float>, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.cvttps2dq.256(<8 x float>, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_cvtt_ps2dq_256(<8 x float> %x0, <8 x i32> %x1, i8 %x2) { define <8 x i32>@test_int_x86_avx512_mask_cvtt_ps2dq_256(<8 x float> %x0, <8 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_ps2dq_256: ; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_ps2dq_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvttps2dq %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vcvttps2dq %ymm0, %ymm1 {%k1}
; CHECK-NEXT: vcvttps2dq %ymm0, %ymm0 ; CHECK-NEXT: vcvttps2dq %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.cvttps2dq.256(<8 x float> %x0, <8 x i32> %x1, i8 %x2) %res = call <8 x i32> @llvm.x86.avx512.mask.cvttps2dq.256(<8 x float> %x0, <8 x i32> %x1, i8 %x2)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.cvttps2dq.256(<8 x float> %x0, <8 x i32> %x1, i8 -1) %res1 = call <8 x i32> @llvm.x86.avx512.mask.cvttps2dq.256(<8 x float> %x0, <8 x i32> %x1, i8 -1)
%res2 = add <8 x i32> %res, %res1 %res2 = add <8 x i32> %res, %res1
ret <8 x i32> %res2 ret <8 x i32> %res2
} }
declare <4 x i32> @llvm.x86.avx512.mask.cvttps2udq.128(<4 x float>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.cvttps2udq.128(<4 x float>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_cvtt_ps2udq_128(<4 x float> %x0, <4 x i32> %x1, i8 %x2) { define <4 x i32>@test_int_x86_avx512_mask_cvtt_ps2udq_128(<4 x float> %x0, <4 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_ps2udq_128: ; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_ps2udq_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvttps2udq %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vcvttps2udq %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vcvttps2udq %xmm0, %xmm0 ; CHECK-NEXT: vcvttps2udq %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.cvttps2udq.128(<4 x float> %x0, <4 x i32> %x1, i8 %x2) %res = call <4 x i32> @llvm.x86.avx512.mask.cvttps2udq.128(<4 x float> %x0, <4 x i32> %x1, i8 %x2)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvttps2udq.128(<4 x float> %x0, <4 x i32> %x1, i8 -1) %res1 = call <4 x i32> @llvm.x86.avx512.mask.cvttps2udq.128(<4 x float> %x0, <4 x i32> %x1, i8 -1)
%res2 = add <4 x i32> %res, %res1 %res2 = add <4 x i32> %res, %res1
ret <4 x i32> %res2 ret <4 x i32> %res2
} }
declare <8 x i32> @llvm.x86.avx512.mask.cvttps2udq.256(<8 x float>, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.cvttps2udq.256(<8 x float>, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_cvtt_ps2udq_256(<8 x float> %x0, <8 x i32> %x1, i8 %x2) { define <8 x i32>@test_int_x86_avx512_mask_cvtt_ps2udq_256(<8 x float> %x0, <8 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_ps2udq_256: ; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_ps2udq_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvttps2udq %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vcvttps2udq %ymm0, %ymm1 {%k1}
; CHECK-NEXT: vcvttps2udq %ymm0, %ymm0 ; CHECK-NEXT: vcvttps2udq %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.cvttps2udq.256(<8 x float> %x0, <8 x i32> %x1, i8 %x2) %res = call <8 x i32> @llvm.x86.avx512.mask.cvttps2udq.256(<8 x float> %x0, <8 x i32> %x1, i8 %x2)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.cvttps2udq.256(<8 x float> %x0, <8 x i32> %x1, i8 -1) %res1 = call <8 x i32> @llvm.x86.avx512.mask.cvttps2udq.256(<8 x float> %x0, <8 x i32> %x1, i8 -1)
%res2 = add <8 x i32> %res, %res1 %res2 = add <8 x i32> %res, %res1
ret <8 x i32> %res2 ret <8 x i32> %res2
} }
declare <2 x double> @llvm.x86.avx512.mask.cvtudq2pd.128(<4 x i32>, <2 x double>, i8) declare <2 x double> @llvm.x86.avx512.mask.cvtudq2pd.128(<4 x i32>, <2 x double>, i8)
define <2 x double>@test_int_x86_avx512_mask_cvt_udq2pd_128(<4 x i32> %x0, <2 x double> %x1, i8 %x2) { define <2 x double>@test_int_x86_avx512_mask_cvt_udq2pd_128(<4 x i32> %x0, <2 x double> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_udq2pd_128: ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_udq2pd_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvtudq2pd %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vcvtudq2pd %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vcvtudq2pd %xmm0, %xmm0 ; CHECK-NEXT: vcvtudq2pd %xmm0, %xmm0
; CHECK-NEXT: vaddpd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vaddpd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.cvtudq2pd.128(<4 x i32> %x0, <2 x double> %x1, i8 %x2) %res = call <2 x double> @llvm.x86.avx512.mask.cvtudq2pd.128(<4 x i32> %x0, <2 x double> %x1, i8 %x2)
%res1 = call <2 x double> @llvm.x86.avx512.mask.cvtudq2pd.128(<4 x i32> %x0, <2 x double> %x1, i8 -1) %res1 = call <2 x double> @llvm.x86.avx512.mask.cvtudq2pd.128(<4 x i32> %x0, <2 x double> %x1, i8 -1)
%res2 = fadd <2 x double> %res, %res1 %res2 = fadd <2 x double> %res, %res1
ret <2 x double> %res2 ret <2 x double> %res2
} }
declare <4 x double> @llvm.x86.avx512.mask.cvtudq2pd.256(<4 x i32>, <4 x double>, i8) declare <4 x double> @llvm.x86.avx512.mask.cvtudq2pd.256(<4 x i32>, <4 x double>, i8)
define <4 x double>@test_int_x86_avx512_mask_cvt_udq2pd_256(<4 x i32> %x0, <4 x double> %x1, i8 %x2) { define <4 x double>@test_int_x86_avx512_mask_cvt_udq2pd_256(<4 x i32> %x0, <4 x double> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_udq2pd_256: ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_udq2pd_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvtudq2pd %xmm0, %ymm1 {%k1} ; CHECK-NEXT: vcvtudq2pd %xmm0, %ymm1 {%k1}
; CHECK-NEXT: vcvtudq2pd %xmm0, %ymm0 ; CHECK-NEXT: vcvtudq2pd %xmm0, %ymm0
; CHECK-NEXT: vaddpd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vaddpd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x double> @llvm.x86.avx512.mask.cvtudq2pd.256(<4 x i32> %x0, <4 x double> %x1, i8 %x2) %res = call <4 x double> @llvm.x86.avx512.mask.cvtudq2pd.256(<4 x i32> %x0, <4 x double> %x1, i8 %x2)
%res1 = call <4 x double> @llvm.x86.avx512.mask.cvtudq2pd.256(<4 x i32> %x0, <4 x double> %x1, i8 -1) %res1 = call <4 x double> @llvm.x86.avx512.mask.cvtudq2pd.256(<4 x i32> %x0, <4 x double> %x1, i8 -1)
%res2 = fadd <4 x double> %res, %res1 %res2 = fadd <4 x double> %res, %res1
ret <4 x double> %res2 ret <4 x double> %res2
} }
declare <4 x float> @llvm.x86.avx512.mask.cvtudq2ps.128(<4 x i32>, <4 x float>, i8) declare <4 x float> @llvm.x86.avx512.mask.cvtudq2ps.128(<4 x i32>, <4 x float>, i8)
define <4 x float>@test_int_x86_avx512_mask_cvt_udq2ps_128(<4 x i32> %x0, <4 x float> %x1, i8 %x2) { define <4 x float>@test_int_x86_avx512_mask_cvt_udq2ps_128(<4 x i32> %x0, <4 x float> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_udq2ps_128: ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_udq2ps_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvtudq2ps %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vcvtudq2ps %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vcvtudq2ps %xmm0, %xmm0 ; CHECK-NEXT: vcvtudq2ps %xmm0, %xmm0
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.cvtudq2ps.128(<4 x i32> %x0, <4 x float> %x1, i8 %x2) %res = call <4 x float> @llvm.x86.avx512.mask.cvtudq2ps.128(<4 x i32> %x0, <4 x float> %x1, i8 %x2)
%res1 = call <4 x float> @llvm.x86.avx512.mask.cvtudq2ps.128(<4 x i32> %x0, <4 x float> %x1, i8 -1) %res1 = call <4 x float> @llvm.x86.avx512.mask.cvtudq2ps.128(<4 x i32> %x0, <4 x float> %x1, i8 -1)
%res2 = fadd <4 x float> %res, %res1 %res2 = fadd <4 x float> %res, %res1
ret <4 x float> %res2 ret <4 x float> %res2
} }
declare <8 x float> @llvm.x86.avx512.mask.cvtudq2ps.256(<8 x i32>, <8 x float>, i8) declare <8 x float> @llvm.x86.avx512.mask.cvtudq2ps.256(<8 x i32>, <8 x float>, i8)
define <8 x float>@test_int_x86_avx512_mask_cvt_udq2ps_256(<8 x i32> %x0, <8 x float> %x1, i8 %x2) { define <8 x float>@test_int_x86_avx512_mask_cvt_udq2ps_256(<8 x i32> %x0, <8 x float> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_udq2ps_256: ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_udq2ps_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcvtudq2ps %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vcvtudq2ps %ymm0, %ymm1 {%k1}
; CHECK-NEXT: vcvtudq2ps %ymm0, %ymm0 ; CHECK-NEXT: vcvtudq2ps %ymm0, %ymm0
; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx512.mask.cvtudq2ps.256(<8 x i32> %x0, <8 x float> %x1, i8 %x2) %res = call <8 x float> @llvm.x86.avx512.mask.cvtudq2ps.256(<8 x i32> %x0, <8 x float> %x1, i8 %x2)
%res1 = call <8 x float> @llvm.x86.avx512.mask.cvtudq2ps.256(<8 x i32> %x0, <8 x float> %x1, i8 -1) %res1 = call <8 x float> @llvm.x86.avx512.mask.cvtudq2ps.256(<8 x i32> %x0, <8 x float> %x1, i8 -1)
%res2 = fadd <8 x float> %res, %res1 %res2 = fadd <8 x float> %res, %res1
ret <8 x float> %res2 ret <8 x float> %res2
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Linesdefine <8 x float>@test_int_x86_avx512_mask_rndscale_ps_256(<8 x float> %x0, <8 x float> %x2, i8 %x3) {
ret <8 x float> %res2 ret <8 x float> %res2
} }
declare <8 x float> @llvm.x86.avx512.mask.shuf.f32x4.256(<8 x float>, <8 x float>, i32, <8 x float>, i8) declare <8 x float> @llvm.x86.avx512.mask.shuf.f32x4.256(<8 x float>, <8 x float>, i32, <8 x float>, i8)
define <8 x float>@test_int_x86_avx512_mask_shuf_f32x4_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x3, i8 %x4) { define <8 x float>@test_int_x86_avx512_mask_shuf_f32x4_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x3, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_shuf_f32x4_256: ; CHECK-LABEL: test_int_x86_avx512_mask_shuf_f32x4_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vshuff32x4 $22, %ymm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vshuff32x4 $22, %ymm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: ## ymm2 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; CHECK-NEXT: ## ymm2 = ymm0[0,1,2,3],ymm1[4,5,6,7]
; CHECK-NEXT: vshuff32x4 $22, %ymm1, %ymm0, %ymm3 {%k1} {z} ; CHECK-NEXT: vshuff32x4 $22, %ymm1, %ymm0, %ymm3 {%k1} {z}
; CHECK-NEXT: ## ymm3 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; CHECK-NEXT: ## ymm3 = ymm0[0,1,2,3],ymm1[4,5,6,7]
; CHECK-NEXT: vshuff32x4 $22, %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vshuff32x4 $22, %ymm1, %ymm0, %ymm0
; CHECK-NEXT: ## ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; CHECK-NEXT: ## ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
; CHECK-NEXT: vaddps %ymm0, %ymm2, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm2, %ymm0
; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx512.mask.shuf.f32x4.256(<8 x float> %x0, <8 x float> %x1, i32 22, <8 x float> %x3, i8 %x4) %res = call <8 x float> @llvm.x86.avx512.mask.shuf.f32x4.256(<8 x float> %x0, <8 x float> %x1, i32 22, <8 x float> %x3, i8 %x4)
%res1 = call <8 x float> @llvm.x86.avx512.mask.shuf.f32x4.256(<8 x float> %x0, <8 x float> %x1, i32 22, <8 x float> %x3, i8 -1) %res1 = call <8 x float> @llvm.x86.avx512.mask.shuf.f32x4.256(<8 x float> %x0, <8 x float> %x1, i32 22, <8 x float> %x3, i8 -1)
%res2 = call <8 x float> @llvm.x86.avx512.mask.shuf.f32x4.256(<8 x float> %x0, <8 x float> %x1, i32 22, <8 x float> zeroinitializer, i8 %x4) %res2 = call <8 x float> @llvm.x86.avx512.mask.shuf.f32x4.256(<8 x float> %x0, <8 x float> %x1, i32 22, <8 x float> zeroinitializer, i8 %x4)
%res3 = fadd <8 x float> %res, %res1 %res3 = fadd <8 x float> %res, %res1
%res4 = fadd <8 x float> %res2, %res3 %res4 = fadd <8 x float> %res2, %res3
ret <8 x float> %res4 ret <8 x float> %res4
} }
declare <4 x double> @llvm.x86.avx512.mask.shuf.f64x2.256(<4 x double>, <4 x double>, i32, <4 x double>, i8) declare <4 x double> @llvm.x86.avx512.mask.shuf.f64x2.256(<4 x double>, <4 x double>, i32, <4 x double>, i8)
define <4 x double>@test_int_x86_avx512_mask_shuf_f64x2_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x3, i8 %x4) { define <4 x double>@test_int_x86_avx512_mask_shuf_f64x2_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x3, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_shuf_f64x2_256: ; CHECK-LABEL: test_int_x86_avx512_mask_shuf_f64x2_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vshuff64x2 $22, %ymm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vshuff64x2 $22, %ymm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: ## ymm2 = ymm0[0,1],ymm1[2,3] ; CHECK-NEXT: ## ymm2 = ymm0[0,1],ymm1[2,3]
; CHECK-NEXT: vshuff64x2 $22, %ymm1, %ymm0, %ymm3 {%k1} {z} ; CHECK-NEXT: vshuff64x2 $22, %ymm1, %ymm0, %ymm3 {%k1} {z}
; CHECK-NEXT: ## ymm3 = ymm0[0,1],ymm1[2,3] ; CHECK-NEXT: ## ymm3 = ymm0[0,1],ymm1[2,3]
; CHECK-NEXT: vshuff64x2 $22, %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vshuff64x2 $22, %ymm1, %ymm0, %ymm0
; CHECK-NEXT: ## ymm0 = ymm0[0,1],ymm1[2,3] ; CHECK-NEXT: ## ymm0 = ymm0[0,1],ymm1[2,3]
; CHECK-NEXT: vaddpd %ymm0, %ymm2, %ymm0 ; CHECK-NEXT: vaddpd %ymm0, %ymm2, %ymm0
; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x double> @llvm.x86.avx512.mask.shuf.f64x2.256(<4 x double> %x0, <4 x double> %x1, i32 22, <4 x double> %x3, i8 %x4) %res = call <4 x double> @llvm.x86.avx512.mask.shuf.f64x2.256(<4 x double> %x0, <4 x double> %x1, i32 22, <4 x double> %x3, i8 %x4)
%res1 = call <4 x double> @llvm.x86.avx512.mask.shuf.f64x2.256(<4 x double> %x0, <4 x double> %x1, i32 22, <4 x double> %x3, i8 -1) %res1 = call <4 x double> @llvm.x86.avx512.mask.shuf.f64x2.256(<4 x double> %x0, <4 x double> %x1, i32 22, <4 x double> %x3, i8 -1)
%res2 = call <4 x double> @llvm.x86.avx512.mask.shuf.f64x2.256(<4 x double> %x0, <4 x double> %x1, i32 22, <4 x double> zeroinitializer, i8 %x4) %res2 = call <4 x double> @llvm.x86.avx512.mask.shuf.f64x2.256(<4 x double> %x0, <4 x double> %x1, i32 22, <4 x double> zeroinitializer, i8 %x4)
%res3 = fadd <4 x double> %res, %res1 %res3 = fadd <4 x double> %res, %res1
%res4 = fadd <4 x double> %res2, %res3 %res4 = fadd <4 x double> %res2, %res3
ret <4 x double> %res4 ret <4 x double> %res4
} }
declare <8 x i32> @llvm.x86.avx512.mask.shuf.i32x4.256(<8 x i32>, <8 x i32>, i32, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.shuf.i32x4.256(<8 x i32>, <8 x i32>, i32, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_shuf_i32x4_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x3, i8 %x4) { define <8 x i32>@test_int_x86_avx512_mask_shuf_i32x4_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x3, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_shuf_i32x4_256: ; CHECK-LABEL: test_int_x86_avx512_mask_shuf_i32x4_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vshufi32x4 $22, %ymm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vshufi32x4 $22, %ymm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: ## ymm2 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; CHECK-NEXT: ## ymm2 = ymm0[0,1,2,3],ymm1[4,5,6,7]
; CHECK-NEXT: vshufi32x4 $22, %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vshufi32x4 $22, %ymm1, %ymm0, %ymm0
; CHECK-NEXT: ## ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; CHECK-NEXT: ## ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
; CHECK-NEXT: vpaddd %ymm0, %ymm2, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm2, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.shuf.i32x4.256(<8 x i32> %x0, <8 x i32> %x1, i32 22, <8 x i32> %x3, i8 %x4) %res = call <8 x i32> @llvm.x86.avx512.mask.shuf.i32x4.256(<8 x i32> %x0, <8 x i32> %x1, i32 22, <8 x i32> %x3, i8 %x4)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.shuf.i32x4.256(<8 x i32> %x0, <8 x i32> %x1, i32 22, <8 x i32> %x3, i8 -1) %res1 = call <8 x i32> @llvm.x86.avx512.mask.shuf.i32x4.256(<8 x i32> %x0, <8 x i32> %x1, i32 22, <8 x i32> %x3, i8 -1)
%res2 = add <8 x i32> %res, %res1 %res2 = add <8 x i32> %res, %res1
ret <8 x i32> %res2 ret <8 x i32> %res2
} }
declare <4 x i64> @llvm.x86.avx512.mask.shuf.i64x2.256(<4 x i64>, <4 x i64>, i32, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.shuf.i64x2.256(<4 x i64>, <4 x i64>, i32, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_mask_shuf_i64x2_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x3, i8 %x4) { define <4 x i64>@test_int_x86_avx512_mask_shuf_i64x2_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x3, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_shuf_i64x2_256: ; CHECK-LABEL: test_int_x86_avx512_mask_shuf_i64x2_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vshufi64x2 $22, %ymm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vshufi64x2 $22, %ymm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: ## ymm2 = ymm0[0,1],ymm1[2,3] ; CHECK-NEXT: ## ymm2 = ymm0[0,1],ymm1[2,3]
; CHECK-NEXT: vshufi64x2 $22, %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vshufi64x2 $22, %ymm1, %ymm0, %ymm0
; CHECK-NEXT: ## ymm0 = ymm0[0,1],ymm1[2,3] ; CHECK-NEXT: ## ymm0 = ymm0[0,1],ymm1[2,3]
; CHECK-NEXT: vpaddq %ymm0, %ymm2, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm2, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.shuf.i64x2.256(<4 x i64> %x0, <4 x i64> %x1, i32 22, <4 x i64> %x3, i8 %x4) %res = call <4 x i64> @llvm.x86.avx512.mask.shuf.i64x2.256(<4 x i64> %x0, <4 x i64> %x1, i32 22, <4 x i64> %x3, i8 %x4)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.shuf.i64x2.256(<4 x i64> %x0, <4 x i64> %x1, i32 22, <4 x i64> %x3, i8 -1) %res1 = call <4 x i64> @llvm.x86.avx512.mask.shuf.i64x2.256(<4 x i64> %x0, <4 x i64> %x1, i32 22, <4 x i64> %x3, i8 -1)
Show All 21 Lines; CHECK-NEXT: retq
ret <4 x float> %res4 ret <4 x float> %res4
} }
declare <2 x double> @llvm.x86.avx512.mask.getmant.pd.128(<2 x double>, i32, <2 x double>, i8) declare <2 x double> @llvm.x86.avx512.mask.getmant.pd.128(<2 x double>, i32, <2 x double>, i8)
define <2 x double>@test_int_x86_avx512_mask_getmant_pd_128(<2 x double> %x0, <2 x double> %x2, i8 %x3) { define <2 x double>@test_int_x86_avx512_mask_getmant_pd_128(<2 x double> %x0, <2 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_getmant_pd_128: ; CHECK-LABEL: test_int_x86_avx512_mask_getmant_pd_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vgetmantpd $11, %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vgetmantpd $11, %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vgetmantpd $11, %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vgetmantpd $11, %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vgetmantpd $11, %xmm0, %xmm0 ; CHECK-NEXT: vgetmantpd $11, %xmm0, %xmm0
; CHECK-NEXT: vaddpd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vaddpd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: vaddpd %xmm0, %xmm2, %xmm0 ; CHECK-NEXT: vaddpd %xmm0, %xmm2, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.getmant.pd.128(<2 x double> %x0, i32 11, <2 x double> %x2, i8 %x3) %res = call <2 x double> @llvm.x86.avx512.mask.getmant.pd.128(<2 x double> %x0, i32 11, <2 x double> %x2, i8 %x3)
%res2 = call <2 x double> @llvm.x86.avx512.mask.getmant.pd.128(<2 x double> %x0, i32 11, <2 x double> zeroinitializer, i8 %x3) %res2 = call <2 x double> @llvm.x86.avx512.mask.getmant.pd.128(<2 x double> %x0, i32 11, <2 x double> zeroinitializer, i8 %x3)
%res1 = call <2 x double> @llvm.x86.avx512.mask.getmant.pd.128(<2 x double> %x0, i32 11, <2 x double> %x2, i8 -1) %res1 = call <2 x double> @llvm.x86.avx512.mask.getmant.pd.128(<2 x double> %x0, i32 11, <2 x double> %x2, i8 -1)
%res3 = fadd <2 x double> %res, %res1 %res3 = fadd <2 x double> %res, %res1
%res4 = fadd <2 x double> %res2, %res3 %res4 = fadd <2 x double> %res2, %res3
ret <2 x double> %res4 ret <2 x double> %res4
} }
declare <4 x double> @llvm.x86.avx512.mask.getmant.pd.256(<4 x double>, i32, <4 x double>, i8) declare <4 x double> @llvm.x86.avx512.mask.getmant.pd.256(<4 x double>, i32, <4 x double>, i8)
define <4 x double>@test_int_x86_avx512_mask_getmant_pd_256(<4 x double> %x0, <4 x double> %x2, i8 %x3) { define <4 x double>@test_int_x86_avx512_mask_getmant_pd_256(<4 x double> %x0, <4 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_getmant_pd_256: ; CHECK-LABEL: test_int_x86_avx512_mask_getmant_pd_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vgetmantpd $11, %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vgetmantpd $11, %ymm0, %ymm1 {%k1}
; CHECK-NEXT: vgetmantpd $11, %ymm0, %ymm0 ; CHECK-NEXT: vgetmantpd $11, %ymm0, %ymm0
; CHECK-NEXT: vaddpd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vaddpd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x double> @llvm.x86.avx512.mask.getmant.pd.256(<4 x double> %x0, i32 11, <4 x double> %x2, i8 %x3) %res = call <4 x double> @llvm.x86.avx512.mask.getmant.pd.256(<4 x double> %x0, i32 11, <4 x double> %x2, i8 %x3)
%res1 = call <4 x double> @llvm.x86.avx512.mask.getmant.pd.256(<4 x double> %x0, i32 11, <4 x double> %x2, i8 -1) %res1 = call <4 x double> @llvm.x86.avx512.mask.getmant.pd.256(<4 x double> %x0, i32 11, <4 x double> %x2, i8 -1)
%res2 = fadd <4 x double> %res, %res1 %res2 = fadd <4 x double> %res, %res1
ret <4 x double> %res2 ret <4 x double> %res2
} }
declare <4 x float> @llvm.x86.avx512.mask.getmant.ps.128(<4 x float>, i32, <4 x float>, i8) declare <4 x float> @llvm.x86.avx512.mask.getmant.ps.128(<4 x float>, i32, <4 x float>, i8)
define <4 x float>@test_int_x86_avx512_mask_getmant_ps_128(<4 x float> %x0, <4 x float> %x2, i8 %x3) { define <4 x float>@test_int_x86_avx512_mask_getmant_ps_128(<4 x float> %x0, <4 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_getmant_ps_128: ; CHECK-LABEL: test_int_x86_avx512_mask_getmant_ps_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vgetmantps $11, %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vgetmantps $11, %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vgetmantps $11, %xmm0, %xmm0 ; CHECK-NEXT: vgetmantps $11, %xmm0, %xmm0
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.getmant.ps.128(<4 x float> %x0, i32 11, <4 x float> %x2, i8 %x3) %res = call <4 x float> @llvm.x86.avx512.mask.getmant.ps.128(<4 x float> %x0, i32 11, <4 x float> %x2, i8 %x3)
%res1 = call <4 x float> @llvm.x86.avx512.mask.getmant.ps.128(<4 x float> %x0, i32 11, <4 x float> %x2, i8 -1) %res1 = call <4 x float> @llvm.x86.avx512.mask.getmant.ps.128(<4 x float> %x0, i32 11, <4 x float> %x2, i8 -1)
%res2 = fadd <4 x float> %res, %res1 %res2 = fadd <4 x float> %res, %res1
ret <4 x float> %res2 ret <4 x float> %res2
} }
declare <8 x float> @llvm.x86.avx512.mask.getmant.ps.256(<8 x float>, i32, <8 x float>, i8) declare <8 x float> @llvm.x86.avx512.mask.getmant.ps.256(<8 x float>, i32, <8 x float>, i8)
define <8 x float>@test_int_x86_avx512_mask_getmant_ps_256(<8 x float> %x0, <8 x float> %x2, i8 %x3) { define <8 x float>@test_int_x86_avx512_mask_getmant_ps_256(<8 x float> %x0, <8 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_getmant_ps_256: ; CHECK-LABEL: test_int_x86_avx512_mask_getmant_ps_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vgetmantps $11, %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vgetmantps $11, %ymm0, %ymm1 {%k1}
; CHECK-NEXT: vgetmantps $11, %ymm0, %ymm0 ; CHECK-NEXT: vgetmantps $11, %ymm0, %ymm0
; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx512.mask.getmant.ps.256(<8 x float> %x0, i32 11, <8 x float> %x2, i8 %x3) %res = call <8 x float> @llvm.x86.avx512.mask.getmant.ps.256(<8 x float> %x0, i32 11, <8 x float> %x2, i8 %x3)
%res1 = call <8 x float> @llvm.x86.avx512.mask.getmant.ps.256(<8 x float> %x0, i32 11, <8 x float> %x2, i8 -1) %res1 = call <8 x float> @llvm.x86.avx512.mask.getmant.ps.256(<8 x float> %x0, i32 11, <8 x float> %x2, i8 -1)
%res2 = fadd <8 x float> %res, %res1 %res2 = fadd <8 x float> %res, %res1
ret <8 x float> %res2 ret <8 x float> %res2
} }
declare <2 x double> @llvm.x86.avx512.mask.shuf.pd.128(<2 x double>, <2 x double>, i32, <2 x double>, i8) declare <2 x double> @llvm.x86.avx512.mask.shuf.pd.128(<2 x double>, <2 x double>, i32, <2 x double>, i8)
define <2 x double>@test_int_x86_avx512_mask_shuf_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x3, i8 %x4) { define <2 x double>@test_int_x86_avx512_mask_shuf_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x3, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_shuf_pd_128: ; CHECK-LABEL: test_int_x86_avx512_mask_shuf_pd_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vshufpd $22, %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vshufpd $22, %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: ## xmm2 = xmm2[0],k1[1] ; CHECK-NEXT: ## xmm2 = xmm2[0],k1[1]
; CHECK-NEXT: vshufpd $22, %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: vshufpd $22, %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: ## xmm3 = k1[0],xmm0[1] ; CHECK-NEXT: ## xmm3 = k1[0],xmm0[1]
; CHECK-NEXT: vshufpd $22, %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vshufpd $22, %xmm1, %xmm0, %xmm0
; CHECK-NEXT: ## xmm0 = xmm0[0],xmm1[1] ; CHECK-NEXT: ## xmm0 = xmm0[0],xmm1[1]
; CHECK-NEXT: vaddpd %xmm0, %xmm2, %xmm0 ; CHECK-NEXT: vaddpd %xmm0, %xmm2, %xmm0
; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.shuf.pd.128(<2 x double> %x0, <2 x double> %x1, i32 22, <2 x double> %x3, i8 %x4) %res = call <2 x double> @llvm.x86.avx512.mask.shuf.pd.128(<2 x double> %x0, <2 x double> %x1, i32 22, <2 x double> %x3, i8 %x4)
%res1 = call <2 x double> @llvm.x86.avx512.mask.shuf.pd.128(<2 x double> %x0, <2 x double> %x1, i32 22, <2 x double> %x3, i8 -1) %res1 = call <2 x double> @llvm.x86.avx512.mask.shuf.pd.128(<2 x double> %x0, <2 x double> %x1, i32 22, <2 x double> %x3, i8 -1)
%res2 = call <2 x double> @llvm.x86.avx512.mask.shuf.pd.128(<2 x double> %x0, <2 x double> %x1, i32 22, <2 x double> zeroinitializer, i8 %x4) %res2 = call <2 x double> @llvm.x86.avx512.mask.shuf.pd.128(<2 x double> %x0, <2 x double> %x1, i32 22, <2 x double> zeroinitializer, i8 %x4)
%res3 = fadd <2 x double> %res, %res1 %res3 = fadd <2 x double> %res, %res1
%res4 = fadd <2 x double> %res2, %res3 %res4 = fadd <2 x double> %res2, %res3
ret <2 x double> %res4 ret <2 x double> %res4
} }
declare <4 x double> @llvm.x86.avx512.mask.shuf.pd.256(<4 x double>, <4 x double>, i32, <4 x double>, i8) declare <4 x double> @llvm.x86.avx512.mask.shuf.pd.256(<4 x double>, <4 x double>, i32, <4 x double>, i8)
define <4 x double>@test_int_x86_avx512_mask_shuf_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x3, i8 %x4) { define <4 x double>@test_int_x86_avx512_mask_shuf_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x3, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_shuf_pd_256: ; CHECK-LABEL: test_int_x86_avx512_mask_shuf_pd_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vshufpd $22, %ymm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vshufpd $22, %ymm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: ## ymm2 = ymm2[0],k1[1],ymm2[3],k1[2] ; CHECK-NEXT: ## ymm2 = ymm2[0],k1[1],ymm2[3],k1[2]
; CHECK-NEXT: vshufpd $22, %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vshufpd $22, %ymm1, %ymm0, %ymm0
; CHECK-NEXT: ## ymm0 = ymm0[0],ymm1[1],ymm0[3],ymm1[2] ; CHECK-NEXT: ## ymm0 = ymm0[0],ymm1[1],ymm0[3],ymm1[2]
; CHECK-NEXT: vaddpd %ymm0, %ymm2, %ymm0 ; CHECK-NEXT: vaddpd %ymm0, %ymm2, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x double> @llvm.x86.avx512.mask.shuf.pd.256(<4 x double> %x0, <4 x double> %x1, i32 22, <4 x double> %x3, i8 %x4) %res = call <4 x double> @llvm.x86.avx512.mask.shuf.pd.256(<4 x double> %x0, <4 x double> %x1, i32 22, <4 x double> %x3, i8 %x4)
%res1 = call <4 x double> @llvm.x86.avx512.mask.shuf.pd.256(<4 x double> %x0, <4 x double> %x1, i32 22, <4 x double> %x3, i8 -1) %res1 = call <4 x double> @llvm.x86.avx512.mask.shuf.pd.256(<4 x double> %x0, <4 x double> %x1, i32 22, <4 x double> %x3, i8 -1)
%res2 = fadd <4 x double> %res, %res1 %res2 = fadd <4 x double> %res, %res1
ret <4 x double> %res2 ret <4 x double> %res2
} }
declare <4 x float> @llvm.x86.avx512.mask.shuf.ps.128(<4 x float>, <4 x float>, i32, <4 x float>, i8) declare <4 x float> @llvm.x86.avx512.mask.shuf.ps.128(<4 x float>, <4 x float>, i32, <4 x float>, i8)
define <4 x float>@test_int_x86_avx512_mask_shuf_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x3, i8 %x4) { define <4 x float>@test_int_x86_avx512_mask_shuf_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x3, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_shuf_ps_128: ; CHECK-LABEL: test_int_x86_avx512_mask_shuf_ps_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vshufps $22, %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vshufps $22, %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: ## xmm2 = xmm2[2,1],k1[1,0] ; CHECK-NEXT: ## xmm2 = xmm2[2,1],k1[1,0]
; CHECK-NEXT: vshufps $22, %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vshufps $22, %xmm1, %xmm0, %xmm0
; CHECK-NEXT: ## xmm0 = xmm0[2,1],xmm1[1,0] ; CHECK-NEXT: ## xmm0 = xmm0[2,1],xmm1[1,0]
; CHECK-NEXT: vaddps %xmm0, %xmm2, %xmm0 ; CHECK-NEXT: vaddps %xmm0, %xmm2, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.shuf.ps.128(<4 x float> %x0, <4 x float> %x1, i32 22, <4 x float> %x3, i8 %x4) %res = call <4 x float> @llvm.x86.avx512.mask.shuf.ps.128(<4 x float> %x0, <4 x float> %x1, i32 22, <4 x float> %x3, i8 %x4)
%res1 = call <4 x float> @llvm.x86.avx512.mask.shuf.ps.128(<4 x float> %x0, <4 x float> %x1, i32 22, <4 x float> %x3, i8 -1) %res1 = call <4 x float> @llvm.x86.avx512.mask.shuf.ps.128(<4 x float> %x0, <4 x float> %x1, i32 22, <4 x float> %x3, i8 -1)
%res2 = fadd <4 x float> %res, %res1 %res2 = fadd <4 x float> %res, %res1
ret <4 x float> %res2 ret <4 x float> %res2
} }
declare <8 x float> @llvm.x86.avx512.mask.shuf.ps.256(<8 x float>, <8 x float>, i32, <8 x float>, i8) declare <8 x float> @llvm.x86.avx512.mask.shuf.ps.256(<8 x float>, <8 x float>, i32, <8 x float>, i8)
define <8 x float>@test_int_x86_avx512_mask_shuf_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x3, i8 %x4) { define <8 x float>@test_int_x86_avx512_mask_shuf_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x3, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_shuf_ps_256: ; CHECK-LABEL: test_int_x86_avx512_mask_shuf_ps_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vshufps $22, %ymm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vshufps $22, %ymm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: ## ymm2 = ymm2[2,1],k1[1,0],ymm2[6,5],k1[5,4] ; CHECK-NEXT: ## ymm2 = ymm2[2,1],k1[1,0],ymm2[6,5],k1[5,4]
; CHECK-NEXT: vshufps $22, %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vshufps $22, %ymm1, %ymm0, %ymm0
; CHECK-NEXT: ## ymm0 = ymm0[2,1],ymm1[1,0],ymm0[6,5],ymm1[5,4] ; CHECK-NEXT: ## ymm0 = ymm0[2,1],ymm1[1,0],ymm0[6,5],ymm1[5,4]
; CHECK-NEXT: vaddps %ymm0, %ymm2, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm2, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx512.mask.shuf.ps.256(<8 x float> %x0, <8 x float> %x1, i32 22, <8 x float> %x3, i8 %x4) %res = call <8 x float> @llvm.x86.avx512.mask.shuf.ps.256(<8 x float> %x0, <8 x float> %x1, i32 22, <8 x float> %x3, i8 %x4)
%res1 = call <8 x float> @llvm.x86.avx512.mask.shuf.ps.256(<8 x float> %x0, <8 x float> %x1, i32 22, <8 x float> %x3, i8 -1) %res1 = call <8 x float> @llvm.x86.avx512.mask.shuf.ps.256(<8 x float> %x0, <8 x float> %x1, i32 22, <8 x float> %x3, i8 -1)
%res2 = fadd <8 x float> %res, %res1 %res2 = fadd <8 x float> %res, %res1
ret <8 x float> %res2 ret <8 x float> %res2
} }
declare <4 x i32> @llvm.x86.avx512.mask.valign.d.128(<4 x i32>, <4 x i32>, i32, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.valign.d.128(<4 x i32>, <4 x i32>, i32, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_valign_d_128(<4 x i32> %x0, <4 x i32> %x1,<4 x i32> %x3, i8 %x4) { define <4 x i32>@test_int_x86_avx512_mask_valign_d_128(<4 x i32> %x0, <4 x i32> %x1,<4 x i32> %x3, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_valign_d_128: ; CHECK-LABEL: test_int_x86_avx512_mask_valign_d_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: valignd $22, %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: valignd $22, %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: valignd $22, %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: valignd $22, %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: valignd $22, %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: valignd $22, %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm0
; CHECK-NEXT: vpaddd %xmm3, %xmm0, %xmm0 ; CHECK-NEXT: vpaddd %xmm3, %xmm0, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.valign.d.128(<4 x i32> %x0, <4 x i32> %x1, i32 22, <4 x i32> %x3, i8 %x4) %res = call <4 x i32> @llvm.x86.avx512.mask.valign.d.128(<4 x i32> %x0, <4 x i32> %x1, i32 22, <4 x i32> %x3, i8 %x4)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.valign.d.128(<4 x i32> %x0, <4 x i32> %x1, i32 22, <4 x i32> %x3, i8 -1) %res1 = call <4 x i32> @llvm.x86.avx512.mask.valign.d.128(<4 x i32> %x0, <4 x i32> %x1, i32 22, <4 x i32> %x3, i8 -1)
%res2 = call <4 x i32> @llvm.x86.avx512.mask.valign.d.128(<4 x i32> %x0, <4 x i32> %x1, i32 22, <4 x i32> zeroinitializer,i8 %x4) %res2 = call <4 x i32> @llvm.x86.avx512.mask.valign.d.128(<4 x i32> %x0, <4 x i32> %x1, i32 22, <4 x i32> zeroinitializer,i8 %x4)
%res3 = add <4 x i32> %res, %res1 %res3 = add <4 x i32> %res, %res1
%res4 = add <4 x i32> %res3, %res2 %res4 = add <4 x i32> %res3, %res2
ret <4 x i32> %res4 ret <4 x i32> %res4
} }
declare <8 x i32> @llvm.x86.avx512.mask.valign.d.256(<8 x i32>, <8 x i32>, i32, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.valign.d.256(<8 x i32>, <8 x i32>, i32, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_valign_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x3, i8 %x4) { define <8 x i32>@test_int_x86_avx512_mask_valign_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x3, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_valign_d_256: ; CHECK-LABEL: test_int_x86_avx512_mask_valign_d_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: valignd $22, %ymm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: valignd $22, %ymm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: valignd $22, %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: valignd $22, %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm0, %ymm2, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm2, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.valign.d.256(<8 x i32> %x0, <8 x i32> %x1, i32 22, <8 x i32> %x3, i8 %x4) %res = call <8 x i32> @llvm.x86.avx512.mask.valign.d.256(<8 x i32> %x0, <8 x i32> %x1, i32 22, <8 x i32> %x3, i8 %x4)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.valign.d.256(<8 x i32> %x0, <8 x i32> %x1, i32 22, <8 x i32> %x3, i8 -1) %res1 = call <8 x i32> @llvm.x86.avx512.mask.valign.d.256(<8 x i32> %x0, <8 x i32> %x1, i32 22, <8 x i32> %x3, i8 -1)
%res2 = add <8 x i32> %res, %res1 %res2 = add <8 x i32> %res, %res1
ret <8 x i32> %res2 ret <8 x i32> %res2
} }
declare <2 x i64> @llvm.x86.avx512.mask.valign.q.128(<2 x i64>, <2 x i64>, i32, <2 x i64>, i8) declare <2 x i64> @llvm.x86.avx512.mask.valign.q.128(<2 x i64>, <2 x i64>, i32, <2 x i64>, i8)
define <2 x i64>@test_int_x86_avx512_mask_valign_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x3, i8 %x4) { define <2 x i64>@test_int_x86_avx512_mask_valign_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x3, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_valign_q_128: ; CHECK-LABEL: test_int_x86_avx512_mask_valign_q_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: valignq $22, %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: valignq $22, %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: valignq $22, %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: valignq $22, %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddq %xmm0, %xmm2, %xmm0 ; CHECK-NEXT: vpaddq %xmm0, %xmm2, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.mask.valign.q.128(<2 x i64> %x0, <2 x i64> %x1, i32 22, <2 x i64> %x3, i8 %x4) %res = call <2 x i64> @llvm.x86.avx512.mask.valign.q.128(<2 x i64> %x0, <2 x i64> %x1, i32 22, <2 x i64> %x3, i8 %x4)
%res1 = call <2 x i64> @llvm.x86.avx512.mask.valign.q.128(<2 x i64> %x0, <2 x i64> %x1, i32 22, <2 x i64> %x3, i8 -1) %res1 = call <2 x i64> @llvm.x86.avx512.mask.valign.q.128(<2 x i64> %x0, <2 x i64> %x1, i32 22, <2 x i64> %x3, i8 -1)
%res2 = add <2 x i64> %res, %res1 %res2 = add <2 x i64> %res, %res1
ret <2 x i64> %res2 ret <2 x i64> %res2
} }
declare <4 x i64> @llvm.x86.avx512.mask.valign.q.256(<4 x i64>, <4 x i64>, i32, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.valign.q.256(<4 x i64>, <4 x i64>, i32, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_mask_valign_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x3, i8 %x4) { define <4 x i64>@test_int_x86_avx512_mask_valign_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x3, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_valign_q_256: ; CHECK-LABEL: test_int_x86_avx512_mask_valign_q_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: valignq $22, %ymm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: valignq $22, %ymm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: valignq $22, %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: valignq $22, %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddq %ymm0, %ymm2, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm2, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.valign.q.256(<4 x i64> %x0, <4 x i64> %x1, i32 22, <4 x i64> %x3, i8 %x4) %res = call <4 x i64> @llvm.x86.avx512.mask.valign.q.256(<4 x i64> %x0, <4 x i64> %x1, i32 22, <4 x i64> %x3, i8 %x4)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.valign.q.256(<4 x i64> %x0, <4 x i64> %x1, i32 22, <4 x i64> %x3, i8 -1) %res1 = call <4 x i64> @llvm.x86.avx512.mask.valign.q.256(<4 x i64> %x0, <4 x i64> %x1, i32 22, <4 x i64> %x3, i8 -1)
%res2 = add <4 x i64> %res, %res1 %res2 = add <4 x i64> %res, %res1
ret <4 x i64> %res2 ret <4 x i64> %res2
} }
declare <4 x double> @llvm.x86.avx512.mask.vpermil.pd.256(<4 x double>, i32, <4 x double>, i8) declare <4 x double> @llvm.x86.avx512.mask.vpermil.pd.256(<4 x double>, i32, <4 x double>, i8)
define <4 x double>@test_int_x86_avx512_mask_vpermil_pd_256(<4 x double> %x0, <4 x double> %x2, i8 %x3) { define <4 x double>@test_int_x86_avx512_mask_vpermil_pd_256(<4 x double> %x0, <4 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vpermil_pd_256: ; CHECK-LABEL: test_int_x86_avx512_mask_vpermil_pd_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpermilpd $22, %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vpermilpd $22, %ymm0, %ymm1 {%k1}
; CHECK-NEXT: ## ymm1 = ymm1[0,1,3,2] ; CHECK-NEXT: ## ymm1 = ymm1[0,1,3,2]
; CHECK-NEXT: vpermilpd $22, %ymm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpermilpd $22, %ymm0, %ymm2 {%k1} {z}
; CHECK-NEXT: ## ymm2 = k1[0,1,3,2] ; CHECK-NEXT: ## ymm2 = k1[0,1,3,2]
; CHECK-NEXT: vpermilpd $22, %ymm0, %ymm0 ; CHECK-NEXT: vpermilpd $22, %ymm0, %ymm0
; CHECK-NEXT: ## ymm0 = ymm0[0,1,3,2] ; CHECK-NEXT: ## ymm0 = ymm0[0,1,3,2]
; CHECK-NEXT: vaddpd %ymm2, %ymm1, %ymm1 ; CHECK-NEXT: vaddpd %ymm2, %ymm1, %ymm1
; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x double> @llvm.x86.avx512.mask.vpermil.pd.256(<4 x double> %x0, i32 22, <4 x double> %x2, i8 %x3) %res = call <4 x double> @llvm.x86.avx512.mask.vpermil.pd.256(<4 x double> %x0, i32 22, <4 x double> %x2, i8 %x3)
%res1 = call <4 x double> @llvm.x86.avx512.mask.vpermil.pd.256(<4 x double> %x0, i32 22, <4 x double> zeroinitializer, i8 %x3) %res1 = call <4 x double> @llvm.x86.avx512.mask.vpermil.pd.256(<4 x double> %x0, i32 22, <4 x double> zeroinitializer, i8 %x3)
%res2 = call <4 x double> @llvm.x86.avx512.mask.vpermil.pd.256(<4 x double> %x0, i32 22, <4 x double> %x2, i8 -1) %res2 = call <4 x double> @llvm.x86.avx512.mask.vpermil.pd.256(<4 x double> %x0, i32 22, <4 x double> %x2, i8 -1)
%res3 = fadd <4 x double> %res, %res1 %res3 = fadd <4 x double> %res, %res1
%res4 = fadd <4 x double> %res2, %res3 %res4 = fadd <4 x double> %res2, %res3
ret <4 x double> %res4 ret <4 x double> %res4
} }
declare <2 x double> @llvm.x86.avx512.mask.vpermil.pd.128(<2 x double>, i32, <2 x double>, i8) declare <2 x double> @llvm.x86.avx512.mask.vpermil.pd.128(<2 x double>, i32, <2 x double>, i8)
define <2 x double>@test_int_x86_avx512_mask_vpermil_pd_128(<2 x double> %x0, <2 x double> %x2, i8 %x3) { define <2 x double>@test_int_x86_avx512_mask_vpermil_pd_128(<2 x double> %x0, <2 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vpermil_pd_128: ; CHECK-LABEL: test_int_x86_avx512_mask_vpermil_pd_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpermilpd $1, %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpermilpd $1, %xmm0, %xmm1 {%k1}
; CHECK-NEXT: ## xmm1 = xmm1[1,0] ; CHECK-NEXT: ## xmm1 = xmm1[1,0]
; CHECK-NEXT: vpermilpd $1, %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpermilpd $1, %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: ## xmm2 = k1[1,0] ; CHECK-NEXT: ## xmm2 = k1[1,0]
; CHECK-NEXT: vpermilpd $1, %xmm0, %xmm0 ; CHECK-NEXT: vpermilpd $1, %xmm0, %xmm0
; CHECK-NEXT: ## xmm0 = xmm0[1,0] ; CHECK-NEXT: ## xmm0 = xmm0[1,0]
; CHECK-NEXT: vaddpd %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vaddpd %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vaddpd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vaddpd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.vpermil.pd.128(<2 x double> %x0, i32 1, <2 x double> %x2, i8 %x3) %res = call <2 x double> @llvm.x86.avx512.mask.vpermil.pd.128(<2 x double> %x0, i32 1, <2 x double> %x2, i8 %x3)
%res1 = call <2 x double> @llvm.x86.avx512.mask.vpermil.pd.128(<2 x double> %x0, i32 1, <2 x double> zeroinitializer, i8 %x3) %res1 = call <2 x double> @llvm.x86.avx512.mask.vpermil.pd.128(<2 x double> %x0, i32 1, <2 x double> zeroinitializer, i8 %x3)
%res2 = call <2 x double> @llvm.x86.avx512.mask.vpermil.pd.128(<2 x double> %x0, i32 1, <2 x double> %x2, i8 -1) %res2 = call <2 x double> @llvm.x86.avx512.mask.vpermil.pd.128(<2 x double> %x0, i32 1, <2 x double> %x2, i8 -1)
%res3 = fadd <2 x double> %res, %res1 %res3 = fadd <2 x double> %res, %res1
%res4 = fadd <2 x double> %res3, %res2 %res4 = fadd <2 x double> %res3, %res2
ret <2 x double> %res4 ret <2 x double> %res4
} }
declare <8 x float> @llvm.x86.avx512.mask.vpermil.ps.256(<8 x float>, i32, <8 x float>, i8) declare <8 x float> @llvm.x86.avx512.mask.vpermil.ps.256(<8 x float>, i32, <8 x float>, i8)
define <8 x float>@test_int_x86_avx512_mask_vpermil_ps_256(<8 x float> %x0, <8 x float> %x2, i8 %x3) { define <8 x float>@test_int_x86_avx512_mask_vpermil_ps_256(<8 x float> %x0, <8 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vpermil_ps_256: ; CHECK-LABEL: test_int_x86_avx512_mask_vpermil_ps_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpermilps $22, %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vpermilps $22, %ymm0, %ymm1 {%k1}
; CHECK-NEXT: ## ymm1 = ymm1[2,1,1,0,6,5,5,4] ; CHECK-NEXT: ## ymm1 = ymm1[2,1,1,0,6,5,5,4]
; CHECK-NEXT: vpermilps $22, %ymm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpermilps $22, %ymm0, %ymm2 {%k1} {z}
; CHECK-NEXT: ## ymm2 = k1[2,1,1,0,6,5,5,4] ; CHECK-NEXT: ## ymm2 = k1[2,1,1,0,6,5,5,4]
; CHECK-NEXT: vpermilps $22, %ymm0, %ymm0 ; CHECK-NEXT: vpermilps $22, %ymm0, %ymm0
; CHECK-NEXT: ## ymm0 = ymm0[2,1,1,0,6,5,5,4] ; CHECK-NEXT: ## ymm0 = ymm0[2,1,1,0,6,5,5,4]
; CHECK-NEXT: vaddps %ymm2, %ymm1, %ymm1 ; CHECK-NEXT: vaddps %ymm2, %ymm1, %ymm1
; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx512.mask.vpermil.ps.256(<8 x float> %x0, i32 22, <8 x float> %x2, i8 %x3) %res = call <8 x float> @llvm.x86.avx512.mask.vpermil.ps.256(<8 x float> %x0, i32 22, <8 x float> %x2, i8 %x3)
%res1 = call <8 x float> @llvm.x86.avx512.mask.vpermil.ps.256(<8 x float> %x0, i32 22, <8 x float> zeroinitializer, i8 %x3) %res1 = call <8 x float> @llvm.x86.avx512.mask.vpermil.ps.256(<8 x float> %x0, i32 22, <8 x float> zeroinitializer, i8 %x3)
%res2 = call <8 x float> @llvm.x86.avx512.mask.vpermil.ps.256(<8 x float> %x0, i32 22, <8 x float> %x2, i8 -1) %res2 = call <8 x float> @llvm.x86.avx512.mask.vpermil.ps.256(<8 x float> %x0, i32 22, <8 x float> %x2, i8 -1)
%res3 = fadd <8 x float> %res, %res1 %res3 = fadd <8 x float> %res, %res1
%res4 = fadd <8 x float> %res3, %res2 %res4 = fadd <8 x float> %res3, %res2
ret <8 x float> %res4 ret <8 x float> %res4
} }
declare <4 x float> @llvm.x86.avx512.mask.vpermil.ps.128(<4 x float>, i32, <4 x float>, i8) declare <4 x float> @llvm.x86.avx512.mask.vpermil.ps.128(<4 x float>, i32, <4 x float>, i8)
define <4 x float>@test_int_x86_avx512_mask_vpermil_ps_128(<4 x float> %x0, <4 x float> %x2, i8 %x3) { define <4 x float>@test_int_x86_avx512_mask_vpermil_ps_128(<4 x float> %x0, <4 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vpermil_ps_128: ; CHECK-LABEL: test_int_x86_avx512_mask_vpermil_ps_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpermilps $22, %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpermilps $22, %xmm0, %xmm1 {%k1}
; CHECK-NEXT: ## xmm1 = xmm1[2,1,1,0] ; CHECK-NEXT: ## xmm1 = xmm1[2,1,1,0]
; CHECK-NEXT: vpermilps $22, %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpermilps $22, %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: ## xmm2 = k1[2,1,1,0] ; CHECK-NEXT: ## xmm2 = k1[2,1,1,0]
; CHECK-NEXT: vpermilps $22, %xmm0, %xmm0 ; CHECK-NEXT: vpermilps $22, %xmm0, %xmm0
; CHECK-NEXT: ## xmm0 = xmm0[2,1,1,0] ; CHECK-NEXT: ## xmm0 = xmm0[2,1,1,0]
; CHECK-NEXT: vaddps %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vaddps %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vaddps %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.vpermil.ps.128(<4 x float> %x0, i32 22, <4 x float> %x2, i8 %x3) %res = call <4 x float> @llvm.x86.avx512.mask.vpermil.ps.128(<4 x float> %x0, i32 22, <4 x float> %x2, i8 %x3)
%res1 = call <4 x float> @llvm.x86.avx512.mask.vpermil.ps.128(<4 x float> %x0, i32 22, <4 x float> zeroinitializer, i8 %x3) %res1 = call <4 x float> @llvm.x86.avx512.mask.vpermil.ps.128(<4 x float> %x0, i32 22, <4 x float> zeroinitializer, i8 %x3)
%res2 = call <4 x float> @llvm.x86.avx512.mask.vpermil.ps.128(<4 x float> %x0, i32 22, <4 x float> %x2, i8 -1) %res2 = call <4 x float> @llvm.x86.avx512.mask.vpermil.ps.128(<4 x float> %x0, i32 22, <4 x float> %x2, i8 -1)
%res3 = fadd <4 x float> %res, %res1 %res3 = fadd <4 x float> %res, %res1
%res4 = fadd <4 x float> %res2, %res3 %res4 = fadd <4 x float> %res2, %res3
ret <4 x float> %res4 ret <4 x float> %res4
} }
declare <4 x double> @llvm.x86.avx512.mask.vpermilvar.pd.256(<4 x double>, <4 x i64>, <4 x double>, i8) declare <4 x double> @llvm.x86.avx512.mask.vpermilvar.pd.256(<4 x double>, <4 x i64>, <4 x double>, i8)
define <4 x double>@test_int_x86_avx512_mask_vpermilvar_pd_256(<4 x double> %x0, <4 x i64> %x1, <4 x double> %x2, i8 %x3) { define <4 x double>@test_int_x86_avx512_mask_vpermilvar_pd_256(<4 x double> %x0, <4 x i64> %x1, <4 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vpermilvar_pd_256: ; CHECK-LABEL: test_int_x86_avx512_mask_vpermilvar_pd_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpermilpd %ymm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vpermilpd %ymm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: vpermilpd %ymm1, %ymm0, %ymm3 {%k1} {z} ; CHECK-NEXT: vpermilpd %ymm1, %ymm0, %ymm3 {%k1} {z}
; CHECK-NEXT: vpermilpd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vpermilpd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vaddpd %ymm3, %ymm2, %ymm1 ; CHECK-NEXT: vaddpd %ymm3, %ymm2, %ymm1
; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x double> @llvm.x86.avx512.mask.vpermilvar.pd.256(<4 x double> %x0, <4 x i64> %x1, <4 x double> %x2, i8 %x3) %res = call <4 x double> @llvm.x86.avx512.mask.vpermilvar.pd.256(<4 x double> %x0, <4 x i64> %x1, <4 x double> %x2, i8 %x3)
%res1 = call <4 x double> @llvm.x86.avx512.mask.vpermilvar.pd.256(<4 x double> %x0, <4 x i64> %x1, <4 x double> zeroinitializer, i8 %x3) %res1 = call <4 x double> @llvm.x86.avx512.mask.vpermilvar.pd.256(<4 x double> %x0, <4 x i64> %x1, <4 x double> zeroinitializer, i8 %x3)
%res2 = call <4 x double> @llvm.x86.avx512.mask.vpermilvar.pd.256(<4 x double> %x0, <4 x i64> %x1, <4 x double> %x2, i8 -1) %res2 = call <4 x double> @llvm.x86.avx512.mask.vpermilvar.pd.256(<4 x double> %x0, <4 x i64> %x1, <4 x double> %x2, i8 -1)
%res3 = fadd <4 x double> %res, %res1 %res3 = fadd <4 x double> %res, %res1
%res4 = fadd <4 x double> %res2, %res3 %res4 = fadd <4 x double> %res2, %res3
ret <4 x double> %res4 ret <4 x double> %res4
} }
declare <2 x double> @llvm.x86.avx512.mask.vpermilvar.pd.128(<2 x double>, <2 x i64>, <2 x double>, i8) declare <2 x double> @llvm.x86.avx512.mask.vpermilvar.pd.128(<2 x double>, <2 x i64>, <2 x double>, i8)
define <2 x double>@test_int_x86_avx512_mask_vpermilvar_pd_128(<2 x double> %x0, <2 x i64> %x1, <2 x double> %x2, i8 %x3) { define <2 x double>@test_int_x86_avx512_mask_vpermilvar_pd_128(<2 x double> %x0, <2 x i64> %x1, <2 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vpermilvar_pd_128: ; CHECK-LABEL: test_int_x86_avx512_mask_vpermilvar_pd_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpermilpd %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vpermilpd %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vpermilpd %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: vpermilpd %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: vpermilpd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpermilpd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vaddpd %xmm3, %xmm2, %xmm1 ; CHECK-NEXT: vaddpd %xmm3, %xmm2, %xmm1
; CHECK-NEXT: vaddpd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vaddpd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.vpermilvar.pd.128(<2 x double> %x0, <2 x i64> %x1, <2 x double> %x2, i8 %x3) %res = call <2 x double> @llvm.x86.avx512.mask.vpermilvar.pd.128(<2 x double> %x0, <2 x i64> %x1, <2 x double> %x2, i8 %x3)
%res1 = call <2 x double> @llvm.x86.avx512.mask.vpermilvar.pd.128(<2 x double> %x0, <2 x i64> %x1, <2 x double> zeroinitializer, i8 %x3) %res1 = call <2 x double> @llvm.x86.avx512.mask.vpermilvar.pd.128(<2 x double> %x0, <2 x i64> %x1, <2 x double> zeroinitializer, i8 %x3)
%res2 = call <2 x double> @llvm.x86.avx512.mask.vpermilvar.pd.128(<2 x double> %x0, <2 x i64> %x1, <2 x double> %x2, i8 -1) %res2 = call <2 x double> @llvm.x86.avx512.mask.vpermilvar.pd.128(<2 x double> %x0, <2 x i64> %x1, <2 x double> %x2, i8 -1)
%res3 = fadd <2 x double> %res, %res1 %res3 = fadd <2 x double> %res, %res1
%res4 = fadd <2 x double> %res3, %res2 %res4 = fadd <2 x double> %res3, %res2
ret <2 x double> %res4 ret <2 x double> %res4
} }
declare <8 x float> @llvm.x86.avx512.mask.vpermilvar.ps.256(<8 x float>, <8 x i32>, <8 x float>, i8) declare <8 x float> @llvm.x86.avx512.mask.vpermilvar.ps.256(<8 x float>, <8 x i32>, <8 x float>, i8)
define <8 x float>@test_int_x86_avx512_mask_vpermilvar_ps_256(<8 x float> %x0, <8 x i32> %x1, <8 x float> %x2, i8 %x3) { define <8 x float>@test_int_x86_avx512_mask_vpermilvar_ps_256(<8 x float> %x0, <8 x i32> %x1, <8 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vpermilvar_ps_256: ; CHECK-LABEL: test_int_x86_avx512_mask_vpermilvar_ps_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpermilps %ymm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vpermilps %ymm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: vpermilps %ymm1, %ymm0, %ymm3 {%k1} {z} ; CHECK-NEXT: vpermilps %ymm1, %ymm0, %ymm3 {%k1} {z}
; CHECK-NEXT: vpermilps %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vpermilps %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vaddps %ymm3, %ymm2, %ymm1 ; CHECK-NEXT: vaddps %ymm3, %ymm2, %ymm1
; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx512.mask.vpermilvar.ps.256(<8 x float> %x0, <8 x i32> %x1, <8 x float> %x2, i8 %x3) %res = call <8 x float> @llvm.x86.avx512.mask.vpermilvar.ps.256(<8 x float> %x0, <8 x i32> %x1, <8 x float> %x2, i8 %x3)
%res1 = call <8 x float> @llvm.x86.avx512.mask.vpermilvar.ps.256(<8 x float> %x0, <8 x i32> %x1, <8 x float> zeroinitializer, i8 %x3) %res1 = call <8 x float> @llvm.x86.avx512.mask.vpermilvar.ps.256(<8 x float> %x0, <8 x i32> %x1, <8 x float> zeroinitializer, i8 %x3)
%res2 = call <8 x float> @llvm.x86.avx512.mask.vpermilvar.ps.256(<8 x float> %x0, <8 x i32> %x1, <8 x float> %x2, i8 -1) %res2 = call <8 x float> @llvm.x86.avx512.mask.vpermilvar.ps.256(<8 x float> %x0, <8 x i32> %x1, <8 x float> %x2, i8 -1)
%res3 = fadd <8 x float> %res, %res1 %res3 = fadd <8 x float> %res, %res1
%res4 = fadd <8 x float> %res3, %res2 %res4 = fadd <8 x float> %res3, %res2
ret <8 x float> %res4 ret <8 x float> %res4
} }
declare <4 x float> @llvm.x86.avx512.mask.vpermilvar.ps.128(<4 x float>, <4 x i32>, <4 x float>, i8) declare <4 x float> @llvm.x86.avx512.mask.vpermilvar.ps.128(<4 x float>, <4 x i32>, <4 x float>, i8)
define <4 x float>@test_int_x86_avx512_mask_vpermilvar_ps_128(<4 x float> %x0, <4 x i32> %x1, <4 x float> %x2, i8 %x3) { define <4 x float>@test_int_x86_avx512_mask_vpermilvar_ps_128(<4 x float> %x0, <4 x i32> %x1, <4 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_vpermilvar_ps_128: ; CHECK-LABEL: test_int_x86_avx512_mask_vpermilvar_ps_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpermilps %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vpermilps %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vpermilps %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: vpermilps %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: vpermilps %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpermilps %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vaddps %xmm3, %xmm2, %xmm1 ; CHECK-NEXT: vaddps %xmm3, %xmm2, %xmm1
; CHECK-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vaddps %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.vpermilvar.ps.128(<4 x float> %x0, <4 x i32> %x1, <4 x float> %x2, i8 %x3) %res = call <4 x float> @llvm.x86.avx512.mask.vpermilvar.ps.128(<4 x float> %x0, <4 x i32> %x1, <4 x float> %x2, i8 %x3)
%res1 = call <4 x float> @llvm.x86.avx512.mask.vpermilvar.ps.128(<4 x float> %x0, <4 x i32> %x1, <4 x float> zeroinitializer, i8 %x3) %res1 = call <4 x float> @llvm.x86.avx512.mask.vpermilvar.ps.128(<4 x float> %x0, <4 x i32> %x1, <4 x float> zeroinitializer, i8 %x3)
%res2 = call <4 x float> @llvm.x86.avx512.mask.vpermilvar.ps.128(<4 x float> %x0, <4 x i32> %x1, <4 x float> %x2, i8 -1) %res2 = call <4 x float> @llvm.x86.avx512.mask.vpermilvar.ps.128(<4 x float> %x0, <4 x i32> %x1, <4 x float> %x2, i8 -1)
%res3 = fadd <4 x float> %res, %res1 %res3 = fadd <4 x float> %res, %res1
%res4 = fadd <4 x float> %res2, %res3 %res4 = fadd <4 x float> %res2, %res3
ret <4 x float> %res4 ret <4 x float> %res4
} }
declare <8 x float> @llvm.x86.avx512.mask.insertf32x4.256(<8 x float>, <4 x float>, i32, <8 x float>, i8) declare <8 x float> @llvm.x86.avx512.mask.insertf32x4.256(<8 x float>, <4 x float>, i32, <8 x float>, i8)
define <8 x float>@test_int_x86_avx512_mask_insertf32x4_256(<8 x float> %x0, <4 x float> %x1, <8 x float> %x3, i8 %x4) { define <8 x float>@test_int_x86_avx512_mask_insertf32x4_256(<8 x float> %x0, <4 x float> %x1, <8 x float> %x3, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_insertf32x4_256: ; CHECK-LABEL: test_int_x86_avx512_mask_insertf32x4_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vinsertf32x4 $1, %xmm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vinsertf32x4 $1, %xmm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: vinsertf32x4 $1, %xmm1, %ymm0, %ymm3 {%k1} {z} ; CHECK-NEXT: vinsertf32x4 $1, %xmm1, %ymm0, %ymm3 {%k1} {z}
; CHECK-NEXT: vinsertf32x4 $1, %xmm1, %ymm0, %ymm0 ; CHECK-NEXT: vinsertf32x4 $1, %xmm1, %ymm0, %ymm0
; CHECK-NEXT: vaddps %ymm0, %ymm2, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm2, %ymm0
; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx512.mask.insertf32x4.256(<8 x float> %x0, <4 x float> %x1, i32 1, <8 x float> %x3, i8 %x4) %res = call <8 x float> @llvm.x86.avx512.mask.insertf32x4.256(<8 x float> %x0, <4 x float> %x1, i32 1, <8 x float> %x3, i8 %x4)
%res1 = call <8 x float> @llvm.x86.avx512.mask.insertf32x4.256(<8 x float> %x0, <4 x float> %x1, i32 1, <8 x float> %x3, i8 -1) %res1 = call <8 x float> @llvm.x86.avx512.mask.insertf32x4.256(<8 x float> %x0, <4 x float> %x1, i32 1, <8 x float> %x3, i8 -1)
%res2 = call <8 x float> @llvm.x86.avx512.mask.insertf32x4.256(<8 x float> %x0, <4 x float> %x1, i32 1, <8 x float> zeroinitializer, i8 %x4) %res2 = call <8 x float> @llvm.x86.avx512.mask.insertf32x4.256(<8 x float> %x0, <4 x float> %x1, i32 1, <8 x float> zeroinitializer, i8 %x4)
%res3 = fadd <8 x float> %res, %res1 %res3 = fadd <8 x float> %res, %res1
%res4 = fadd <8 x float> %res2, %res3 %res4 = fadd <8 x float> %res2, %res3
ret <8 x float> %res4 ret <8 x float> %res4
} }
declare <8 x i32> @llvm.x86.avx512.mask.inserti32x4.256(<8 x i32>, <4 x i32>, i32, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.inserti32x4.256(<8 x i32>, <4 x i32>, i32, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_inserti32x4_256(<8 x i32> %x0, <4 x i32> %x1, <8 x i32> %x3, i8 %x4) { define <8 x i32>@test_int_x86_avx512_mask_inserti32x4_256(<8 x i32> %x0, <4 x i32> %x1, <8 x i32> %x3, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_inserti32x4_256: ; CHECK-LABEL: test_int_x86_avx512_mask_inserti32x4_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vinserti32x4 $1, %xmm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vinserti32x4 $1, %xmm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: vinserti32x4 $1, %xmm1, %ymm0, %ymm3 {%k1} {z} ; CHECK-NEXT: vinserti32x4 $1, %xmm1, %ymm0, %ymm3 {%k1} {z}
; CHECK-NEXT: vinserti32x4 $1, %xmm1, %ymm0, %ymm0 ; CHECK-NEXT: vinserti32x4 $1, %xmm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm0, %ymm2, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm2, %ymm0
; CHECK-NEXT: vpaddd %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.inserti32x4.256(<8 x i32> %x0, <4 x i32> %x1, i32 1, <8 x i32> %x3, i8 %x4) %res = call <8 x i32> @llvm.x86.avx512.mask.inserti32x4.256(<8 x i32> %x0, <4 x i32> %x1, i32 1, <8 x i32> %x3, i8 %x4)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.inserti32x4.256(<8 x i32> %x0, <4 x i32> %x1, i32 1, <8 x i32> %x3, i8 -1) %res1 = call <8 x i32> @llvm.x86.avx512.mask.inserti32x4.256(<8 x i32> %x0, <4 x i32> %x1, i32 1, <8 x i32> %x3, i8 -1)
%res2 = call <8 x i32> @llvm.x86.avx512.mask.inserti32x4.256(<8 x i32> %x0, <4 x i32> %x1, i32 1, <8 x i32> zeroinitializer, i8 %x4) %res2 = call <8 x i32> @llvm.x86.avx512.mask.inserti32x4.256(<8 x i32> %x0, <4 x i32> %x1, i32 1, <8 x i32> zeroinitializer, i8 %x4)
%res3 = add <8 x i32> %res, %res1 %res3 = add <8 x i32> %res, %res1
%res4 = add <8 x i32> %res2, %res3 %res4 = add <8 x i32> %res2, %res3
ret <8 x i32> %res4 ret <8 x i32> %res4
} }
declare <4 x i32> @llvm.x86.avx512.mask.pternlog.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i32, i8) declare <4 x i32> @llvm.x86.avx512.mask.pternlog.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i32, i8)
define <4 x i32>@test_int_x86_avx512_mask_pternlog_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x4) { define <4 x i32>@test_int_x86_avx512_mask_pternlog_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_pternlog_d_128: ; CHECK-LABEL: test_int_x86_avx512_mask_pternlog_d_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vpternlogd $33, %xmm2, %xmm1, %xmm3 {%k1} ; CHECK-NEXT: vpternlogd $33, %xmm2, %xmm1, %xmm3 {%k1}
; CHECK-NEXT: vpternlogd $33, %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vpternlogd $33, %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.pternlog.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i32 33, i8 %x4) %res = call <4 x i32> @llvm.x86.avx512.mask.pternlog.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i32 33, i8 %x4)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.pternlog.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i32 33, i8 -1) %res1 = call <4 x i32> @llvm.x86.avx512.mask.pternlog.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i32 33, i8 -1)
%res2 = add <4 x i32> %res, %res1 %res2 = add <4 x i32> %res, %res1
ret <4 x i32> %res2 ret <4 x i32> %res2
} }
declare <4 x i32> @llvm.x86.avx512.maskz.pternlog.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i32, i8) declare <4 x i32> @llvm.x86.avx512.maskz.pternlog.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i32, i8)
define <4 x i32>@test_int_x86_avx512_maskz_pternlog_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x4) { define <4 x i32>@test_int_x86_avx512_maskz_pternlog_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_maskz_pternlog_d_128: ; CHECK-LABEL: test_int_x86_avx512_maskz_pternlog_d_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vpternlogd $33, %xmm2, %xmm1, %xmm3 {%k1} {z} ; CHECK-NEXT: vpternlogd $33, %xmm2, %xmm1, %xmm3 {%k1} {z}
; CHECK-NEXT: vpternlogd $33, %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vpternlogd $33, %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.maskz.pternlog.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i32 33, i8 %x4) %res = call <4 x i32> @llvm.x86.avx512.maskz.pternlog.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i32 33, i8 %x4)
%res1 = call <4 x i32> @llvm.x86.avx512.maskz.pternlog.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i32 33, i8 -1) %res1 = call <4 x i32> @llvm.x86.avx512.maskz.pternlog.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i32 33, i8 -1)
%res2 = add <4 x i32> %res, %res1 %res2 = add <4 x i32> %res, %res1
ret <4 x i32> %res2 ret <4 x i32> %res2
} }
declare <8 x i32> @llvm.x86.avx512.mask.pternlog.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i32, i8) declare <8 x i32> @llvm.x86.avx512.mask.pternlog.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i32, i8)
define <8 x i32>@test_int_x86_avx512_mask_pternlog_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x4) { define <8 x i32>@test_int_x86_avx512_mask_pternlog_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_pternlog_d_256: ; CHECK-LABEL: test_int_x86_avx512_mask_pternlog_d_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vpternlogd $33, %ymm2, %ymm1, %ymm3 {%k1} ; CHECK-NEXT: vpternlogd $33, %ymm2, %ymm1, %ymm3 {%k1}
; CHECK-NEXT: vpternlogd $33, %ymm2, %ymm1, %ymm0 ; CHECK-NEXT: vpternlogd $33, %ymm2, %ymm1, %ymm0
; CHECK-NEXT: vpaddd %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.pternlog.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i32 33, i8 %x4) %res = call <8 x i32> @llvm.x86.avx512.mask.pternlog.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i32 33, i8 %x4)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.pternlog.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i32 33, i8 -1) %res1 = call <8 x i32> @llvm.x86.avx512.mask.pternlog.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i32 33, i8 -1)
%res2 = add <8 x i32> %res, %res1 %res2 = add <8 x i32> %res, %res1
ret <8 x i32> %res2 ret <8 x i32> %res2
} }
declare <8 x i32> @llvm.x86.avx512.maskz.pternlog.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i32, i8) declare <8 x i32> @llvm.x86.avx512.maskz.pternlog.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i32, i8)
define <8 x i32>@test_int_x86_avx512_maskz_pternlog_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x4) { define <8 x i32>@test_int_x86_avx512_maskz_pternlog_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_maskz_pternlog_d_256: ; CHECK-LABEL: test_int_x86_avx512_maskz_pternlog_d_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vpternlogd $33, %ymm2, %ymm1, %ymm3 {%k1} {z} ; CHECK-NEXT: vpternlogd $33, %ymm2, %ymm1, %ymm3 {%k1} {z}
; CHECK-NEXT: vpternlogd $33, %ymm2, %ymm1, %ymm0 ; CHECK-NEXT: vpternlogd $33, %ymm2, %ymm1, %ymm0
; CHECK-NEXT: vpaddd %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.maskz.pternlog.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i32 33, i8 %x4) %res = call <8 x i32> @llvm.x86.avx512.maskz.pternlog.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i32 33, i8 %x4)
%res1 = call <8 x i32> @llvm.x86.avx512.maskz.pternlog.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i32 33, i8 -1) %res1 = call <8 x i32> @llvm.x86.avx512.maskz.pternlog.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i32 33, i8 -1)
%res2 = add <8 x i32> %res, %res1 %res2 = add <8 x i32> %res, %res1
ret <8 x i32> %res2 ret <8 x i32> %res2
} }
declare <2 x i64> @llvm.x86.avx512.mask.pternlog.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i32, i8) declare <2 x i64> @llvm.x86.avx512.mask.pternlog.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i32, i8)
define <2 x i64>@test_int_x86_avx512_mask_pternlog_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x4) { define <2 x i64>@test_int_x86_avx512_mask_pternlog_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_pternlog_q_128: ; CHECK-LABEL: test_int_x86_avx512_mask_pternlog_q_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vpternlogq $33, %xmm2, %xmm1, %xmm3 {%k1} ; CHECK-NEXT: vpternlogq $33, %xmm2, %xmm1, %xmm3 {%k1}
; CHECK-NEXT: vpternlogq $33, %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vpternlogq $33, %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vpaddq %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vpaddq %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.mask.pternlog.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i32 33, i8 %x4) %res = call <2 x i64> @llvm.x86.avx512.mask.pternlog.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i32 33, i8 %x4)
%res1 = call <2 x i64> @llvm.x86.avx512.mask.pternlog.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i32 33, i8 -1) %res1 = call <2 x i64> @llvm.x86.avx512.mask.pternlog.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i32 33, i8 -1)
%res2 = add <2 x i64> %res, %res1 %res2 = add <2 x i64> %res, %res1
ret <2 x i64> %res2 ret <2 x i64> %res2
} }
declare <2 x i64> @llvm.x86.avx512.maskz.pternlog.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i32, i8) declare <2 x i64> @llvm.x86.avx512.maskz.pternlog.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i32, i8)
define <2 x i64>@test_int_x86_avx512_maskz_pternlog_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x4) { define <2 x i64>@test_int_x86_avx512_maskz_pternlog_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_maskz_pternlog_q_128: ; CHECK-LABEL: test_int_x86_avx512_maskz_pternlog_q_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vpternlogq $33, %xmm2, %xmm1, %xmm3 {%k1} {z} ; CHECK-NEXT: vpternlogq $33, %xmm2, %xmm1, %xmm3 {%k1} {z}
; CHECK-NEXT: vpternlogq $33, %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vpternlogq $33, %xmm2, %xmm1, %xmm0
; CHECK-NEXT: vpaddq %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vpaddq %xmm0, %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.maskz.pternlog.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i32 33, i8 %x4) %res = call <2 x i64> @llvm.x86.avx512.maskz.pternlog.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i32 33, i8 %x4)
%res1 = call <2 x i64> @llvm.x86.avx512.maskz.pternlog.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i32 33, i8 -1) %res1 = call <2 x i64> @llvm.x86.avx512.maskz.pternlog.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i32 33, i8 -1)
%res2 = add <2 x i64> %res, %res1 %res2 = add <2 x i64> %res, %res1
ret <2 x i64> %res2 ret <2 x i64> %res2
} }
declare <4 x i64> @llvm.x86.avx512.mask.pternlog.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i32, i8) declare <4 x i64> @llvm.x86.avx512.mask.pternlog.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i32, i8)
define <4 x i64>@test_int_x86_avx512_mask_pternlog_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x4) { define <4 x i64>@test_int_x86_avx512_mask_pternlog_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_mask_pternlog_q_256: ; CHECK-LABEL: test_int_x86_avx512_mask_pternlog_q_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vpternlogq $33, %ymm2, %ymm1, %ymm3 {%k1} ; CHECK-NEXT: vpternlogq $33, %ymm2, %ymm1, %ymm3 {%k1}
; CHECK-NEXT: vpternlogq $33, %ymm2, %ymm1, %ymm0 ; CHECK-NEXT: vpternlogq $33, %ymm2, %ymm1, %ymm0
; CHECK-NEXT: vpaddq %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.pternlog.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i32 33, i8 %x4) %res = call <4 x i64> @llvm.x86.avx512.mask.pternlog.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i32 33, i8 %x4)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.pternlog.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i32 33, i8 -1) %res1 = call <4 x i64> @llvm.x86.avx512.mask.pternlog.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i32 33, i8 -1)
%res2 = add <4 x i64> %res, %res1 %res2 = add <4 x i64> %res, %res1
ret <4 x i64> %res2 ret <4 x i64> %res2
} }
declare <4 x i64> @llvm.x86.avx512.maskz.pternlog.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i32, i8) declare <4 x i64> @llvm.x86.avx512.maskz.pternlog.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i32, i8)
define <4 x i64>@test_int_x86_avx512_maskz_pternlog_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x4) { define <4 x i64>@test_int_x86_avx512_maskz_pternlog_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x4) {
; CHECK-LABEL: test_int_x86_avx512_maskz_pternlog_q_256: ; CHECK-LABEL: test_int_x86_avx512_maskz_pternlog_q_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps %zmm0, %zmm3 ; CHECK-NEXT: vmovaps %zmm0, %zmm3
; CHECK-NEXT: vpternlogq $33, %ymm2, %ymm1, %ymm3 {%k1} {z} ; CHECK-NEXT: vpternlogq $33, %ymm2, %ymm1, %ymm3 {%k1} {z}
; CHECK-NEXT: vpternlogq $33, %ymm2, %ymm1, %ymm0 ; CHECK-NEXT: vpternlogq $33, %ymm2, %ymm1, %ymm0
; CHECK-NEXT: vpaddq %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.maskz.pternlog.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i32 33, i8 %x4) %res = call <4 x i64> @llvm.x86.avx512.maskz.pternlog.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i32 33, i8 %x4)
%res1 = call <4 x i64> @llvm.x86.avx512.maskz.pternlog.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i32 33, i8 -1) %res1 = call <4 x i64> @llvm.x86.avx512.maskz.pternlog.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i32 33, i8 -1)
%res2 = add <4 x i64> %res, %res1 %res2 = add <4 x i64> %res, %res1
ret <4 x i64> %res2 ret <4 x i64> %res2
} }
declare <8 x i32> @llvm.x86.avx512.pbroadcastd.256(<4 x i32>, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.pbroadcastd.256(<4 x i32>, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_pbroadcastd_256(<4 x i32> %x0, <8 x i32> %x1, i8 %mask) { define <8 x i32>@test_int_x86_avx512_pbroadcastd_256(<4 x i32> %x0, <8 x i32> %x1, i8 %mask) {
; CHECK-LABEL: test_int_x86_avx512_pbroadcastd_256: ; CHECK-LABEL: test_int_x86_avx512_pbroadcastd_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpbroadcastd %xmm0, %ymm1 {%k1} ; CHECK-NEXT: vpbroadcastd %xmm0, %ymm1 {%k1}
; CHECK-NEXT: vpbroadcastd %xmm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpbroadcastd %xmm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vpbroadcastd %xmm0, %ymm0 ; CHECK-NEXT: vpbroadcastd %xmm0, %ymm0
; CHECK-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm0, %ymm2, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm2, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.pbroadcastd.256(<4 x i32> %x0, <8 x i32> %x1, i8 -1) %res = call <8 x i32> @llvm.x86.avx512.pbroadcastd.256(<4 x i32> %x0, <8 x i32> %x1, i8 -1)
%res1 = call <8 x i32> @llvm.x86.avx512.pbroadcastd.256(<4 x i32> %x0, <8 x i32> %x1, i8 %mask) %res1 = call <8 x i32> @llvm.x86.avx512.pbroadcastd.256(<4 x i32> %x0, <8 x i32> %x1, i8 %mask)
%res2 = call <8 x i32> @llvm.x86.avx512.pbroadcastd.256(<4 x i32> %x0, <8 x i32> zeroinitializer, i8 %mask) %res2 = call <8 x i32> @llvm.x86.avx512.pbroadcastd.256(<4 x i32> %x0, <8 x i32> zeroinitializer, i8 %mask)
%res3 = add <8 x i32> %res, %res1 %res3 = add <8 x i32> %res, %res1
%res4 = add <8 x i32> %res2, %res3 %res4 = add <8 x i32> %res2, %res3
ret <8 x i32> %res4 ret <8 x i32> %res4
} }
declare <4 x i32> @llvm.x86.avx512.pbroadcastd.128(<4 x i32>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.pbroadcastd.128(<4 x i32>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_pbroadcastd_128(<4 x i32> %x0, <4 x i32> %x1, i8 %mask) { define <4 x i32>@test_int_x86_avx512_pbroadcastd_128(<4 x i32> %x0, <4 x i32> %x1, i8 %mask) {
; CHECK-LABEL: test_int_x86_avx512_pbroadcastd_128: ; CHECK-LABEL: test_int_x86_avx512_pbroadcastd_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpbroadcastd %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpbroadcastd %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpbroadcastd %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpbroadcastd %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpbroadcastd %xmm0, %xmm0 ; CHECK-NEXT: vpbroadcastd %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.pbroadcastd.128(<4 x i32> %x0, <4 x i32> %x1, i8 -1) %res = call <4 x i32> @llvm.x86.avx512.pbroadcastd.128(<4 x i32> %x0, <4 x i32> %x1, i8 -1)
%res1 = call <4 x i32> @llvm.x86.avx512.pbroadcastd.128(<4 x i32> %x0, <4 x i32> %x1, i8 %mask) %res1 = call <4 x i32> @llvm.x86.avx512.pbroadcastd.128(<4 x i32> %x0, <4 x i32> %x1, i8 %mask)
%res2 = call <4 x i32> @llvm.x86.avx512.pbroadcastd.128(<4 x i32> %x0, <4 x i32> zeroinitializer, i8 %mask) %res2 = call <4 x i32> @llvm.x86.avx512.pbroadcastd.128(<4 x i32> %x0, <4 x i32> zeroinitializer, i8 %mask)
%res3 = add <4 x i32> %res, %res1 %res3 = add <4 x i32> %res, %res1
%res4 = add <4 x i32> %res2, %res3 %res4 = add <4 x i32> %res2, %res3
ret <4 x i32> %res4 ret <4 x i32> %res4
} }
declare <4 x i64> @llvm.x86.avx512.pbroadcastq.256(<2 x i64>, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.pbroadcastq.256(<2 x i64>, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_pbroadcastq_256(<2 x i64> %x0, <4 x i64> %x1, i8 %mask) { define <4 x i64>@test_int_x86_avx512_pbroadcastq_256(<2 x i64> %x0, <4 x i64> %x1, i8 %mask) {
; CHECK-LABEL: test_int_x86_avx512_pbroadcastq_256: ; CHECK-LABEL: test_int_x86_avx512_pbroadcastq_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpbroadcastq %xmm0, %ymm1 {%k1} ; CHECK-NEXT: vpbroadcastq %xmm0, %ymm1 {%k1}
; CHECK-NEXT: vpbroadcastq %xmm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpbroadcastq %xmm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vpbroadcastq %xmm0, %ymm0 ; CHECK-NEXT: vpbroadcastq %xmm0, %ymm0
; CHECK-NEXT: vpaddq %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vpaddq %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddq %ymm0, %ymm2, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm2, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.pbroadcastq.256(<2 x i64> %x0, <4 x i64> %x1,i8 -1) %res = call <4 x i64> @llvm.x86.avx512.pbroadcastq.256(<2 x i64> %x0, <4 x i64> %x1,i8 -1)
%res1 = call <4 x i64> @llvm.x86.avx512.pbroadcastq.256(<2 x i64> %x0, <4 x i64> %x1,i8 %mask) %res1 = call <4 x i64> @llvm.x86.avx512.pbroadcastq.256(<2 x i64> %x0, <4 x i64> %x1,i8 %mask)
%res2 = call <4 x i64> @llvm.x86.avx512.pbroadcastq.256(<2 x i64> %x0, <4 x i64> zeroinitializer,i8 %mask) %res2 = call <4 x i64> @llvm.x86.avx512.pbroadcastq.256(<2 x i64> %x0, <4 x i64> zeroinitializer,i8 %mask)
%res3 = add <4 x i64> %res, %res1 %res3 = add <4 x i64> %res, %res1
%res4 = add <4 x i64> %res2, %res3 %res4 = add <4 x i64> %res2, %res3
ret <4 x i64> %res4 ret <4 x i64> %res4
} }
declare <2 x i64> @llvm.x86.avx512.pbroadcastq.128(<2 x i64>, <2 x i64>, i8) declare <2 x i64> @llvm.x86.avx512.pbroadcastq.128(<2 x i64>, <2 x i64>, i8)
define <2 x i64>@test_int_x86_avx512_pbroadcastq_128(<2 x i64> %x0, <2 x i64> %x1, i8 %mask) { define <2 x i64>@test_int_x86_avx512_pbroadcastq_128(<2 x i64> %x0, <2 x i64> %x1, i8 %mask) {
; CHECK-LABEL: test_int_x86_avx512_pbroadcastq_128: ; CHECK-LABEL: test_int_x86_avx512_pbroadcastq_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpbroadcastq %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpbroadcastq %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpbroadcastq %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpbroadcastq %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpbroadcastq %xmm0, %xmm0 ; CHECK-NEXT: vpbroadcastq %xmm0, %xmm0
; CHECK-NEXT: vpaddq %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddq %xmm0, %xmm2, %xmm0 ; CHECK-NEXT: vpaddq %xmm0, %xmm2, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.pbroadcastq.128(<2 x i64> %x0, <2 x i64> %x1,i8 -1) %res = call <2 x i64> @llvm.x86.avx512.pbroadcastq.128(<2 x i64> %x0, <2 x i64> %x1,i8 -1)
%res1 = call <2 x i64> @llvm.x86.avx512.pbroadcastq.128(<2 x i64> %x0, <2 x i64> %x1,i8 %mask) %res1 = call <2 x i64> @llvm.x86.avx512.pbroadcastq.128(<2 x i64> %x0, <2 x i64> %x1,i8 %mask)
%res2 = call <2 x i64> @llvm.x86.avx512.pbroadcastq.128(<2 x i64> %x0, <2 x i64> zeroinitializer,i8 %mask) %res2 = call <2 x i64> @llvm.x86.avx512.pbroadcastq.128(<2 x i64> %x0, <2 x i64> zeroinitializer,i8 %mask)
%res3 = add <2 x i64> %res, %res1 %res3 = add <2 x i64> %res, %res1
%res4 = add <2 x i64> %res2, %res3 %res4 = add <2 x i64> %res2, %res3
ret <2 x i64> %res4 ret <2 x i64> %res4
} }
define <4 x float> @test_x86_vcvtph2ps_128(<8 x i16> %a0) { define <4 x float> @test_x86_vcvtph2ps_128(<8 x i16> %a0) {
; CHECK: test_x86_vcvtph2ps_128 ; CHECK: test_x86_vcvtph2ps_128
; CHECK: vcvtph2ps %xmm0, %xmm0 ; CHECK: vcvtph2ps %xmm0, %xmm0
%res = call <4 x float> @llvm.x86.avx512.mask.vcvtph2ps.128(<8 x i16> %a0, <4 x float> zeroinitializer, i8 -1) %res = call <4 x float> @llvm.x86.avx512.mask.vcvtph2ps.128(<8 x i16> %a0, <4 x float> zeroinitializer, i8 -1)
ret <4 x float> %res ret <4 x float> %res
} }
define <4 x float> @test_x86_vcvtph2ps_128_rrk(<8 x i16> %a0,<4 x float> %a1, i8 %mask) { define <4 x float> @test_x86_vcvtph2ps_128_rrk(<8 x i16> %a0,<4 x float> %a1, i8 %mask) {
; CHECK: test_x86_vcvtph2ps_128_rrk ; CHECK: test_x86_vcvtph2ps_128_rrk
; CHECK: vcvtph2ps %xmm0, %xmm1 {%k1} ; CHECK: vcvtph2ps %xmm0, %xmm1 {%k1}
%res = call <4 x float> @llvm.x86.avx512.mask.vcvtph2ps.128(<8 x i16> %a0, <4 x float> %a1, i8 %mask) %res = call <4 x float> @llvm.x86.avx512.mask.vcvtph2ps.128(<8 x i16> %a0, <4 x float> %a1, i8 %mask)
Show All 14 Linesdefine <8 x float> @test_x86_vcvtph2ps_256(<8 x i16> %a0) {
; CHECK: test_x86_vcvtph2ps_256 ; CHECK: test_x86_vcvtph2ps_256
; CHECK: vcvtph2ps %xmm0, %ymm0 ; CHECK: vcvtph2ps %xmm0, %ymm0
%res = call <8 x float> @llvm.x86.avx512.mask.vcvtph2ps.256(<8 x i16> %a0, <8 x float> zeroinitializer, i8 -1) %res = call <8 x float> @llvm.x86.avx512.mask.vcvtph2ps.256(<8 x i16> %a0, <8 x float> zeroinitializer, i8 -1)
ret <8 x float> %res ret <8 x float> %res
} }
define <8 x float> @test_x86_vcvtph2ps_256_rrk(<8 x i16> %a0,<8 x float> %a1, i8 %mask) { define <8 x float> @test_x86_vcvtph2ps_256_rrk(<8 x i16> %a0,<8 x float> %a1, i8 %mask) {
; CHECK: test_x86_vcvtph2ps_256_rrk ; CHECK: test_x86_vcvtph2ps_256_rrk
; CHECK: vcvtph2ps %xmm0, %ymm1 {%k1} ; CHECK: vcvtph2ps %xmm0, %ymm1 {%k1}
%res = call <8 x float> @llvm.x86.avx512.mask.vcvtph2ps.256(<8 x i16> %a0, <8 x float> %a1, i8 %mask) %res = call <8 x float> @llvm.x86.avx512.mask.vcvtph2ps.256(<8 x i16> %a0, <8 x float> %a1, i8 %mask)
ret <8 x float> %res ret <8 x float> %res
} }
define <8 x float> @test_x86_vcvtph2ps_256_rrkz(<8 x i16> %a0, i8 %mask) { define <8 x float> @test_x86_vcvtph2ps_256_rrkz(<8 x i16> %a0, i8 %mask) {
; CHECK: test_x86_vcvtph2ps_256_rrkz ; CHECK: test_x86_vcvtph2ps_256_rrkz
; CHECK: vcvtph2ps %xmm0, %ymm0 {%k1} {z} ; CHECK: vcvtph2ps %xmm0, %ymm0 {%k1} {z}
%res = call <8 x float> @llvm.x86.avx512.mask.vcvtph2ps.256(<8 x i16> %a0, <8 x float> zeroinitializer, i8 %mask) %res = call <8 x float> @llvm.x86.avx512.mask.vcvtph2ps.256(<8 x i16> %a0, <8 x float> zeroinitializer, i8 %mask)
Show All 21 Lines
declare <8 x i16> @llvm.x86.avx512.mask.vcvtps2ph.256(<8 x float>, i32, <8 x i16>, i8) nounwind readonly declare <8 x i16> @llvm.x86.avx512.mask.vcvtps2ph.256(<8 x float>, i32, <8 x i16>, i8) nounwind readonly
declare <4 x float> @llvm.x86.avx512.mask.movsldup.128(<4 x float>, <4 x float>, i8) declare <4 x float> @llvm.x86.avx512.mask.movsldup.128(<4 x float>, <4 x float>, i8)
define <4 x float>@test_int_x86_avx512_mask_movsldup_128(<4 x float> %x0, <4 x float> %x1, i8 %x2) { define <4 x float>@test_int_x86_avx512_mask_movsldup_128(<4 x float> %x0, <4 x float> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_movsldup_128: ; CHECK-LABEL: test_int_x86_avx512_mask_movsldup_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovsldup %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vmovsldup %xmm0, %xmm1 {%k1}
; CHECK-NEXT: ## xmm1 = xmm0[0,0,2,2] ; CHECK-NEXT: ## xmm1 = xmm0[0,0,2,2]
; CHECK-NEXT: vmovsldup %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vmovsldup %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: ## xmm2 = xmm0[0,0,2,2] ; CHECK-NEXT: ## xmm2 = xmm0[0,0,2,2]
; CHECK-NEXT: vmovsldup %xmm0, %xmm0 ; CHECK-NEXT: vmovsldup %xmm0, %xmm0
; CHECK-NEXT: ## xmm0 = xmm0[0,0,2,2] ; CHECK-NEXT: ## xmm0 = xmm0[0,0,2,2]
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0
; CHECK-NEXT: vaddps %xmm0, %xmm2, %xmm0 ; CHECK-NEXT: vaddps %xmm0, %xmm2, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.movsldup.128(<4 x float> %x0, <4 x float> %x1, i8 %x2) %res = call <4 x float> @llvm.x86.avx512.mask.movsldup.128(<4 x float> %x0, <4 x float> %x1, i8 %x2)
%res1 = call <4 x float> @llvm.x86.avx512.mask.movsldup.128(<4 x float> %x0, <4 x float> %x1, i8 -1) %res1 = call <4 x float> @llvm.x86.avx512.mask.movsldup.128(<4 x float> %x0, <4 x float> %x1, i8 -1)
%res2 = call <4 x float> @llvm.x86.avx512.mask.movsldup.128(<4 x float> %x0, <4 x float> zeroinitializer, i8 %x2) %res2 = call <4 x float> @llvm.x86.avx512.mask.movsldup.128(<4 x float> %x0, <4 x float> zeroinitializer, i8 %x2)
%res3 = fadd <4 x float> %res, %res1 %res3 = fadd <4 x float> %res, %res1
%res4 = fadd <4 x float> %res2, %res3 %res4 = fadd <4 x float> %res2, %res3
ret <4 x float> %res4 ret <4 x float> %res4
} }
declare <8 x float> @llvm.x86.avx512.mask.movsldup.256(<8 x float>, <8 x float>, i8) declare <8 x float> @llvm.x86.avx512.mask.movsldup.256(<8 x float>, <8 x float>, i8)
define <8 x float>@test_int_x86_avx512_mask_movsldup_256(<8 x float> %x0, <8 x float> %x1, i8 %x2) { define <8 x float>@test_int_x86_avx512_mask_movsldup_256(<8 x float> %x0, <8 x float> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_movsldup_256: ; CHECK-LABEL: test_int_x86_avx512_mask_movsldup_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovsldup %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vmovsldup %ymm0, %ymm1 {%k1}
; CHECK-NEXT: ## ymm1 = ymm0[0,0,2,2,4,4,6,6] ; CHECK-NEXT: ## ymm1 = ymm0[0,0,2,2,4,4,6,6]
; CHECK-NEXT: vmovsldup %ymm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vmovsldup %ymm0, %ymm2 {%k1} {z}
; CHECK-NEXT: ## ymm2 = ymm0[0,0,2,2,4,4,6,6] ; CHECK-NEXT: ## ymm2 = ymm0[0,0,2,2,4,4,6,6]
; CHECK-NEXT: vmovsldup %ymm0, %ymm0 ; CHECK-NEXT: vmovsldup %ymm0, %ymm0
; CHECK-NEXT: ## ymm0 = ymm0[0,0,2,2,4,4,6,6] ; CHECK-NEXT: ## ymm0 = ymm0[0,0,2,2,4,4,6,6]
; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0
; CHECK-NEXT: vaddps %ymm0, %ymm2, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm2, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx512.mask.movsldup.256(<8 x float> %x0, <8 x float> %x1, i8 %x2) %res = call <8 x float> @llvm.x86.avx512.mask.movsldup.256(<8 x float> %x0, <8 x float> %x1, i8 %x2)
%res1 = call <8 x float> @llvm.x86.avx512.mask.movsldup.256(<8 x float> %x0, <8 x float> %x1, i8 -1) %res1 = call <8 x float> @llvm.x86.avx512.mask.movsldup.256(<8 x float> %x0, <8 x float> %x1, i8 -1)
%res2 = call <8 x float> @llvm.x86.avx512.mask.movsldup.256(<8 x float> %x0, <8 x float> zeroinitializer, i8 %x2) %res2 = call <8 x float> @llvm.x86.avx512.mask.movsldup.256(<8 x float> %x0, <8 x float> zeroinitializer, i8 %x2)
%res3 = fadd <8 x float> %res, %res1 %res3 = fadd <8 x float> %res, %res1
%res4 = fadd <8 x float> %res2, %res3 %res4 = fadd <8 x float> %res2, %res3
ret <8 x float> %res4 ret <8 x float> %res4
} }
declare <4 x float> @llvm.x86.avx512.mask.movshdup.128(<4 x float>, <4 x float>, i8) declare <4 x float> @llvm.x86.avx512.mask.movshdup.128(<4 x float>, <4 x float>, i8)
define <4 x float>@test_int_x86_avx512_mask_movshdup_128(<4 x float> %x0, <4 x float> %x1, i8 %x2) { define <4 x float>@test_int_x86_avx512_mask_movshdup_128(<4 x float> %x0, <4 x float> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_movshdup_128: ; CHECK-LABEL: test_int_x86_avx512_mask_movshdup_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovshdup %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vmovshdup %xmm0, %xmm1 {%k1}
; CHECK-NEXT: ## xmm1 = xmm0[1,1,3,3] ; CHECK-NEXT: ## xmm1 = xmm0[1,1,3,3]
; CHECK-NEXT: vmovshdup %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vmovshdup %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: ## xmm2 = xmm0[1,1,3,3] ; CHECK-NEXT: ## xmm2 = xmm0[1,1,3,3]
; CHECK-NEXT: vmovshdup %xmm0, %xmm0 ; CHECK-NEXT: vmovshdup %xmm0, %xmm0
; CHECK-NEXT: ## xmm0 = xmm0[1,1,3,3] ; CHECK-NEXT: ## xmm0 = xmm0[1,1,3,3]
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0
; CHECK-NEXT: vaddps %xmm0, %xmm2, %xmm0 ; CHECK-NEXT: vaddps %xmm0, %xmm2, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.movshdup.128(<4 x float> %x0, <4 x float> %x1, i8 %x2) %res = call <4 x float> @llvm.x86.avx512.mask.movshdup.128(<4 x float> %x0, <4 x float> %x1, i8 %x2)
%res1 = call <4 x float> @llvm.x86.avx512.mask.movshdup.128(<4 x float> %x0, <4 x float> %x1, i8 -1) %res1 = call <4 x float> @llvm.x86.avx512.mask.movshdup.128(<4 x float> %x0, <4 x float> %x1, i8 -1)
%res2 = call <4 x float> @llvm.x86.avx512.mask.movshdup.128(<4 x float> %x0, <4 x float> zeroinitializer, i8 %x2) %res2 = call <4 x float> @llvm.x86.avx512.mask.movshdup.128(<4 x float> %x0, <4 x float> zeroinitializer, i8 %x2)
%res3 = fadd <4 x float> %res, %res1 %res3 = fadd <4 x float> %res, %res1
%res4 = fadd <4 x float> %res2, %res3 %res4 = fadd <4 x float> %res2, %res3
ret <4 x float> %res4 ret <4 x float> %res4
} }
declare <8 x float> @llvm.x86.avx512.mask.movshdup.256(<8 x float>, <8 x float>, i8) declare <8 x float> @llvm.x86.avx512.mask.movshdup.256(<8 x float>, <8 x float>, i8)
define <8 x float>@test_int_x86_avx512_mask_movshdup_256(<8 x float> %x0, <8 x float> %x1, i8 %x2) { define <8 x float>@test_int_x86_avx512_mask_movshdup_256(<8 x float> %x0, <8 x float> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_movshdup_256: ; CHECK-LABEL: test_int_x86_avx512_mask_movshdup_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovshdup %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vmovshdup %ymm0, %ymm1 {%k1}
; CHECK-NEXT: ## ymm1 = ymm0[1,1,3,3,5,5,7,7] ; CHECK-NEXT: ## ymm1 = ymm0[1,1,3,3,5,5,7,7]
; CHECK-NEXT: vmovshdup %ymm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vmovshdup %ymm0, %ymm2 {%k1} {z}
; CHECK-NEXT: ## ymm2 = ymm0[1,1,3,3,5,5,7,7] ; CHECK-NEXT: ## ymm2 = ymm0[1,1,3,3,5,5,7,7]
; CHECK-NEXT: vmovshdup %ymm0, %ymm0 ; CHECK-NEXT: vmovshdup %ymm0, %ymm0
; CHECK-NEXT: ## ymm0 = ymm0[1,1,3,3,5,5,7,7] ; CHECK-NEXT: ## ymm0 = ymm0[1,1,3,3,5,5,7,7]
; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0
; CHECK-NEXT: vaddps %ymm0, %ymm2, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm2, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx512.mask.movshdup.256(<8 x float> %x0, <8 x float> %x1, i8 %x2) %res = call <8 x float> @llvm.x86.avx512.mask.movshdup.256(<8 x float> %x0, <8 x float> %x1, i8 %x2)
%res1 = call <8 x float> @llvm.x86.avx512.mask.movshdup.256(<8 x float> %x0, <8 x float> %x1, i8 -1) %res1 = call <8 x float> @llvm.x86.avx512.mask.movshdup.256(<8 x float> %x0, <8 x float> %x1, i8 -1)
%res2 = call <8 x float> @llvm.x86.avx512.mask.movshdup.256(<8 x float> %x0, <8 x float> zeroinitializer, i8 %x2) %res2 = call <8 x float> @llvm.x86.avx512.mask.movshdup.256(<8 x float> %x0, <8 x float> zeroinitializer, i8 %x2)
%res3 = fadd <8 x float> %res, %res1 %res3 = fadd <8 x float> %res, %res1
%res4 = fadd <8 x float> %res2, %res3 %res4 = fadd <8 x float> %res2, %res3
ret <8 x float> %res4 ret <8 x float> %res4
} }
declare <2 x double> @llvm.x86.avx512.mask.movddup.128(<2 x double>, <2 x double>, i8) declare <2 x double> @llvm.x86.avx512.mask.movddup.128(<2 x double>, <2 x double>, i8)
define <2 x double>@test_int_x86_avx512_mask_movddup_128(<2 x double> %x0, <2 x double> %x1, i8 %x2) { define <2 x double>@test_int_x86_avx512_mask_movddup_128(<2 x double> %x0, <2 x double> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_movddup_128: ; CHECK-LABEL: test_int_x86_avx512_mask_movddup_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovddup %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vmovddup %xmm0, %xmm1 {%k1}
; CHECK-NEXT: ## xmm1 = xmm0[0,0] ; CHECK-NEXT: ## xmm1 = xmm0[0,0]
; CHECK-NEXT: vmovddup %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vmovddup %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: ## xmm2 = xmm0[0,0] ; CHECK-NEXT: ## xmm2 = xmm0[0,0]
; CHECK-NEXT: vmovddup %xmm0, %xmm0 ; CHECK-NEXT: vmovddup %xmm0, %xmm0
; CHECK-NEXT: ## xmm0 = xmm0[0,0] ; CHECK-NEXT: ## xmm0 = xmm0[0,0]
; CHECK-NEXT: vaddpd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vaddpd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: vaddpd %xmm0, %xmm2, %xmm0 ; CHECK-NEXT: vaddpd %xmm0, %xmm2, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.movddup.128(<2 x double> %x0, <2 x double> %x1, i8 %x2) %res = call <2 x double> @llvm.x86.avx512.mask.movddup.128(<2 x double> %x0, <2 x double> %x1, i8 %x2)
%res1 = call <2 x double> @llvm.x86.avx512.mask.movddup.128(<2 x double> %x0, <2 x double> %x1, i8 -1) %res1 = call <2 x double> @llvm.x86.avx512.mask.movddup.128(<2 x double> %x0, <2 x double> %x1, i8 -1)
%res2 = call <2 x double> @llvm.x86.avx512.mask.movddup.128(<2 x double> %x0, <2 x double> zeroinitializer, i8 %x2) %res2 = call <2 x double> @llvm.x86.avx512.mask.movddup.128(<2 x double> %x0, <2 x double> zeroinitializer, i8 %x2)
%res3 = fadd <2 x double> %res, %res1 %res3 = fadd <2 x double> %res, %res1
%res4 = fadd <2 x double> %res2, %res3 %res4 = fadd <2 x double> %res2, %res3
ret <2 x double> %res4 ret <2 x double> %res4
} }
declare <4 x double> @llvm.x86.avx512.mask.movddup.256(<4 x double>, <4 x double>, i8) declare <4 x double> @llvm.x86.avx512.mask.movddup.256(<4 x double>, <4 x double>, i8)
define <4 x double>@test_int_x86_avx512_mask_movddup_256(<4 x double> %x0, <4 x double> %x1, i8 %x2) { define <4 x double>@test_int_x86_avx512_mask_movddup_256(<4 x double> %x0, <4 x double> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_movddup_256: ; CHECK-LABEL: test_int_x86_avx512_mask_movddup_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovddup %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vmovddup %ymm0, %ymm1 {%k1}
; CHECK-NEXT: ## ymm1 = ymm0[0,0,2,2] ; CHECK-NEXT: ## ymm1 = ymm0[0,0,2,2]
; CHECK-NEXT: vmovddup %ymm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vmovddup %ymm0, %ymm2 {%k1} {z}
; CHECK-NEXT: ## ymm2 = ymm0[0,0,2,2] ; CHECK-NEXT: ## ymm2 = ymm0[0,0,2,2]
; CHECK-NEXT: vmovddup %ymm0, %ymm0 ; CHECK-NEXT: vmovddup %ymm0, %ymm0
; CHECK-NEXT: ## ymm0 = ymm0[0,0,2,2] ; CHECK-NEXT: ## ymm0 = ymm0[0,0,2,2]
; CHECK-NEXT: vaddpd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vaddpd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: vaddpd %ymm0, %ymm2, %ymm0 ; CHECK-NEXT: vaddpd %ymm0, %ymm2, %ymm0
▲ Show 20 Lines • Show All 184 Lines • ▼ Show 20 Lines; CHECK: vrcp14pd %xmm0, %xmm1 {%k1}
ret <2 x double> %res ret <2 x double> %res
} }
declare <4 x double> @llvm.x86.avx512.rcp14.pd.256(<4 x double>, <4 x double>, i8) nounwind readnone declare <4 x double> @llvm.x86.avx512.rcp14.pd.256(<4 x double>, <4 x double>, i8) nounwind readnone
declare <2 x double> @llvm.x86.avx512.rcp14.pd.128(<2 x double>, <2 x double>, i8) nounwind readnone declare <2 x double> @llvm.x86.avx512.rcp14.pd.128(<2 x double>, <2 x double>, i8) nounwind readnone
define <4 x double> @test_x86_vbroadcast_sd_pd_256(<2 x double> %a0, <4 x double> %a1, i8 %mask ) { define <4 x double> @test_x86_vbroadcast_sd_pd_256(<2 x double> %a0, <4 x double> %a1, i8 %mask ) {
; CHECK-LABEL: test_x86_vbroadcast_sd_pd_256: ; CHECK-LABEL: test_x86_vbroadcast_sd_pd_256:
; CHECK: kmovw %eax, %k1 ; CHECK: kmovw %edi, %k1
; CHECK-NEXT: vbroadcastsd %xmm0, %ymm1 {%k1} ; CHECK-NEXT: vbroadcastsd %xmm0, %ymm1 {%k1}
; CHECK-NEXT: vbroadcastsd %xmm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vbroadcastsd %xmm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vbroadcastsd %xmm0, %ymm0 ; CHECK-NEXT: vbroadcastsd %xmm0, %ymm0
; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0
%res = call <4 x double> @llvm.x86.avx512.mask.broadcast.sd.pd.256(<2 x double> %a0, <4 x double> zeroinitializer, i8 -1) %res = call <4 x double> @llvm.x86.avx512.mask.broadcast.sd.pd.256(<2 x double> %a0, <4 x double> zeroinitializer, i8 -1)
%res1 = call <4 x double> @llvm.x86.avx512.mask.broadcast.sd.pd.256(<2 x double> %a0, <4 x double> %a1, i8 %mask) %res1 = call <4 x double> @llvm.x86.avx512.mask.broadcast.sd.pd.256(<2 x double> %a0, <4 x double> %a1, i8 %mask)
%res2 = call <4 x double> @llvm.x86.avx512.mask.broadcast.sd.pd.256(<2 x double> %a0, <4 x double> zeroinitializer, i8 %mask) %res2 = call <4 x double> @llvm.x86.avx512.mask.broadcast.sd.pd.256(<2 x double> %a0, <4 x double> zeroinitializer, i8 %mask)
%res3 = fadd <4 x double> %res, %res1 %res3 = fadd <4 x double> %res, %res1
%res4 = fadd <4 x double> %res2, %res3 %res4 = fadd <4 x double> %res2, %res3
ret <4 x double> %res4 ret <4 x double> %res4
} }
declare <4 x double> @llvm.x86.avx512.mask.broadcast.sd.pd.256(<2 x double>, <4 x double>, i8) nounwind readonly declare <4 x double> @llvm.x86.avx512.mask.broadcast.sd.pd.256(<2 x double>, <4 x double>, i8) nounwind readonly
define <8 x float> @test_x86_vbroadcast_ss_ps_256(<4 x float> %a0, <8 x float> %a1, i8 %mask ) { define <8 x float> @test_x86_vbroadcast_ss_ps_256(<4 x float> %a0, <8 x float> %a1, i8 %mask ) {
; CHECK-LABEL: test_x86_vbroadcast_ss_ps_256: ; CHECK-LABEL: test_x86_vbroadcast_ss_ps_256:
; CHECK: kmovw %eax, %k1 ; CHECK: kmovw %edi, %k1
; CHECK-NEXT: vbroadcastss %xmm0, %ymm1 {%k1} ; CHECK-NEXT: vbroadcastss %xmm0, %ymm1 {%k1}
; CHECK-NEXT: vbroadcastss %xmm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vbroadcastss %xmm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vbroadcastss %xmm0, %ymm0 ; CHECK-NEXT: vbroadcastss %xmm0, %ymm0
; CHECK-NEXT: vaddps %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vaddps %ymm1, %ymm0, %ymm0
%res = call <8 x float> @llvm.x86.avx512.mask.broadcast.ss.ps.256(<4 x float> %a0, <8 x float> zeroinitializer, i8 -1) %res = call <8 x float> @llvm.x86.avx512.mask.broadcast.ss.ps.256(<4 x float> %a0, <8 x float> zeroinitializer, i8 -1)
%res1 = call <8 x float> @llvm.x86.avx512.mask.broadcast.ss.ps.256(<4 x float> %a0, <8 x float> %a1, i8 %mask) %res1 = call <8 x float> @llvm.x86.avx512.mask.broadcast.ss.ps.256(<4 x float> %a0, <8 x float> %a1, i8 %mask)
%res2 = call <8 x float> @llvm.x86.avx512.mask.broadcast.ss.ps.256(<4 x float> %a0, <8 x float> zeroinitializer, i8 %mask) %res2 = call <8 x float> @llvm.x86.avx512.mask.broadcast.ss.ps.256(<4 x float> %a0, <8 x float> zeroinitializer, i8 %mask)
%res3 = fadd <8 x float> %res, %res1 %res3 = fadd <8 x float> %res, %res1
%res4 = fadd <8 x float> %res2, %res3 %res4 = fadd <8 x float> %res2, %res3
ret <8 x float> %res4 ret <8 x float> %res4
} }
declare <8 x float> @llvm.x86.avx512.mask.broadcast.ss.ps.256(<4 x float>, <8 x float>, i8) nounwind readonly declare <8 x float> @llvm.x86.avx512.mask.broadcast.ss.ps.256(<4 x float>, <8 x float>, i8) nounwind readonly
define <4 x float> @test_x86_vbroadcast_ss_ps_128(<4 x float> %a0, <4 x float> %a1, i8 %mask ) { define <4 x float> @test_x86_vbroadcast_ss_ps_128(<4 x float> %a0, <4 x float> %a1, i8 %mask ) {
; CHECK-LABEL: test_x86_vbroadcast_ss_ps_128: ; CHECK-LABEL: test_x86_vbroadcast_ss_ps_128:
; CHECK: kmovw %eax, %k1 ; CHECK: kmovw %edi, %k1
; CHECK-NEXT: vbroadcastss %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vbroadcastss %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vbroadcastss %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vbroadcastss %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vbroadcastss %xmm0, %xmm0 ; CHECK-NEXT: vbroadcastss %xmm0, %xmm0
; CHECK-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vaddps %xmm1, %xmm0, %xmm0
%res = call <4 x float> @llvm.x86.avx512.mask.broadcast.ss.ps.128(<4 x float> %a0, <4 x float> zeroinitializer, i8 -1) %res = call <4 x float> @llvm.x86.avx512.mask.broadcast.ss.ps.128(<4 x float> %a0, <4 x float> zeroinitializer, i8 -1)
%res1 = call <4 x float> @llvm.x86.avx512.mask.broadcast.ss.ps.128(<4 x float> %a0, <4 x float> %a1, i8 %mask) %res1 = call <4 x float> @llvm.x86.avx512.mask.broadcast.ss.ps.128(<4 x float> %a0, <4 x float> %a1, i8 %mask)
%res2 = call <4 x float> @llvm.x86.avx512.mask.broadcast.ss.ps.128(<4 x float> %a0, <4 x float> zeroinitializer, i8 %mask) %res2 = call <4 x float> @llvm.x86.avx512.mask.broadcast.ss.ps.128(<4 x float> %a0, <4 x float> zeroinitializer, i8 %mask)
%res3 = fadd <4 x float> %res, %res1 %res3 = fadd <4 x float> %res, %res1
%res4 = fadd <4 x float> %res2, %res3 %res4 = fadd <4 x float> %res2, %res3
ret <4 x float> %res4 ret <4 x float> %res4
} }
declare <4 x float> @llvm.x86.avx512.mask.broadcast.ss.ps.128(<4 x float>, <4 x float>, i8) nounwind readonly declare <4 x float> @llvm.x86.avx512.mask.broadcast.ss.ps.128(<4 x float>, <4 x float>, i8) nounwind readonly
declare <8 x float> @llvm.x86.avx512.mask.broadcastf32x4.256(<4 x float>, <8 x float>, i8) declare <8 x float> @llvm.x86.avx512.mask.broadcastf32x4.256(<4 x float>, <8 x float>, i8)
define <8 x float>@test_int_x86_avx512_mask_broadcastf32x4_256(<4 x float> %x0, <8 x float> %x2, i8 %mask) { define <8 x float>@test_int_x86_avx512_mask_broadcastf32x4_256(<4 x float> %x0, <8 x float> %x2, i8 %mask) {
; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf32x4_256: ; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf32x4_256:
; CHECK: kmovw %eax, %k1 ; CHECK: kmovw %edi, %k1
; CHECK: vshuff32x4 $0, %ymm0, %ymm0, %ymm2 {%k1} {z} ; CHECK: vshuff32x4 $0, %ymm0, %ymm0, %ymm2 {%k1} {z}
; CHECK: vshuff32x4 $0, %ymm0, %ymm0, %ymm1 {%k1} ; CHECK: vshuff32x4 $0, %ymm0, %ymm0, %ymm1 {%k1}
; CHECK: vshuff32x4 $0, %ymm0, %ymm0, %ymm0 ; CHECK: vshuff32x4 $0, %ymm0, %ymm0, %ymm0
; CHECK: vaddps %ymm1, %ymm0, %ymm0 ; CHECK: vaddps %ymm1, %ymm0, %ymm0
; CHECK: vaddps %ymm0, %ymm2, %ymm0 ; CHECK: vaddps %ymm0, %ymm2, %ymm0
%res1 = call <8 x float> @llvm.x86.avx512.mask.broadcastf32x4.256(<4 x float> %x0, <8 x float> %x2, i8 -1) %res1 = call <8 x float> @llvm.x86.avx512.mask.broadcastf32x4.256(<4 x float> %x0, <8 x float> %x2, i8 -1)
%res2 = call <8 x float> @llvm.x86.avx512.mask.broadcastf32x4.256(<4 x float> %x0, <8 x float> %x2, i8 %mask) %res2 = call <8 x float> @llvm.x86.avx512.mask.broadcastf32x4.256(<4 x float> %x0, <8 x float> %x2, i8 %mask)
%res3 = call <8 x float> @llvm.x86.avx512.mask.broadcastf32x4.256(<4 x float> %x0, <8 x float> zeroinitializer, i8 %mask) %res3 = call <8 x float> @llvm.x86.avx512.mask.broadcastf32x4.256(<4 x float> %x0, <8 x float> zeroinitializer, i8 %mask)
%res4 = fadd <8 x float> %res1, %res2 %res4 = fadd <8 x float> %res1, %res2
%res5 = fadd <8 x float> %res3, %res4 %res5 = fadd <8 x float> %res3, %res4
ret <8 x float> %res5 ret <8 x float> %res5
} }
declare <8 x i32> @llvm.x86.avx512.mask.broadcasti32x4.256(<4 x i32>, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.broadcasti32x4.256(<4 x i32>, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_broadcasti32x4_256(<4 x i32> %x0, <8 x i32> %x2, i8 %mask) { define <8 x i32>@test_int_x86_avx512_mask_broadcasti32x4_256(<4 x i32> %x0, <8 x i32> %x2, i8 %mask) {
; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti32x4_256: ; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti32x4_256:
; CHECK: kmovw %eax, %k1 ; CHECK: kmovw %edi, %k1
; CHECK: vshufi32x4 $0, %ymm0, %ymm0, %ymm2 {%k1} {z} ; CHECK: vshufi32x4 $0, %ymm0, %ymm0, %ymm2 {%k1} {z}
; CHECK: vshufi32x4 $0, %ymm0, %ymm0, %ymm1 {%k1} ; CHECK: vshufi32x4 $0, %ymm0, %ymm0, %ymm1 {%k1}
; CHECK: vshufi32x4 $0, %ymm0, %ymm0, %ymm0 ; CHECK: vshufi32x4 $0, %ymm0, %ymm0, %ymm0
; CHECK: vpaddd %ymm1, %ymm0, %ymm0 ; CHECK: vpaddd %ymm1, %ymm0, %ymm0
; CHECK: vpaddd %ymm0, %ymm2, %ymm0 ; CHECK: vpaddd %ymm0, %ymm2, %ymm0
%res1 = call <8 x i32> @llvm.x86.avx512.mask.broadcasti32x4.256(<4 x i32> %x0, <8 x i32> %x2, i8 -1) %res1 = call <8 x i32> @llvm.x86.avx512.mask.broadcasti32x4.256(<4 x i32> %x0, <8 x i32> %x2, i8 -1)
%res2 = call <8 x i32> @llvm.x86.avx512.mask.broadcasti32x4.256(<4 x i32> %x0, <8 x i32> %x2, i8 %mask) %res2 = call <8 x i32> @llvm.x86.avx512.mask.broadcasti32x4.256(<4 x i32> %x0, <8 x i32> %x2, i8 %mask)
%res3 = call <8 x i32> @llvm.x86.avx512.mask.broadcasti32x4.256(<4 x i32> %x0, <8 x i32> zeroinitializer, i8 %mask) %res3 = call <8 x i32> @llvm.x86.avx512.mask.broadcasti32x4.256(<4 x i32> %x0, <8 x i32> zeroinitializer, i8 %mask)
%res4 = add <8 x i32> %res1, %res2 %res4 = add <8 x i32> %res1, %res2
%res5 = add <8 x i32> %res3, %res4 %res5 = add <8 x i32> %res3, %res4
ret <8 x i32> %res5 ret <8 x i32> %res5
} }
declare <2 x i64> @llvm.x86.avx512.mask.psrl.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8) declare <2 x i64> @llvm.x86.avx512.mask.psrl.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)
define <2 x i64>@test_int_x86_avx512_mask_psrl_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) { define <2 x i64>@test_int_x86_avx512_mask_psrl_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psrl_q_128: ; CHECK-LABEL: test_int_x86_avx512_mask_psrl_q_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsrlq %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vpsrlq %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vpsrlq %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: vpsrlq %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: vpsrlq %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpsrlq %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddq %xmm0, %xmm2, %xmm0 ; CHECK-NEXT: vpaddq %xmm0, %xmm2, %xmm0
; CHECK-NEXT: vpaddq %xmm3, %xmm0, %xmm0 ; CHECK-NEXT: vpaddq %xmm3, %xmm0, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.mask.psrl.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) %res = call <2 x i64> @llvm.x86.avx512.mask.psrl.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)
%res1 = call <2 x i64> @llvm.x86.avx512.mask.psrl.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1) %res1 = call <2 x i64> @llvm.x86.avx512.mask.psrl.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)
%res2 = call <2 x i64> @llvm.x86.avx512.mask.psrl.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3) %res2 = call <2 x i64> @llvm.x86.avx512.mask.psrl.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)
%res3 = add <2 x i64> %res, %res1 %res3 = add <2 x i64> %res, %res1
%res4 = add <2 x i64> %res3, %res2 %res4 = add <2 x i64> %res3, %res2
ret <2 x i64> %res4 ret <2 x i64> %res4
} }
declare <4 x i64> @llvm.x86.avx512.mask.psrl.q.256(<4 x i64>, <2 x i64>, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.psrl.q.256(<4 x i64>, <2 x i64>, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_mask_psrl_q_256(<4 x i64> %x0, <2 x i64> %x1, <4 x i64> %x2, i8 %x3) { define <4 x i64>@test_int_x86_avx512_mask_psrl_q_256(<4 x i64> %x0, <2 x i64> %x1, <4 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psrl_q_256: ; CHECK-LABEL: test_int_x86_avx512_mask_psrl_q_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsrlq %xmm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vpsrlq %xmm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: vpsrlq %xmm1, %ymm0, %ymm3 {%k1} {z} ; CHECK-NEXT: vpsrlq %xmm1, %ymm0, %ymm3 {%k1} {z}
; CHECK-NEXT: vpsrlq %xmm1, %ymm0, %ymm0 ; CHECK-NEXT: vpsrlq %xmm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddq %ymm0, %ymm2, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm2, %ymm0
; CHECK-NEXT: vpaddq %ymm3, %ymm0, %ymm0 ; CHECK-NEXT: vpaddq %ymm3, %ymm0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.psrl.q.256(<4 x i64> %x0, <2 x i64> %x1, <4 x i64> %x2, i8 %x3) %res = call <4 x i64> @llvm.x86.avx512.mask.psrl.q.256(<4 x i64> %x0, <2 x i64> %x1, <4 x i64> %x2, i8 %x3)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.psrl.q.256(<4 x i64> %x0, <2 x i64> %x1, <4 x i64> %x2, i8 -1) %res1 = call <4 x i64> @llvm.x86.avx512.mask.psrl.q.256(<4 x i64> %x0, <2 x i64> %x1, <4 x i64> %x2, i8 -1)
%res2 = call <4 x i64> @llvm.x86.avx512.mask.psrl.q.256(<4 x i64> %x0, <2 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3) %res2 = call <4 x i64> @llvm.x86.avx512.mask.psrl.q.256(<4 x i64> %x0, <2 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)
%res3 = add <4 x i64> %res, %res1 %res3 = add <4 x i64> %res, %res1
%res4 = add <4 x i64> %res3, %res2 %res4 = add <4 x i64> %res3, %res2
ret <4 x i64> %res4 ret <4 x i64> %res4
} }
declare <2 x i64> @llvm.x86.avx512.mask.psrl.qi.128(<2 x i64>, i8, <2 x i64>, i8) declare <2 x i64> @llvm.x86.avx512.mask.psrl.qi.128(<2 x i64>, i8, <2 x i64>, i8)
define <2 x i64>@test_int_x86_avx512_mask_psrl_qi_128(<2 x i64> %x0, i8 %x1, <2 x i64> %x2, i8 %x3) { define <2 x i64>@test_int_x86_avx512_mask_psrl_qi_128(<2 x i64> %x0, i8 %x1, <2 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psrl_qi_128: ; CHECK-LABEL: test_int_x86_avx512_mask_psrl_qi_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsrlq $255, %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpsrlq $255, %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpsrlq $255, %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpsrlq $255, %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpsrlq $255, %xmm0, %xmm0 ; CHECK-NEXT: vpsrlq $255, %xmm0, %xmm0
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
; CHECK-NEXT: vpaddq %xmm0, %xmm2, %xmm0 ; CHECK-NEXT: vpaddq %xmm0, %xmm2, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.mask.psrl.qi.128(<2 x i64> %x0, i8 255, <2 x i64> %x2, i8 %x3) %res = call <2 x i64> @llvm.x86.avx512.mask.psrl.qi.128(<2 x i64> %x0, i8 255, <2 x i64> %x2, i8 %x3)
%res1 = call <2 x i64> @llvm.x86.avx512.mask.psrl.qi.128(<2 x i64> %x0, i8 255, <2 x i64> %x2, i8 -1) %res1 = call <2 x i64> @llvm.x86.avx512.mask.psrl.qi.128(<2 x i64> %x0, i8 255, <2 x i64> %x2, i8 -1)
%res2 = call <2 x i64> @llvm.x86.avx512.mask.psrl.qi.128(<2 x i64> %x0, i8 255, <2 x i64> zeroinitializer, i8 %x3) %res2 = call <2 x i64> @llvm.x86.avx512.mask.psrl.qi.128(<2 x i64> %x0, i8 255, <2 x i64> zeroinitializer, i8 %x3)
%res3 = add <2 x i64> %res, %res1 %res3 = add <2 x i64> %res, %res1
%res4 = add <2 x i64> %res2, %res3 %res4 = add <2 x i64> %res2, %res3
ret <2 x i64> %res4 ret <2 x i64> %res4
} }
declare <4 x i64> @llvm.x86.avx512.mask.psrl.qi.256(<4 x i64>, i8, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.psrl.qi.256(<4 x i64>, i8, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_mask_psrl_qi_256(<4 x i64> %x0, i8 %x1, <4 x i64> %x2, i8 %x3) { define <4 x i64>@test_int_x86_avx512_mask_psrl_qi_256(<4 x i64> %x0, i8 %x1, <4 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psrl_qi_256: ; CHECK-LABEL: test_int_x86_avx512_mask_psrl_qi_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsrlq $255, %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vpsrlq $255, %ymm0, %ymm1 {%k1}
; CHECK-NEXT: vpsrlq $255, %ymm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpsrlq $255, %ymm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vpsrlq $255, %ymm0, %ymm0 ; CHECK-NEXT: vpsrlq $255, %ymm0, %ymm0
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
; CHECK-NEXT: vpaddq %ymm0, %ymm2, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm2, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.psrl.qi.256(<4 x i64> %x0, i8 255, <4 x i64> %x2, i8 %x3) %res = call <4 x i64> @llvm.x86.avx512.mask.psrl.qi.256(<4 x i64> %x0, i8 255, <4 x i64> %x2, i8 %x3)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.psrl.qi.256(<4 x i64> %x0, i8 255, <4 x i64> %x2, i8 -1) %res1 = call <4 x i64> @llvm.x86.avx512.mask.psrl.qi.256(<4 x i64> %x0, i8 255, <4 x i64> %x2, i8 -1)
%res2 = call <4 x i64> @llvm.x86.avx512.mask.psrl.qi.256(<4 x i64> %x0, i8 255, <4 x i64> zeroinitializer, i8 %x3) %res2 = call <4 x i64> @llvm.x86.avx512.mask.psrl.qi.256(<4 x i64> %x0, i8 255, <4 x i64> zeroinitializer, i8 %x3)
%res3 = add <4 x i64> %res, %res1 %res3 = add <4 x i64> %res, %res1
%res4 = add <4 x i64> %res2, %res3 %res4 = add <4 x i64> %res2, %res3
ret <4 x i64> %res4 ret <4 x i64> %res4
} }
declare <4 x i32> @llvm.x86.avx512.mask.psrl.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.psrl.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_psrl_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) { define <4 x i32>@test_int_x86_avx512_mask_psrl_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psrl_d_128: ; CHECK-LABEL: test_int_x86_avx512_mask_psrl_d_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsrld %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vpsrld %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vpsrld %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: vpsrld %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: vpsrld %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpsrld %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm0
; CHECK-NEXT: vpaddd %xmm3, %xmm0, %xmm0 ; CHECK-NEXT: vpaddd %xmm3, %xmm0, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.psrl.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) %res = call <4 x i32> @llvm.x86.avx512.mask.psrl.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.psrl.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 -1) %res1 = call <4 x i32> @llvm.x86.avx512.mask.psrl.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 -1)
%res2 = call <4 x i32> @llvm.x86.avx512.mask.psrl.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %x3) %res2 = call <4 x i32> @llvm.x86.avx512.mask.psrl.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %x3)
%res3 = add <4 x i32> %res, %res1 %res3 = add <4 x i32> %res, %res1
%res4 = add <4 x i32> %res3, %res2 %res4 = add <4 x i32> %res3, %res2
ret <4 x i32> %res4 ret <4 x i32> %res4
} }
declare <8 x i32> @llvm.x86.avx512.mask.psrl.d.256(<8 x i32>, <4 x i32>, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.psrl.d.256(<8 x i32>, <4 x i32>, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_psrl_d_256(<8 x i32> %x0, <4 x i32> %x1, <8 x i32> %x2, i8 %x3) { define <8 x i32>@test_int_x86_avx512_mask_psrl_d_256(<8 x i32> %x0, <4 x i32> %x1, <8 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psrl_d_256: ; CHECK-LABEL: test_int_x86_avx512_mask_psrl_d_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsrld %xmm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vpsrld %xmm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: vpsrld %xmm1, %ymm0, %ymm3 {%k1} {z} ; CHECK-NEXT: vpsrld %xmm1, %ymm0, %ymm3 {%k1} {z}
; CHECK-NEXT: vpsrld %xmm1, %ymm0, %ymm0 ; CHECK-NEXT: vpsrld %xmm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm0, %ymm2, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm2, %ymm0
; CHECK-NEXT: vpaddd %ymm0, %ymm3, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm3, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.psrl.d.256(<8 x i32> %x0, <4 x i32> %x1, <8 x i32> %x2, i8 %x3) %res = call <8 x i32> @llvm.x86.avx512.mask.psrl.d.256(<8 x i32> %x0, <4 x i32> %x1, <8 x i32> %x2, i8 %x3)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.psrl.d.256(<8 x i32> %x0, <4 x i32> %x1, <8 x i32> %x2, i8 -1) %res1 = call <8 x i32> @llvm.x86.avx512.mask.psrl.d.256(<8 x i32> %x0, <4 x i32> %x1, <8 x i32> %x2, i8 -1)
%res2 = call <8 x i32> @llvm.x86.avx512.mask.psrl.d.256(<8 x i32> %x0, <4 x i32> %x1, <8 x i32> zeroinitializer, i8 %x3) %res2 = call <8 x i32> @llvm.x86.avx512.mask.psrl.d.256(<8 x i32> %x0, <4 x i32> %x1, <8 x i32> zeroinitializer, i8 %x3)
%res3 = add <8 x i32> %res, %res1 %res3 = add <8 x i32> %res, %res1
%res4 = add <8 x i32> %res2, %res3 %res4 = add <8 x i32> %res2, %res3
ret <8 x i32> %res4 ret <8 x i32> %res4
} }
declare <4 x i32> @llvm.x86.avx512.mask.psrl.di.128(<4 x i32>, i8, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.psrl.di.128(<4 x i32>, i8, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_psrl_di_128(<4 x i32> %x0, i8 %x1, <4 x i32> %x2, i8 %x3) { define <4 x i32>@test_int_x86_avx512_mask_psrl_di_128(<4 x i32> %x0, i8 %x1, <4 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psrl_di_128: ; CHECK-LABEL: test_int_x86_avx512_mask_psrl_di_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsrld $255, %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpsrld $255, %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpsrld $255, %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpsrld $255, %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpsrld $255, %xmm0, %xmm0 ; CHECK-NEXT: vpsrld $255, %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.psrl.di.128(<4 x i32> %x0, i8 255, <4 x i32> %x2, i8 %x3) %res = call <4 x i32> @llvm.x86.avx512.mask.psrl.di.128(<4 x i32> %x0, i8 255, <4 x i32> %x2, i8 %x3)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.psrl.di.128(<4 x i32> %x0, i8 255, <4 x i32> %x2, i8 -1) %res1 = call <4 x i32> @llvm.x86.avx512.mask.psrl.di.128(<4 x i32> %x0, i8 255, <4 x i32> %x2, i8 -1)
%res2 = call <4 x i32> @llvm.x86.avx512.mask.psrl.di.128(<4 x i32> %x0, i8 255, <4 x i32> zeroinitializer, i8 %x3) %res2 = call <4 x i32> @llvm.x86.avx512.mask.psrl.di.128(<4 x i32> %x0, i8 255, <4 x i32> zeroinitializer, i8 %x3)
%res3 = add <4 x i32> %res, %res1 %res3 = add <4 x i32> %res, %res1
%res4 = add <4 x i32> %res2, %res3 %res4 = add <4 x i32> %res2, %res3
ret <4 x i32> %res4 ret <4 x i32> %res4
} }
declare <8 x i32> @llvm.x86.avx512.mask.psrl.di.256(<8 x i32>, i8, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.psrl.di.256(<8 x i32>, i8, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_psrl_di_256(<8 x i32> %x0, i8 %x1, <8 x i32> %x2, i8 %x3) { define <8 x i32>@test_int_x86_avx512_mask_psrl_di_256(<8 x i32> %x0, i8 %x1, <8 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psrl_di_256: ; CHECK-LABEL: test_int_x86_avx512_mask_psrl_di_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsrld $255, %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vpsrld $255, %ymm0, %ymm1 {%k1}
; CHECK-NEXT: vpsrld $255, %ymm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpsrld $255, %ymm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vpsrld $255, %ymm0, %ymm0 ; CHECK-NEXT: vpsrld $255, %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: vpaddd %ymm0, %ymm2, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm2, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.psrl.di.256(<8 x i32> %x0, i8 255, <8 x i32> %x2, i8 %x3) %res = call <8 x i32> @llvm.x86.avx512.mask.psrl.di.256(<8 x i32> %x0, i8 255, <8 x i32> %x2, i8 %x3)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.psrl.di.256(<8 x i32> %x0, i8 255, <8 x i32> %x2, i8 -1) %res1 = call <8 x i32> @llvm.x86.avx512.mask.psrl.di.256(<8 x i32> %x0, i8 255, <8 x i32> %x2, i8 -1)
Show All 23 Lines; CHECK-NEXT: retq
ret <16 x i32> %res4 ret <16 x i32> %res4
} }
declare <2 x i64> @llvm.x86.avx512.mask.psrlv2.di(<2 x i64>, <2 x i64>, <2 x i64>, i8) declare <2 x i64> @llvm.x86.avx512.mask.psrlv2.di(<2 x i64>, <2 x i64>, <2 x i64>, i8)
define <2 x i64>@test_int_x86_avx512_mask_psrlv2_di(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) { define <2 x i64>@test_int_x86_avx512_mask_psrlv2_di(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psrlv2_di: ; CHECK-LABEL: test_int_x86_avx512_mask_psrlv2_di:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsrlvq %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vpsrlvq %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vpsrlvq %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: vpsrlvq %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddq %xmm3, %xmm2, %xmm1 ; CHECK-NEXT: vpaddq %xmm3, %xmm2, %xmm1
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.mask.psrlv2.di(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) %res = call <2 x i64> @llvm.x86.avx512.mask.psrlv2.di(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)
%res1 = call <2 x i64> @llvm.x86.avx512.mask.psrlv2.di(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3) %res1 = call <2 x i64> @llvm.x86.avx512.mask.psrlv2.di(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)
%res2 = call <2 x i64> @llvm.x86.avx512.mask.psrlv2.di(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1) %res2 = call <2 x i64> @llvm.x86.avx512.mask.psrlv2.di(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)
%res3 = add <2 x i64> %res, %res1 %res3 = add <2 x i64> %res, %res1
%res4 = add <2 x i64> %res3, %res2 %res4 = add <2 x i64> %res3, %res2
ret <2 x i64> %res4 ret <2 x i64> %res4
} }
declare <4 x i64> @llvm.x86.avx512.mask.psrlv4.di(<4 x i64>, <4 x i64>, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.psrlv4.di(<4 x i64>, <4 x i64>, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_mask_psrlv4_di(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) { define <4 x i64>@test_int_x86_avx512_mask_psrlv4_di(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psrlv4_di: ; CHECK-LABEL: test_int_x86_avx512_mask_psrlv4_di:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsrlvq %ymm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vpsrlvq %ymm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: vpsrlvq %ymm1, %ymm0, %ymm3 {%k1} {z} ; CHECK-NEXT: vpsrlvq %ymm1, %ymm0, %ymm3 {%k1} {z}
; CHECK-NEXT: vpsrlvq %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vpsrlvq %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddq %ymm3, %ymm2, %ymm1 ; CHECK-NEXT: vpaddq %ymm3, %ymm2, %ymm1
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.psrlv4.di(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) %res = call <4 x i64> @llvm.x86.avx512.mask.psrlv4.di(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.psrlv4.di(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3) %res1 = call <4 x i64> @llvm.x86.avx512.mask.psrlv4.di(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)
%res2 = call <4 x i64> @llvm.x86.avx512.mask.psrlv4.di(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 -1) %res2 = call <4 x i64> @llvm.x86.avx512.mask.psrlv4.di(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 -1)
%res3 = add <4 x i64> %res, %res1 %res3 = add <4 x i64> %res, %res1
%res4 = add <4 x i64> %res3, %res2 %res4 = add <4 x i64> %res3, %res2
ret <4 x i64> %res4 ret <4 x i64> %res4
} }
declare <4 x i32> @llvm.x86.avx512.mask.psrlv4.si(<4 x i32>, <4 x i32>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.psrlv4.si(<4 x i32>, <4 x i32>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_psrlv4_si(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) { define <4 x i32>@test_int_x86_avx512_mask_psrlv4_si(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psrlv4_si: ; CHECK-LABEL: test_int_x86_avx512_mask_psrlv4_si:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsrlvd %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vpsrlvd %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vpsrlvd %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: vpsrlvd %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm3, %xmm2, %xmm1 ; CHECK-NEXT: vpaddd %xmm3, %xmm2, %xmm1
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.psrlv4.si(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) %res = call <4 x i32> @llvm.x86.avx512.mask.psrlv4.si(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.psrlv4.si(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %x3) %res1 = call <4 x i32> @llvm.x86.avx512.mask.psrlv4.si(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %x3)
%res2 = call <4 x i32> @llvm.x86.avx512.mask.psrlv4.si(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 -1) %res2 = call <4 x i32> @llvm.x86.avx512.mask.psrlv4.si(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 -1)
%res3 = add <4 x i32> %res, %res1 %res3 = add <4 x i32> %res, %res1
%res4 = add <4 x i32> %res3, %res2 %res4 = add <4 x i32> %res3, %res2
ret <4 x i32> %res4 ret <4 x i32> %res4
} }
declare <8 x i32> @llvm.x86.avx512.mask.psrlv8.si(<8 x i32>, <8 x i32>, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.psrlv8.si(<8 x i32>, <8 x i32>, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_psrlv8_si(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) { define <8 x i32>@test_int_x86_avx512_mask_psrlv8_si(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psrlv8_si: ; CHECK-LABEL: test_int_x86_avx512_mask_psrlv8_si:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsrlvd %ymm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vpsrlvd %ymm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: vpsrlvd %ymm1, %ymm0, %ymm3 {%k1} {z} ; CHECK-NEXT: vpsrlvd %ymm1, %ymm0, %ymm3 {%k1} {z}
; CHECK-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm3, %ymm2, %ymm1 ; CHECK-NEXT: vpaddd %ymm3, %ymm2, %ymm1
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.psrlv8.si(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) %res = call <8 x i32> @llvm.x86.avx512.mask.psrlv8.si(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.psrlv8.si(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> zeroinitializer, i8 %x3) %res1 = call <8 x i32> @llvm.x86.avx512.mask.psrlv8.si(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> zeroinitializer, i8 %x3)
%res2 = call <8 x i32> @llvm.x86.avx512.mask.psrlv8.si(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 -1) %res2 = call <8 x i32> @llvm.x86.avx512.mask.psrlv8.si(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 -1)
%res3 = add <8 x i32> %res, %res1 %res3 = add <8 x i32> %res, %res1
%res4 = add <8 x i32> %res3, %res2 %res4 = add <8 x i32> %res3, %res2
ret <8 x i32> %res4 ret <8 x i32> %res4
} }
declare <4 x i32> @llvm.x86.avx512.mask.psra.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.psra.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_psra_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) { define <4 x i32>@test_int_x86_avx512_mask_psra_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psra_d_128: ; CHECK-LABEL: test_int_x86_avx512_mask_psra_d_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsrad %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vpsrad %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vpsrad %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: vpsrad %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: vpsrad %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpsrad %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm3, %xmm2, %xmm1 ; CHECK-NEXT: vpaddd %xmm3, %xmm2, %xmm1
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.psra.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) %res = call <4 x i32> @llvm.x86.avx512.mask.psra.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.psra.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %x3) %res1 = call <4 x i32> @llvm.x86.avx512.mask.psra.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %x3)
%res2 = call <4 x i32> @llvm.x86.avx512.mask.psra.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 -1) %res2 = call <4 x i32> @llvm.x86.avx512.mask.psra.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 -1)
%res3 = add <4 x i32> %res, %res1 %res3 = add <4 x i32> %res, %res1
%res4 = add <4 x i32> %res3, %res2 %res4 = add <4 x i32> %res3, %res2
ret <4 x i32> %res4 ret <4 x i32> %res4
} }
declare <8 x i32> @llvm.x86.avx512.mask.psra.d.256(<8 x i32>, <4 x i32>, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.psra.d.256(<8 x i32>, <4 x i32>, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_psra_d_256(<8 x i32> %x0, <4 x i32> %x1, <8 x i32> %x2, i8 %x3) { define <8 x i32>@test_int_x86_avx512_mask_psra_d_256(<8 x i32> %x0, <4 x i32> %x1, <8 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psra_d_256: ; CHECK-LABEL: test_int_x86_avx512_mask_psra_d_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsrad %xmm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vpsrad %xmm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: vpsrad %xmm1, %ymm0, %ymm3 {%k1} {z} ; CHECK-NEXT: vpsrad %xmm1, %ymm0, %ymm3 {%k1} {z}
; CHECK-NEXT: vpsrad %xmm1, %ymm0, %ymm0 ; CHECK-NEXT: vpsrad %xmm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm3, %ymm2, %ymm1 ; CHECK-NEXT: vpaddd %ymm3, %ymm2, %ymm1
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.psra.d.256(<8 x i32> %x0, <4 x i32> %x1, <8 x i32> %x2, i8 %x3) %res = call <8 x i32> @llvm.x86.avx512.mask.psra.d.256(<8 x i32> %x0, <4 x i32> %x1, <8 x i32> %x2, i8 %x3)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.psra.d.256(<8 x i32> %x0, <4 x i32> %x1, <8 x i32> zeroinitializer, i8 %x3) %res1 = call <8 x i32> @llvm.x86.avx512.mask.psra.d.256(<8 x i32> %x0, <4 x i32> %x1, <8 x i32> zeroinitializer, i8 %x3)
%res2 = call <8 x i32> @llvm.x86.avx512.mask.psra.d.256(<8 x i32> %x0, <4 x i32> %x1, <8 x i32> %x2, i8 -1) %res2 = call <8 x i32> @llvm.x86.avx512.mask.psra.d.256(<8 x i32> %x0, <4 x i32> %x1, <8 x i32> %x2, i8 -1)
%res3 = add <8 x i32> %res, %res1 %res3 = add <8 x i32> %res, %res1
%res4 = add <8 x i32> %res3, %res2 %res4 = add <8 x i32> %res3, %res2
ret <8 x i32> %res4 ret <8 x i32> %res4
} }
declare <4 x i32> @llvm.x86.avx512.mask.psra.di.128(<4 x i32>, i8, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.psra.di.128(<4 x i32>, i8, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_psra_di_128(<4 x i32> %x0, i8 %x1, <4 x i32> %x2, i8 %x3) { define <4 x i32>@test_int_x86_avx512_mask_psra_di_128(<4 x i32> %x0, i8 %x1, <4 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psra_di_128: ; CHECK-LABEL: test_int_x86_avx512_mask_psra_di_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsrad $3, %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpsrad $3, %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpsrad $3, %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpsrad $3, %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpsrad $3, %xmm0, %xmm0 ; CHECK-NEXT: vpsrad $3, %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.psra.di.128(<4 x i32> %x0, i8 3, <4 x i32> %x2, i8 %x3) %res = call <4 x i32> @llvm.x86.avx512.mask.psra.di.128(<4 x i32> %x0, i8 3, <4 x i32> %x2, i8 %x3)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.psra.di.128(<4 x i32> %x0, i8 3, <4 x i32> zeroinitializer, i8 %x3) %res1 = call <4 x i32> @llvm.x86.avx512.mask.psra.di.128(<4 x i32> %x0, i8 3, <4 x i32> zeroinitializer, i8 %x3)
%res2 = call <4 x i32> @llvm.x86.avx512.mask.psra.di.128(<4 x i32> %x0, i8 3, <4 x i32> %x2, i8 -1) %res2 = call <4 x i32> @llvm.x86.avx512.mask.psra.di.128(<4 x i32> %x0, i8 3, <4 x i32> %x2, i8 -1)
%res3 = add <4 x i32> %res, %res1 %res3 = add <4 x i32> %res, %res1
%res4 = add <4 x i32> %res3, %res2 %res4 = add <4 x i32> %res3, %res2
ret <4 x i32> %res4 ret <4 x i32> %res4
} }
declare <8 x i32> @llvm.x86.avx512.mask.psra.di.256(<8 x i32>, i8, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.psra.di.256(<8 x i32>, i8, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_psra_di_256(<8 x i32> %x0, i8 %x1, <8 x i32> %x2, i8 %x3) { define <8 x i32>@test_int_x86_avx512_mask_psra_di_256(<8 x i32> %x0, i8 %x1, <8 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psra_di_256: ; CHECK-LABEL: test_int_x86_avx512_mask_psra_di_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsrad $3, %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vpsrad $3, %ymm0, %ymm1 {%k1}
; CHECK-NEXT: vpsrad $3, %ymm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpsrad $3, %ymm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vpsrad $3, %ymm0, %ymm0 ; CHECK-NEXT: vpsrad $3, %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm2, %ymm1, %ymm1 ; CHECK-NEXT: vpaddd %ymm2, %ymm1, %ymm1
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.psra.di.256(<8 x i32> %x0, i8 3, <8 x i32> %x2, i8 %x3) %res = call <8 x i32> @llvm.x86.avx512.mask.psra.di.256(<8 x i32> %x0, i8 3, <8 x i32> %x2, i8 %x3)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.psra.di.256(<8 x i32> %x0, i8 3, <8 x i32> zeroinitializer, i8 %x3) %res1 = call <8 x i32> @llvm.x86.avx512.mask.psra.di.256(<8 x i32> %x0, i8 3, <8 x i32> zeroinitializer, i8 %x3)
%res2 = call <8 x i32> @llvm.x86.avx512.mask.psra.di.256(<8 x i32> %x0, i8 3, <8 x i32> %x2, i8 -1) %res2 = call <8 x i32> @llvm.x86.avx512.mask.psra.di.256(<8 x i32> %x0, i8 3, <8 x i32> %x2, i8 -1)
%res3 = add <8 x i32> %res, %res1 %res3 = add <8 x i32> %res, %res1
%res4 = add <8 x i32> %res3, %res2 %res4 = add <8 x i32> %res3, %res2
ret <8 x i32> %res4 ret <8 x i32> %res4
} }
declare <2 x i64> @llvm.x86.avx512.mask.psra.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8) declare <2 x i64> @llvm.x86.avx512.mask.psra.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)
define <2 x i64>@test_int_x86_avx512_mask_psra_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) { define <2 x i64>@test_int_x86_avx512_mask_psra_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psra_q_128: ; CHECK-LABEL: test_int_x86_avx512_mask_psra_q_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsraq %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vpsraq %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vpsraq %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: vpsraq %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: vpsraq %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpsraq %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddq %xmm3, %xmm2, %xmm1 ; CHECK-NEXT: vpaddq %xmm3, %xmm2, %xmm1
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.mask.psra.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) %res = call <2 x i64> @llvm.x86.avx512.mask.psra.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)
%res1 = call <2 x i64> @llvm.x86.avx512.mask.psra.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3) %res1 = call <2 x i64> @llvm.x86.avx512.mask.psra.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)
%res2 = call <2 x i64> @llvm.x86.avx512.mask.psra.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1) %res2 = call <2 x i64> @llvm.x86.avx512.mask.psra.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)
%res3 = add <2 x i64> %res, %res1 %res3 = add <2 x i64> %res, %res1
%res4 = add <2 x i64> %res3, %res2 %res4 = add <2 x i64> %res3, %res2
ret <2 x i64> %res4 ret <2 x i64> %res4
} }
declare <4 x i64> @llvm.x86.avx512.mask.psra.q.256(<4 x i64>, <2 x i64>, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.psra.q.256(<4 x i64>, <2 x i64>, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_mask_psra_q_256(<4 x i64> %x0, <2 x i64> %x1, <4 x i64> %x2, i8 %x3) { define <4 x i64>@test_int_x86_avx512_mask_psra_q_256(<4 x i64> %x0, <2 x i64> %x1, <4 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psra_q_256: ; CHECK-LABEL: test_int_x86_avx512_mask_psra_q_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsraq %xmm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vpsraq %xmm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: vpsraq %xmm1, %ymm0, %ymm3 {%k1} {z} ; CHECK-NEXT: vpsraq %xmm1, %ymm0, %ymm3 {%k1} {z}
; CHECK-NEXT: vpsraq %xmm1, %ymm0, %ymm0 ; CHECK-NEXT: vpsraq %xmm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddq %ymm3, %ymm2, %ymm1 ; CHECK-NEXT: vpaddq %ymm3, %ymm2, %ymm1
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.psra.q.256(<4 x i64> %x0, <2 x i64> %x1, <4 x i64> %x2, i8 %x3) %res = call <4 x i64> @llvm.x86.avx512.mask.psra.q.256(<4 x i64> %x0, <2 x i64> %x1, <4 x i64> %x2, i8 %x3)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.psra.q.256(<4 x i64> %x0, <2 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3) %res1 = call <4 x i64> @llvm.x86.avx512.mask.psra.q.256(<4 x i64> %x0, <2 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)
%res2 = call <4 x i64> @llvm.x86.avx512.mask.psra.q.256(<4 x i64> %x0, <2 x i64> %x1, <4 x i64> %x2, i8 -1) %res2 = call <4 x i64> @llvm.x86.avx512.mask.psra.q.256(<4 x i64> %x0, <2 x i64> %x1, <4 x i64> %x2, i8 -1)
%res3 = add <4 x i64> %res, %res1 %res3 = add <4 x i64> %res, %res1
%res4 = add <4 x i64> %res3, %res2 %res4 = add <4 x i64> %res3, %res2
ret <4 x i64> %res4 ret <4 x i64> %res4
} }
declare <2 x i64> @llvm.x86.avx512.mask.psra.qi.128(<2 x i64>, i8, <2 x i64>, i8) declare <2 x i64> @llvm.x86.avx512.mask.psra.qi.128(<2 x i64>, i8, <2 x i64>, i8)
define <2 x i64>@test_int_x86_avx512_mask_psra_qi_128(<2 x i64> %x0, i8 %x1, <2 x i64> %x2, i8 %x3) { define <2 x i64>@test_int_x86_avx512_mask_psra_qi_128(<2 x i64> %x0, i8 %x1, <2 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psra_qi_128: ; CHECK-LABEL: test_int_x86_avx512_mask_psra_qi_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsraq $3, %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpsraq $3, %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpsraq $3, %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpsraq $3, %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpsraq $3, %xmm0, %xmm0 ; CHECK-NEXT: vpsraq $3, %xmm0, %xmm0
; CHECK-NEXT: vpaddq %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpaddq %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.mask.psra.qi.128(<2 x i64> %x0, i8 3, <2 x i64> %x2, i8 %x3) %res = call <2 x i64> @llvm.x86.avx512.mask.psra.qi.128(<2 x i64> %x0, i8 3, <2 x i64> %x2, i8 %x3)
%res1 = call <2 x i64> @llvm.x86.avx512.mask.psra.qi.128(<2 x i64> %x0, i8 3, <2 x i64> zeroinitializer, i8 %x3) %res1 = call <2 x i64> @llvm.x86.avx512.mask.psra.qi.128(<2 x i64> %x0, i8 3, <2 x i64> zeroinitializer, i8 %x3)
%res2 = call <2 x i64> @llvm.x86.avx512.mask.psra.qi.128(<2 x i64> %x0, i8 3, <2 x i64> %x2, i8 -1) %res2 = call <2 x i64> @llvm.x86.avx512.mask.psra.qi.128(<2 x i64> %x0, i8 3, <2 x i64> %x2, i8 -1)
%res3 = add <2 x i64> %res, %res1 %res3 = add <2 x i64> %res, %res1
%res4 = add <2 x i64> %res3, %res2 %res4 = add <2 x i64> %res3, %res2
ret <2 x i64> %res4 ret <2 x i64> %res4
} }
declare <4 x i64> @llvm.x86.avx512.mask.psra.qi.256(<4 x i64>, i8, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.psra.qi.256(<4 x i64>, i8, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_mask_psra_qi_256(<4 x i64> %x0, i8 %x1, <4 x i64> %x2, i8 %x3) { define <4 x i64>@test_int_x86_avx512_mask_psra_qi_256(<4 x i64> %x0, i8 %x1, <4 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psra_qi_256: ; CHECK-LABEL: test_int_x86_avx512_mask_psra_qi_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsraq $3, %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vpsraq $3, %ymm0, %ymm1 {%k1}
; CHECK-NEXT: vpsraq $3, %ymm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpsraq $3, %ymm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vpsraq $3, %ymm0, %ymm0 ; CHECK-NEXT: vpsraq $3, %ymm0, %ymm0
; CHECK-NEXT: vpaddq %ymm2, %ymm1, %ymm1 ; CHECK-NEXT: vpaddq %ymm2, %ymm1, %ymm1
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.psra.qi.256(<4 x i64> %x0, i8 3, <4 x i64> %x2, i8 %x3) %res = call <4 x i64> @llvm.x86.avx512.mask.psra.qi.256(<4 x i64> %x0, i8 3, <4 x i64> %x2, i8 %x3)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.psra.qi.256(<4 x i64> %x0, i8 3, <4 x i64> zeroinitializer, i8 %x3) %res1 = call <4 x i64> @llvm.x86.avx512.mask.psra.qi.256(<4 x i64> %x0, i8 3, <4 x i64> zeroinitializer, i8 %x3)
%res2 = call <4 x i64> @llvm.x86.avx512.mask.psra.qi.256(<4 x i64> %x0, i8 3, <4 x i64> %x2, i8 -1) %res2 = call <4 x i64> @llvm.x86.avx512.mask.psra.qi.256(<4 x i64> %x0, i8 3, <4 x i64> %x2, i8 -1)
%res3 = add <4 x i64> %res, %res1 %res3 = add <4 x i64> %res, %res1
%res4 = add <4 x i64> %res3, %res2 %res4 = add <4 x i64> %res3, %res2
ret <4 x i64> %res4 ret <4 x i64> %res4
} }
declare <4 x i32> @llvm.x86.avx512.mask.psll.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.psll.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_psll_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) { define <4 x i32>@test_int_x86_avx512_mask_psll_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psll_d_128: ; CHECK-LABEL: test_int_x86_avx512_mask_psll_d_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpslld %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vpslld %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vpslld %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: vpslld %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: vpslld %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpslld %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm3, %xmm2, %xmm1 ; CHECK-NEXT: vpaddd %xmm3, %xmm2, %xmm1
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.psll.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) %res = call <4 x i32> @llvm.x86.avx512.mask.psll.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.psll.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %x3) %res1 = call <4 x i32> @llvm.x86.avx512.mask.psll.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %x3)
%res2 = call <4 x i32> @llvm.x86.avx512.mask.psll.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 -1) %res2 = call <4 x i32> @llvm.x86.avx512.mask.psll.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 -1)
%res3 = add <4 x i32> %res, %res1 %res3 = add <4 x i32> %res, %res1
%res4 = add <4 x i32> %res3, %res2 %res4 = add <4 x i32> %res3, %res2
ret <4 x i32> %res4 ret <4 x i32> %res4
} }
declare <8 x i32> @llvm.x86.avx512.mask.psll.d.256(<8 x i32>, <4 x i32>, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.psll.d.256(<8 x i32>, <4 x i32>, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_psll_d_256(<8 x i32> %x0, <4 x i32> %x1, <8 x i32> %x2, i8 %x3) { define <8 x i32>@test_int_x86_avx512_mask_psll_d_256(<8 x i32> %x0, <4 x i32> %x1, <8 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psll_d_256: ; CHECK-LABEL: test_int_x86_avx512_mask_psll_d_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpslld %xmm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vpslld %xmm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: vpslld %xmm1, %ymm0, %ymm3 {%k1} {z} ; CHECK-NEXT: vpslld %xmm1, %ymm0, %ymm3 {%k1} {z}
; CHECK-NEXT: vpslld %xmm1, %ymm0, %ymm0 ; CHECK-NEXT: vpslld %xmm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm3, %ymm2, %ymm1 ; CHECK-NEXT: vpaddd %ymm3, %ymm2, %ymm1
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.psll.d.256(<8 x i32> %x0, <4 x i32> %x1, <8 x i32> %x2, i8 %x3) %res = call <8 x i32> @llvm.x86.avx512.mask.psll.d.256(<8 x i32> %x0, <4 x i32> %x1, <8 x i32> %x2, i8 %x3)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.psll.d.256(<8 x i32> %x0, <4 x i32> %x1, <8 x i32> zeroinitializer, i8 %x3) %res1 = call <8 x i32> @llvm.x86.avx512.mask.psll.d.256(<8 x i32> %x0, <4 x i32> %x1, <8 x i32> zeroinitializer, i8 %x3)
%res2 = call <8 x i32> @llvm.x86.avx512.mask.psll.d.256(<8 x i32> %x0, <4 x i32> %x1, <8 x i32> %x2, i8 -1) %res2 = call <8 x i32> @llvm.x86.avx512.mask.psll.d.256(<8 x i32> %x0, <4 x i32> %x1, <8 x i32> %x2, i8 -1)
%res3 = add <8 x i32> %res, %res1 %res3 = add <8 x i32> %res, %res1
%res4 = add <8 x i32> %res3, %res2 %res4 = add <8 x i32> %res3, %res2
ret <8 x i32> %res4 ret <8 x i32> %res4
} }
declare <4 x i32> @llvm.x86.avx512.mask.psll.di.128(<4 x i32>, i8, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.psll.di.128(<4 x i32>, i8, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_psll_di_128(<4 x i32> %x0, i8 %x1, <4 x i32> %x2, i8 %x3) { define <4 x i32>@test_int_x86_avx512_mask_psll_di_128(<4 x i32> %x0, i8 %x1, <4 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psll_di_128: ; CHECK-LABEL: test_int_x86_avx512_mask_psll_di_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpslld $3, %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpslld $3, %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpslld $3, %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpslld $3, %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpslld $3, %xmm0, %xmm0 ; CHECK-NEXT: vpslld $3, %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.psll.di.128(<4 x i32> %x0, i8 3, <4 x i32> %x2, i8 %x3) %res = call <4 x i32> @llvm.x86.avx512.mask.psll.di.128(<4 x i32> %x0, i8 3, <4 x i32> %x2, i8 %x3)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.psll.di.128(<4 x i32> %x0, i8 3, <4 x i32> zeroinitializer, i8 %x3) %res1 = call <4 x i32> @llvm.x86.avx512.mask.psll.di.128(<4 x i32> %x0, i8 3, <4 x i32> zeroinitializer, i8 %x3)
%res2 = call <4 x i32> @llvm.x86.avx512.mask.psll.di.128(<4 x i32> %x0, i8 3, <4 x i32> %x2, i8 -1) %res2 = call <4 x i32> @llvm.x86.avx512.mask.psll.di.128(<4 x i32> %x0, i8 3, <4 x i32> %x2, i8 -1)
%res3 = add <4 x i32> %res, %res1 %res3 = add <4 x i32> %res, %res1
%res4 = add <4 x i32> %res3, %res2 %res4 = add <4 x i32> %res3, %res2
ret <4 x i32> %res4 ret <4 x i32> %res4
} }
declare <8 x i32> @llvm.x86.avx512.mask.psll.di.256(<8 x i32>, i8, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.psll.di.256(<8 x i32>, i8, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_psll_di_256(<8 x i32> %x0, i8 %x1, <8 x i32> %x2, i8 %x3) { define <8 x i32>@test_int_x86_avx512_mask_psll_di_256(<8 x i32> %x0, i8 %x1, <8 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psll_di_256: ; CHECK-LABEL: test_int_x86_avx512_mask_psll_di_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpslld $3, %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vpslld $3, %ymm0, %ymm1 {%k1}
; CHECK-NEXT: vpslld $3, %ymm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpslld $3, %ymm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vpslld $3, %ymm0, %ymm0 ; CHECK-NEXT: vpslld $3, %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm2, %ymm1, %ymm1 ; CHECK-NEXT: vpaddd %ymm2, %ymm1, %ymm1
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.psll.di.256(<8 x i32> %x0, i8 3, <8 x i32> %x2, i8 %x3) %res = call <8 x i32> @llvm.x86.avx512.mask.psll.di.256(<8 x i32> %x0, i8 3, <8 x i32> %x2, i8 %x3)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.psll.di.256(<8 x i32> %x0, i8 3, <8 x i32> zeroinitializer, i8 %x3) %res1 = call <8 x i32> @llvm.x86.avx512.mask.psll.di.256(<8 x i32> %x0, i8 3, <8 x i32> zeroinitializer, i8 %x3)
%res2 = call <8 x i32> @llvm.x86.avx512.mask.psll.di.256(<8 x i32> %x0, i8 3, <8 x i32> %x2, i8 -1) %res2 = call <8 x i32> @llvm.x86.avx512.mask.psll.di.256(<8 x i32> %x0, i8 3, <8 x i32> %x2, i8 -1)
%res3 = add <8 x i32> %res, %res1 %res3 = add <8 x i32> %res, %res1
%res4 = add <8 x i32> %res3, %res2 %res4 = add <8 x i32> %res3, %res2
ret <8 x i32> %res4 ret <8 x i32> %res4
} }
declare <4 x i64> @llvm.x86.avx512.mask.psll.q.256(<4 x i64>, <2 x i64>, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.psll.q.256(<4 x i64>, <2 x i64>, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_mask_psll_q_256(<4 x i64> %x0, <2 x i64> %x1, <4 x i64> %x2, i8 %x3) { define <4 x i64>@test_int_x86_avx512_mask_psll_q_256(<4 x i64> %x0, <2 x i64> %x1, <4 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psll_q_256: ; CHECK-LABEL: test_int_x86_avx512_mask_psll_q_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsllq %xmm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vpsllq %xmm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: vpsllq %xmm1, %ymm0, %ymm3 {%k1} {z} ; CHECK-NEXT: vpsllq %xmm1, %ymm0, %ymm3 {%k1} {z}
; CHECK-NEXT: vpsllq %xmm1, %ymm0, %ymm0 ; CHECK-NEXT: vpsllq %xmm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddq %ymm3, %ymm2, %ymm1 ; CHECK-NEXT: vpaddq %ymm3, %ymm2, %ymm1
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.psll.q.256(<4 x i64> %x0, <2 x i64> %x1, <4 x i64> %x2, i8 %x3) %res = call <4 x i64> @llvm.x86.avx512.mask.psll.q.256(<4 x i64> %x0, <2 x i64> %x1, <4 x i64> %x2, i8 %x3)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.psll.q.256(<4 x i64> %x0, <2 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3) %res1 = call <4 x i64> @llvm.x86.avx512.mask.psll.q.256(<4 x i64> %x0, <2 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)
%res2 = call <4 x i64> @llvm.x86.avx512.mask.psll.q.256(<4 x i64> %x0, <2 x i64> %x1, <4 x i64> %x2, i8 -1) %res2 = call <4 x i64> @llvm.x86.avx512.mask.psll.q.256(<4 x i64> %x0, <2 x i64> %x1, <4 x i64> %x2, i8 -1)
%res3 = add <4 x i64> %res, %res1 %res3 = add <4 x i64> %res, %res1
%res4 = add <4 x i64> %res3, %res2 %res4 = add <4 x i64> %res3, %res2
ret <4 x i64> %res4 ret <4 x i64> %res4
} }
declare <2 x i64> @llvm.x86.avx512.mask.psll.qi.128(<2 x i64>, i8, <2 x i64>, i8) declare <2 x i64> @llvm.x86.avx512.mask.psll.qi.128(<2 x i64>, i8, <2 x i64>, i8)
define <2 x i64>@test_int_x86_avx512_mask_psll_qi_128(<2 x i64> %x0, i8 %x1, <2 x i64> %x2, i8 %x3) { define <2 x i64>@test_int_x86_avx512_mask_psll_qi_128(<2 x i64> %x0, i8 %x1, <2 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psll_qi_128: ; CHECK-LABEL: test_int_x86_avx512_mask_psll_qi_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsllq $3, %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpsllq $3, %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpsllq $3, %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpsllq $3, %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpsllq $3, %xmm0, %xmm0 ; CHECK-NEXT: vpsllq $3, %xmm0, %xmm0
; CHECK-NEXT: vpaddq %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpaddq %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.mask.psll.qi.128(<2 x i64> %x0, i8 3, <2 x i64> %x2, i8 %x3) %res = call <2 x i64> @llvm.x86.avx512.mask.psll.qi.128(<2 x i64> %x0, i8 3, <2 x i64> %x2, i8 %x3)
%res1 = call <2 x i64> @llvm.x86.avx512.mask.psll.qi.128(<2 x i64> %x0, i8 3, <2 x i64> zeroinitializer, i8 %x3) %res1 = call <2 x i64> @llvm.x86.avx512.mask.psll.qi.128(<2 x i64> %x0, i8 3, <2 x i64> zeroinitializer, i8 %x3)
%res2 = call <2 x i64> @llvm.x86.avx512.mask.psll.qi.128(<2 x i64> %x0, i8 3, <2 x i64> %x2, i8 -1) %res2 = call <2 x i64> @llvm.x86.avx512.mask.psll.qi.128(<2 x i64> %x0, i8 3, <2 x i64> %x2, i8 -1)
%res3 = add <2 x i64> %res, %res1 %res3 = add <2 x i64> %res, %res1
%res4 = add <2 x i64> %res3, %res2 %res4 = add <2 x i64> %res3, %res2
ret <2 x i64> %res4 ret <2 x i64> %res4
} }
declare <4 x i64> @llvm.x86.avx512.mask.psll.qi.256(<4 x i64>, i8, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.psll.qi.256(<4 x i64>, i8, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_mask_psll_qi_256(<4 x i64> %x0, i8 %x1, <4 x i64> %x2, i8 %x3) { define <4 x i64>@test_int_x86_avx512_mask_psll_qi_256(<4 x i64> %x0, i8 %x1, <4 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psll_qi_256: ; CHECK-LABEL: test_int_x86_avx512_mask_psll_qi_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsllq $3, %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vpsllq $3, %ymm0, %ymm1 {%k1}
; CHECK-NEXT: vpsllq $3, %ymm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpsllq $3, %ymm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vpsllq $3, %ymm0, %ymm0 ; CHECK-NEXT: vpsllq $3, %ymm0, %ymm0
; CHECK-NEXT: vpaddq %ymm2, %ymm1, %ymm1 ; CHECK-NEXT: vpaddq %ymm2, %ymm1, %ymm1
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.psll.qi.256(<4 x i64> %x0, i8 3, <4 x i64> %x2, i8 %x3) %res = call <4 x i64> @llvm.x86.avx512.mask.psll.qi.256(<4 x i64> %x0, i8 3, <4 x i64> %x2, i8 %x3)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.psll.qi.256(<4 x i64> %x0, i8 3, <4 x i64> zeroinitializer, i8 %x3) %res1 = call <4 x i64> @llvm.x86.avx512.mask.psll.qi.256(<4 x i64> %x0, i8 3, <4 x i64> zeroinitializer, i8 %x3)
%res2 = call <4 x i64> @llvm.x86.avx512.mask.psll.qi.256(<4 x i64> %x0, i8 3, <4 x i64> %x2, i8 -1) %res2 = call <4 x i64> @llvm.x86.avx512.mask.psll.qi.256(<4 x i64> %x0, i8 3, <4 x i64> %x2, i8 -1)
%res3 = add <4 x i64> %res, %res1 %res3 = add <4 x i64> %res, %res1
%res4 = add <4 x i64> %res3, %res2 %res4 = add <4 x i64> %res3, %res2
ret <4 x i64> %res4 ret <4 x i64> %res4
} }
define <8 x float> @test_mask_load_aligned_ps_256(<8 x float> %data, i8* %ptr, i8 %mask) { define <8 x float> @test_mask_load_aligned_ps_256(<8 x float> %data, i8* %ptr, i8 %mask) {
; CHECK-LABEL: test_mask_load_aligned_ps_256: ; CHECK-LABEL: test_mask_load_aligned_ps_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps (%rdi), %ymm0 ; CHECK-NEXT: vmovaps (%rdi), %ymm0
; CHECK-NEXT: vmovaps (%rdi), %ymm0 {%k1} ; CHECK-NEXT: vmovaps (%rdi), %ymm0 {%k1}
; CHECK-NEXT: vmovaps (%rdi), %ymm1 {%k1} {z} ; CHECK-NEXT: vmovaps (%rdi), %ymm1 {%k1} {z}
; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx512.mask.load.ps.256(i8* %ptr, <8 x float> zeroinitializer, i8 -1) %res = call <8 x float> @llvm.x86.avx512.mask.load.ps.256(i8* %ptr, <8 x float> zeroinitializer, i8 -1)
%res1 = call <8 x float> @llvm.x86.avx512.mask.load.ps.256(i8* %ptr, <8 x float> %res, i8 %mask) %res1 = call <8 x float> @llvm.x86.avx512.mask.load.ps.256(i8* %ptr, <8 x float> %res, i8 %mask)
%res2 = call <8 x float> @llvm.x86.avx512.mask.load.ps.256(i8* %ptr, <8 x float> zeroinitializer, i8 %mask) %res2 = call <8 x float> @llvm.x86.avx512.mask.load.ps.256(i8* %ptr, <8 x float> zeroinitializer, i8 %mask)
%res4 = fadd <8 x float> %res2, %res1 %res4 = fadd <8 x float> %res2, %res1
ret <8 x float> %res4 ret <8 x float> %res4
} }
declare <8 x float> @llvm.x86.avx512.mask.load.ps.256(i8*, <8 x float>, i8) declare <8 x float> @llvm.x86.avx512.mask.load.ps.256(i8*, <8 x float>, i8)
define <8 x float> @test_mask_load_unaligned_ps_256(<8 x float> %data, i8* %ptr, i8 %mask) { define <8 x float> @test_mask_load_unaligned_ps_256(<8 x float> %data, i8* %ptr, i8 %mask) {
; CHECK-LABEL: test_mask_load_unaligned_ps_256: ; CHECK-LABEL: test_mask_load_unaligned_ps_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovups (%rdi), %ymm0 ; CHECK-NEXT: vmovups (%rdi), %ymm0
; CHECK-NEXT: vmovups (%rdi), %ymm0 {%k1} ; CHECK-NEXT: vmovups (%rdi), %ymm0 {%k1}
; CHECK-NEXT: vmovups (%rdi), %ymm1 {%k1} {z} ; CHECK-NEXT: vmovups (%rdi), %ymm1 {%k1} {z}
; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx512.mask.loadu.ps.256(i8* %ptr, <8 x float> zeroinitializer, i8 -1) %res = call <8 x float> @llvm.x86.avx512.mask.loadu.ps.256(i8* %ptr, <8 x float> zeroinitializer, i8 -1)
%res1 = call <8 x float> @llvm.x86.avx512.mask.loadu.ps.256(i8* %ptr, <8 x float> %res, i8 %mask) %res1 = call <8 x float> @llvm.x86.avx512.mask.loadu.ps.256(i8* %ptr, <8 x float> %res, i8 %mask)
%res2 = call <8 x float> @llvm.x86.avx512.mask.loadu.ps.256(i8* %ptr, <8 x float> zeroinitializer, i8 %mask) %res2 = call <8 x float> @llvm.x86.avx512.mask.loadu.ps.256(i8* %ptr, <8 x float> zeroinitializer, i8 %mask)
%res4 = fadd <8 x float> %res2, %res1 %res4 = fadd <8 x float> %res2, %res1
ret <8 x float> %res4 ret <8 x float> %res4
} }
declare <8 x float> @llvm.x86.avx512.mask.loadu.ps.256(i8*, <8 x float>, i8) declare <8 x float> @llvm.x86.avx512.mask.loadu.ps.256(i8*, <8 x float>, i8)
define <4 x double> @test_mask_load_aligned_pd_256(<4 x double> %data, i8* %ptr, i8 %mask) { define <4 x double> @test_mask_load_aligned_pd_256(<4 x double> %data, i8* %ptr, i8 %mask) {
; CHECK-LABEL: test_mask_load_aligned_pd_256: ; CHECK-LABEL: test_mask_load_aligned_pd_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovapd (%rdi), %ymm0 ; CHECK-NEXT: vmovapd (%rdi), %ymm0
; CHECK-NEXT: vmovapd (%rdi), %ymm0 {%k1} ; CHECK-NEXT: vmovapd (%rdi), %ymm0 {%k1}
; CHECK-NEXT: vmovapd (%rdi), %ymm1 {%k1} {z} ; CHECK-NEXT: vmovapd (%rdi), %ymm1 {%k1} {z}
; CHECK-NEXT: vaddpd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vaddpd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x double> @llvm.x86.avx512.mask.load.pd.256(i8* %ptr, <4 x double> zeroinitializer, i8 -1) %res = call <4 x double> @llvm.x86.avx512.mask.load.pd.256(i8* %ptr, <4 x double> zeroinitializer, i8 -1)
%res1 = call <4 x double> @llvm.x86.avx512.mask.load.pd.256(i8* %ptr, <4 x double> %res, i8 %mask) %res1 = call <4 x double> @llvm.x86.avx512.mask.load.pd.256(i8* %ptr, <4 x double> %res, i8 %mask)
%res2 = call <4 x double> @llvm.x86.avx512.mask.load.pd.256(i8* %ptr, <4 x double> zeroinitializer, i8 %mask) %res2 = call <4 x double> @llvm.x86.avx512.mask.load.pd.256(i8* %ptr, <4 x double> zeroinitializer, i8 %mask)
%res4 = fadd <4 x double> %res2, %res1 %res4 = fadd <4 x double> %res2, %res1
ret <4 x double> %res4 ret <4 x double> %res4
} }
declare <4 x double> @llvm.x86.avx512.mask.load.pd.256(i8*, <4 x double>, i8) declare <4 x double> @llvm.x86.avx512.mask.load.pd.256(i8*, <4 x double>, i8)
define <4 x double> @test_mask_load_unaligned_pd_256(<4 x double> %data, i8* %ptr, i8 %mask) { define <4 x double> @test_mask_load_unaligned_pd_256(<4 x double> %data, i8* %ptr, i8 %mask) {
; CHECK-LABEL: test_mask_load_unaligned_pd_256: ; CHECK-LABEL: test_mask_load_unaligned_pd_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovupd (%rdi), %ymm0 ; CHECK-NEXT: vmovupd (%rdi), %ymm0
; CHECK-NEXT: vmovupd (%rdi), %ymm0 {%k1} ; CHECK-NEXT: vmovupd (%rdi), %ymm0 {%k1}
; CHECK-NEXT: vmovupd (%rdi), %ymm1 {%k1} {z} ; CHECK-NEXT: vmovupd (%rdi), %ymm1 {%k1} {z}
; CHECK-NEXT: vaddpd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vaddpd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x double> @llvm.x86.avx512.mask.loadu.pd.256(i8* %ptr, <4 x double> zeroinitializer, i8 -1) %res = call <4 x double> @llvm.x86.avx512.mask.loadu.pd.256(i8* %ptr, <4 x double> zeroinitializer, i8 -1)
%res1 = call <4 x double> @llvm.x86.avx512.mask.loadu.pd.256(i8* %ptr, <4 x double> %res, i8 %mask) %res1 = call <4 x double> @llvm.x86.avx512.mask.loadu.pd.256(i8* %ptr, <4 x double> %res, i8 %mask)
%res2 = call <4 x double> @llvm.x86.avx512.mask.loadu.pd.256(i8* %ptr, <4 x double> zeroinitializer, i8 %mask) %res2 = call <4 x double> @llvm.x86.avx512.mask.loadu.pd.256(i8* %ptr, <4 x double> zeroinitializer, i8 %mask)
%res4 = fadd <4 x double> %res2, %res1 %res4 = fadd <4 x double> %res2, %res1
ret <4 x double> %res4 ret <4 x double> %res4
} }
declare <4 x double> @llvm.x86.avx512.mask.loadu.pd.256(i8*, <4 x double>, i8) declare <4 x double> @llvm.x86.avx512.mask.loadu.pd.256(i8*, <4 x double>, i8)
define <4 x float> @test_mask_load_aligned_ps_128(<4 x float> %data, i8* %ptr, i8 %mask) { define <4 x float> @test_mask_load_aligned_ps_128(<4 x float> %data, i8* %ptr, i8 %mask) {
; CHECK-LABEL: test_mask_load_aligned_ps_128: ; CHECK-LABEL: test_mask_load_aligned_ps_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovaps (%rdi), %xmm0 ; CHECK-NEXT: vmovaps (%rdi), %xmm0
; CHECK-NEXT: vmovaps (%rdi), %xmm0 {%k1} ; CHECK-NEXT: vmovaps (%rdi), %xmm0 {%k1}
; CHECK-NEXT: vmovaps (%rdi), %xmm1 {%k1} {z} ; CHECK-NEXT: vmovaps (%rdi), %xmm1 {%k1} {z}
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.load.ps.128(i8* %ptr, <4 x float> zeroinitializer, i8 -1) %res = call <4 x float> @llvm.x86.avx512.mask.load.ps.128(i8* %ptr, <4 x float> zeroinitializer, i8 -1)
%res1 = call <4 x float> @llvm.x86.avx512.mask.load.ps.128(i8* %ptr, <4 x float> %res, i8 %mask) %res1 = call <4 x float> @llvm.x86.avx512.mask.load.ps.128(i8* %ptr, <4 x float> %res, i8 %mask)
%res2 = call <4 x float> @llvm.x86.avx512.mask.load.ps.128(i8* %ptr, <4 x float> zeroinitializer, i8 %mask) %res2 = call <4 x float> @llvm.x86.avx512.mask.load.ps.128(i8* %ptr, <4 x float> zeroinitializer, i8 %mask)
%res4 = fadd <4 x float> %res2, %res1 %res4 = fadd <4 x float> %res2, %res1
ret <4 x float> %res4 ret <4 x float> %res4
} }
declare <4 x float> @llvm.x86.avx512.mask.load.ps.128(i8*, <4 x float>, i8) declare <4 x float> @llvm.x86.avx512.mask.load.ps.128(i8*, <4 x float>, i8)
define <4 x float> @test_mask_load_unaligned_ps_128(<4 x float> %data, i8* %ptr, i8 %mask) { define <4 x float> @test_mask_load_unaligned_ps_128(<4 x float> %data, i8* %ptr, i8 %mask) {
; CHECK-LABEL: test_mask_load_unaligned_ps_128: ; CHECK-LABEL: test_mask_load_unaligned_ps_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovups (%rdi), %xmm0 ; CHECK-NEXT: vmovups (%rdi), %xmm0
; CHECK-NEXT: vmovups (%rdi), %xmm0 {%k1} ; CHECK-NEXT: vmovups (%rdi), %xmm0 {%k1}
; CHECK-NEXT: vmovups (%rdi), %xmm1 {%k1} {z} ; CHECK-NEXT: vmovups (%rdi), %xmm1 {%k1} {z}
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x float> @llvm.x86.avx512.mask.loadu.ps.128(i8* %ptr, <4 x float> zeroinitializer, i8 -1) %res = call <4 x float> @llvm.x86.avx512.mask.loadu.ps.128(i8* %ptr, <4 x float> zeroinitializer, i8 -1)
%res1 = call <4 x float> @llvm.x86.avx512.mask.loadu.ps.128(i8* %ptr, <4 x float> %res, i8 %mask) %res1 = call <4 x float> @llvm.x86.avx512.mask.loadu.ps.128(i8* %ptr, <4 x float> %res, i8 %mask)
%res2 = call <4 x float> @llvm.x86.avx512.mask.loadu.ps.128(i8* %ptr, <4 x float> zeroinitializer, i8 %mask) %res2 = call <4 x float> @llvm.x86.avx512.mask.loadu.ps.128(i8* %ptr, <4 x float> zeroinitializer, i8 %mask)
%res4 = fadd <4 x float> %res2, %res1 %res4 = fadd <4 x float> %res2, %res1
ret <4 x float> %res4 ret <4 x float> %res4
} }
declare <4 x float> @llvm.x86.avx512.mask.loadu.ps.128(i8*, <4 x float>, i8) declare <4 x float> @llvm.x86.avx512.mask.loadu.ps.128(i8*, <4 x float>, i8)
define <2 x double> @test_mask_load_aligned_pd_128(<2 x double> %data, i8* %ptr, i8 %mask) { define <2 x double> @test_mask_load_aligned_pd_128(<2 x double> %data, i8* %ptr, i8 %mask) {
; CHECK-LABEL: test_mask_load_aligned_pd_128: ; CHECK-LABEL: test_mask_load_aligned_pd_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovapd (%rdi), %xmm0 ; CHECK-NEXT: vmovapd (%rdi), %xmm0
; CHECK-NEXT: vmovapd (%rdi), %xmm0 {%k1} ; CHECK-NEXT: vmovapd (%rdi), %xmm0 {%k1}
; CHECK-NEXT: vmovapd (%rdi), %xmm1 {%k1} {z} ; CHECK-NEXT: vmovapd (%rdi), %xmm1 {%k1} {z}
; CHECK-NEXT: vaddpd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vaddpd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.load.pd.128(i8* %ptr, <2 x double> zeroinitializer, i8 -1) %res = call <2 x double> @llvm.x86.avx512.mask.load.pd.128(i8* %ptr, <2 x double> zeroinitializer, i8 -1)
%res1 = call <2 x double> @llvm.x86.avx512.mask.load.pd.128(i8* %ptr, <2 x double> %res, i8 %mask) %res1 = call <2 x double> @llvm.x86.avx512.mask.load.pd.128(i8* %ptr, <2 x double> %res, i8 %mask)
%res2 = call <2 x double> @llvm.x86.avx512.mask.load.pd.128(i8* %ptr, <2 x double> zeroinitializer, i8 %mask) %res2 = call <2 x double> @llvm.x86.avx512.mask.load.pd.128(i8* %ptr, <2 x double> zeroinitializer, i8 %mask)
%res4 = fadd <2 x double> %res2, %res1 %res4 = fadd <2 x double> %res2, %res1
ret <2 x double> %res4 ret <2 x double> %res4
} }
declare <2 x double> @llvm.x86.avx512.mask.load.pd.128(i8*, <2 x double>, i8) declare <2 x double> @llvm.x86.avx512.mask.load.pd.128(i8*, <2 x double>, i8)
define <2 x double> @test_mask_load_unaligned_pd_128(<2 x double> %data, i8* %ptr, i8 %mask) { define <2 x double> @test_mask_load_unaligned_pd_128(<2 x double> %data, i8* %ptr, i8 %mask) {
; CHECK-LABEL: test_mask_load_unaligned_pd_128: ; CHECK-LABEL: test_mask_load_unaligned_pd_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovupd (%rdi), %xmm0 ; CHECK-NEXT: vmovupd (%rdi), %xmm0
; CHECK-NEXT: vmovupd (%rdi), %xmm0 {%k1} ; CHECK-NEXT: vmovupd (%rdi), %xmm0 {%k1}
; CHECK-NEXT: vmovupd (%rdi), %xmm1 {%k1} {z} ; CHECK-NEXT: vmovupd (%rdi), %xmm1 {%k1} {z}
; CHECK-NEXT: vaddpd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vaddpd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x double> @llvm.x86.avx512.mask.loadu.pd.128(i8* %ptr, <2 x double> zeroinitializer, i8 -1) %res = call <2 x double> @llvm.x86.avx512.mask.loadu.pd.128(i8* %ptr, <2 x double> zeroinitializer, i8 -1)
%res1 = call <2 x double> @llvm.x86.avx512.mask.loadu.pd.128(i8* %ptr, <2 x double> %res, i8 %mask) %res1 = call <2 x double> @llvm.x86.avx512.mask.loadu.pd.128(i8* %ptr, <2 x double> %res, i8 %mask)
%res2 = call <2 x double> @llvm.x86.avx512.mask.loadu.pd.128(i8* %ptr, <2 x double> zeroinitializer, i8 %mask) %res2 = call <2 x double> @llvm.x86.avx512.mask.loadu.pd.128(i8* %ptr, <2 x double> zeroinitializer, i8 %mask)
%res4 = fadd <2 x double> %res2, %res1 %res4 = fadd <2 x double> %res2, %res1
ret <2 x double> %res4 ret <2 x double> %res4
} }
declare <2 x double> @llvm.x86.avx512.mask.loadu.pd.128(i8*, <2 x double>, i8) declare <2 x double> @llvm.x86.avx512.mask.loadu.pd.128(i8*, <2 x double>, i8)
declare <4 x i32> @llvm.x86.avx512.mask.psrav4.si(<4 x i32>, <4 x i32>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.psrav4.si(<4 x i32>, <4 x i32>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_psrav4_si(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) { define <4 x i32>@test_int_x86_avx512_mask_psrav4_si(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psrav4_si: ; CHECK-LABEL: test_int_x86_avx512_mask_psrav4_si:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsravd %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vpsravd %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vpsravd %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: vpsravd %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: vpsravd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpsravd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm3, %xmm2, %xmm1 ; CHECK-NEXT: vpaddd %xmm3, %xmm2, %xmm1
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.psrav4.si(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) %res = call <4 x i32> @llvm.x86.avx512.mask.psrav4.si(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.psrav4.si(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %x3) %res1 = call <4 x i32> @llvm.x86.avx512.mask.psrav4.si(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %x3)
%res2 = call <4 x i32> @llvm.x86.avx512.mask.psrav4.si(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 -1) %res2 = call <4 x i32> @llvm.x86.avx512.mask.psrav4.si(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 -1)
%res3 = add <4 x i32> %res, %res1 %res3 = add <4 x i32> %res, %res1
%res4 = add <4 x i32> %res3, %res2 %res4 = add <4 x i32> %res3, %res2
ret <4 x i32> %res4 ret <4 x i32> %res4
} }
declare <8 x i32> @llvm.x86.avx512.mask.psrav8.si(<8 x i32>, <8 x i32>, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.psrav8.si(<8 x i32>, <8 x i32>, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_psrav8_si(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) { define <8 x i32>@test_int_x86_avx512_mask_psrav8_si(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psrav8_si: ; CHECK-LABEL: test_int_x86_avx512_mask_psrav8_si:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsravd %ymm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vpsravd %ymm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: vpsravd %ymm1, %ymm0, %ymm3 {%k1} {z} ; CHECK-NEXT: vpsravd %ymm1, %ymm0, %ymm3 {%k1} {z}
; CHECK-NEXT: vpsravd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vpsravd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm3, %ymm2, %ymm1 ; CHECK-NEXT: vpaddd %ymm3, %ymm2, %ymm1
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.psrav8.si(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) %res = call <8 x i32> @llvm.x86.avx512.mask.psrav8.si(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.psrav8.si(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> zeroinitializer, i8 %x3) %res1 = call <8 x i32> @llvm.x86.avx512.mask.psrav8.si(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> zeroinitializer, i8 %x3)
%res2 = call <8 x i32> @llvm.x86.avx512.mask.psrav8.si(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 -1) %res2 = call <8 x i32> @llvm.x86.avx512.mask.psrav8.si(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 -1)
%res3 = add <8 x i32> %res, %res1 %res3 = add <8 x i32> %res, %res1
%res4 = add <8 x i32> %res3, %res2 %res4 = add <8 x i32> %res3, %res2
ret <8 x i32> %res4 ret <8 x i32> %res4
} }
declare <2 x i64> @llvm.x86.avx512.mask.psrav.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8) declare <2 x i64> @llvm.x86.avx512.mask.psrav.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)
define <2 x i64>@test_int_x86_avx512_mask_psrav_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) { define <2 x i64>@test_int_x86_avx512_mask_psrav_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psrav_q_128: ; CHECK-LABEL: test_int_x86_avx512_mask_psrav_q_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsravq %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vpsravq %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vpsravq %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: vpsravq %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: vpsravq %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpsravq %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddq %xmm3, %xmm2, %xmm1 ; CHECK-NEXT: vpaddq %xmm3, %xmm2, %xmm1
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.mask.psrav.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) %res = call <2 x i64> @llvm.x86.avx512.mask.psrav.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)
%res1 = call <2 x i64> @llvm.x86.avx512.mask.psrav.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3) %res1 = call <2 x i64> @llvm.x86.avx512.mask.psrav.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)
%res2 = call <2 x i64> @llvm.x86.avx512.mask.psrav.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1) %res2 = call <2 x i64> @llvm.x86.avx512.mask.psrav.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)
%res3 = add <2 x i64> %res, %res1 %res3 = add <2 x i64> %res, %res1
%res4 = add <2 x i64> %res3, %res2 %res4 = add <2 x i64> %res3, %res2
ret <2 x i64> %res4 ret <2 x i64> %res4
} }
declare <4 x i64> @llvm.x86.avx512.mask.psrav.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.psrav.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_mask_psrav_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) { define <4 x i64>@test_int_x86_avx512_mask_psrav_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psrav_q_256: ; CHECK-LABEL: test_int_x86_avx512_mask_psrav_q_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsravq %ymm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vpsravq %ymm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: vpsravq %ymm1, %ymm0, %ymm3 {%k1} {z} ; CHECK-NEXT: vpsravq %ymm1, %ymm0, %ymm3 {%k1} {z}
; CHECK-NEXT: vpsravq %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vpsravq %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddq %ymm3, %ymm2, %ymm1 ; CHECK-NEXT: vpaddq %ymm3, %ymm2, %ymm1
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.psrav.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) %res = call <4 x i64> @llvm.x86.avx512.mask.psrav.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.psrav.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3) %res1 = call <4 x i64> @llvm.x86.avx512.mask.psrav.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)
%res2 = call <4 x i64> @llvm.x86.avx512.mask.psrav.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 -1) %res2 = call <4 x i64> @llvm.x86.avx512.mask.psrav.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 -1)
%res3 = add <4 x i64> %res, %res1 %res3 = add <4 x i64> %res, %res1
%res4 = add <4 x i64> %res3, %res2 %res4 = add <4 x i64> %res3, %res2
ret <4 x i64> %res4 ret <4 x i64> %res4
} }
declare <2 x i64> @llvm.x86.avx512.mask.psllv2.di(<2 x i64>, <2 x i64>, <2 x i64>, i8) declare <2 x i64> @llvm.x86.avx512.mask.psllv2.di(<2 x i64>, <2 x i64>, <2 x i64>, i8)
define <2 x i64>@test_int_x86_avx512_mask_psllv2_di(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) { define <2 x i64>@test_int_x86_avx512_mask_psllv2_di(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psllv2_di: ; CHECK-LABEL: test_int_x86_avx512_mask_psllv2_di:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsllvq %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vpsllvq %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vpsllvq %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: vpsllvq %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: vpsllvq %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddq %xmm3, %xmm2, %xmm1 ; CHECK-NEXT: vpaddq %xmm3, %xmm2, %xmm1
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.mask.psllv2.di(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) %res = call <2 x i64> @llvm.x86.avx512.mask.psllv2.di(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)
%res1 = call <2 x i64> @llvm.x86.avx512.mask.psllv2.di(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3) %res1 = call <2 x i64> @llvm.x86.avx512.mask.psllv2.di(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)
%res2 = call <2 x i64> @llvm.x86.avx512.mask.psllv2.di(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1) %res2 = call <2 x i64> @llvm.x86.avx512.mask.psllv2.di(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)
%res3 = add <2 x i64> %res, %res1 %res3 = add <2 x i64> %res, %res1
%res4 = add <2 x i64> %res3, %res2 %res4 = add <2 x i64> %res3, %res2
ret <2 x i64> %res4 ret <2 x i64> %res4
} }
declare <4 x i64> @llvm.x86.avx512.mask.psllv4.di(<4 x i64>, <4 x i64>, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.psllv4.di(<4 x i64>, <4 x i64>, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_mask_psllv4_di(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) { define <4 x i64>@test_int_x86_avx512_mask_psllv4_di(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psllv4_di: ; CHECK-LABEL: test_int_x86_avx512_mask_psllv4_di:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsllvq %ymm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vpsllvq %ymm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: vpsllvq %ymm1, %ymm0, %ymm3 {%k1} {z} ; CHECK-NEXT: vpsllvq %ymm1, %ymm0, %ymm3 {%k1} {z}
; CHECK-NEXT: vpsllvq %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vpsllvq %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddq %ymm3, %ymm2, %ymm1 ; CHECK-NEXT: vpaddq %ymm3, %ymm2, %ymm1
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.psllv4.di(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) %res = call <4 x i64> @llvm.x86.avx512.mask.psllv4.di(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.psllv4.di(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3) %res1 = call <4 x i64> @llvm.x86.avx512.mask.psllv4.di(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)
%res2 = call <4 x i64> @llvm.x86.avx512.mask.psllv4.di(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 -1) %res2 = call <4 x i64> @llvm.x86.avx512.mask.psllv4.di(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 -1)
%res3 = add <4 x i64> %res, %res1 %res3 = add <4 x i64> %res, %res1
%res4 = add <4 x i64> %res3, %res2 %res4 = add <4 x i64> %res3, %res2
ret <4 x i64> %res4 ret <4 x i64> %res4
} }
declare <4 x i32> @llvm.x86.avx512.mask.psllv4.si(<4 x i32>, <4 x i32>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.psllv4.si(<4 x i32>, <4 x i32>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_psllv4_si(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) { define <4 x i32>@test_int_x86_avx512_mask_psllv4_si(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psllv4_si: ; CHECK-LABEL: test_int_x86_avx512_mask_psllv4_si:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsllvd %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vpsllvd %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vpsllvd %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: vpsllvd %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: vpsllvd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm3, %xmm2, %xmm1 ; CHECK-NEXT: vpaddd %xmm3, %xmm2, %xmm1
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.psllv4.si(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) %res = call <4 x i32> @llvm.x86.avx512.mask.psllv4.si(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.psllv4.si(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %x3) %res1 = call <4 x i32> @llvm.x86.avx512.mask.psllv4.si(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %x3)
%res2 = call <4 x i32> @llvm.x86.avx512.mask.psllv4.si(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 -1) %res2 = call <4 x i32> @llvm.x86.avx512.mask.psllv4.si(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 -1)
%res3 = add <4 x i32> %res, %res1 %res3 = add <4 x i32> %res, %res1
%res4 = add <4 x i32> %res3, %res2 %res4 = add <4 x i32> %res3, %res2
ret <4 x i32> %res4 ret <4 x i32> %res4
} }
declare <8 x i32> @llvm.x86.avx512.mask.psllv8.si(<8 x i32>, <8 x i32>, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.psllv8.si(<8 x i32>, <8 x i32>, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_psllv8_si(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) { define <8 x i32>@test_int_x86_avx512_mask_psllv8_si(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_psllv8_si: ; CHECK-LABEL: test_int_x86_avx512_mask_psllv8_si:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpsllvd %ymm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vpsllvd %ymm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: vpsllvd %ymm1, %ymm0, %ymm3 {%k1} {z} ; CHECK-NEXT: vpsllvd %ymm1, %ymm0, %ymm3 {%k1} {z}
; CHECK-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm3, %ymm2, %ymm1 ; CHECK-NEXT: vpaddd %ymm3, %ymm2, %ymm1
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.psllv8.si(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) %res = call <8 x i32> @llvm.x86.avx512.mask.psllv8.si(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.psllv8.si(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> zeroinitializer, i8 %x3) %res1 = call <8 x i32> @llvm.x86.avx512.mask.psllv8.si(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> zeroinitializer, i8 %x3)
%res2 = call <8 x i32> @llvm.x86.avx512.mask.psllv8.si(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 -1) %res2 = call <8 x i32> @llvm.x86.avx512.mask.psllv8.si(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 -1)
%res3 = add <8 x i32> %res, %res1 %res3 = add <8 x i32> %res, %res1
%res4 = add <8 x i32> %res3, %res2 %res4 = add <8 x i32> %res3, %res2
ret <8 x i32> %res4 ret <8 x i32> %res4
} }
declare <4 x i32> @llvm.x86.avx512.mask.prorv.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.prorv.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_prorv_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) { define <4 x i32>@test_int_x86_avx512_mask_prorv_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_prorv_d_128: ; CHECK-LABEL: test_int_x86_avx512_mask_prorv_d_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vprorvd %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vprorvd %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vprorvd %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: vprorvd %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: vprorvd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vprorvd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm3, %xmm2, %xmm1 ; CHECK-NEXT: vpaddd %xmm3, %xmm2, %xmm1
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.prorv.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) %res = call <4 x i32> @llvm.x86.avx512.mask.prorv.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.prorv.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %x3) %res1 = call <4 x i32> @llvm.x86.avx512.mask.prorv.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %x3)
%res2 = call <4 x i32> @llvm.x86.avx512.mask.prorv.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 -1) %res2 = call <4 x i32> @llvm.x86.avx512.mask.prorv.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 -1)
%res3 = add <4 x i32> %res, %res1 %res3 = add <4 x i32> %res, %res1
%res4 = add <4 x i32> %res3, %res2 %res4 = add <4 x i32> %res3, %res2
ret <4 x i32> %res4 ret <4 x i32> %res4
} }
declare <8 x i32> @llvm.x86.avx512.mask.prorv.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.prorv.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_prorv_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) { define <8 x i32>@test_int_x86_avx512_mask_prorv_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_prorv_d_256: ; CHECK-LABEL: test_int_x86_avx512_mask_prorv_d_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vprorvd %ymm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vprorvd %ymm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: vprorvd %ymm1, %ymm0, %ymm3 {%k1} {z} ; CHECK-NEXT: vprorvd %ymm1, %ymm0, %ymm3 {%k1} {z}
; CHECK-NEXT: vprorvd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vprorvd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm3, %ymm2, %ymm1 ; CHECK-NEXT: vpaddd %ymm3, %ymm2, %ymm1
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.prorv.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) %res = call <8 x i32> @llvm.x86.avx512.mask.prorv.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.prorv.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> zeroinitializer, i8 %x3) %res1 = call <8 x i32> @llvm.x86.avx512.mask.prorv.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> zeroinitializer, i8 %x3)
%res2 = call <8 x i32> @llvm.x86.avx512.mask.prorv.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 -1) %res2 = call <8 x i32> @llvm.x86.avx512.mask.prorv.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 -1)
%res3 = add <8 x i32> %res, %res1 %res3 = add <8 x i32> %res, %res1
%res4 = add <8 x i32> %res3, %res2 %res4 = add <8 x i32> %res3, %res2
ret <8 x i32> %res4 ret <8 x i32> %res4
} }
declare <2 x i64> @llvm.x86.avx512.mask.prorv.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8) declare <2 x i64> @llvm.x86.avx512.mask.prorv.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)
define <2 x i64>@test_int_x86_avx512_mask_prorv_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) { define <2 x i64>@test_int_x86_avx512_mask_prorv_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_prorv_q_128: ; CHECK-LABEL: test_int_x86_avx512_mask_prorv_q_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vprorvq %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vprorvq %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vprorvq %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: vprorvq %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: vprorvq %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vprorvq %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddq %xmm3, %xmm2, %xmm1 ; CHECK-NEXT: vpaddq %xmm3, %xmm2, %xmm1
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.mask.prorv.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) %res = call <2 x i64> @llvm.x86.avx512.mask.prorv.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)
%res1 = call <2 x i64> @llvm.x86.avx512.mask.prorv.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3) %res1 = call <2 x i64> @llvm.x86.avx512.mask.prorv.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)
%res2 = call <2 x i64> @llvm.x86.avx512.mask.prorv.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1) %res2 = call <2 x i64> @llvm.x86.avx512.mask.prorv.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)
%res3 = add <2 x i64> %res, %res1 %res3 = add <2 x i64> %res, %res1
%res4 = add <2 x i64> %res3, %res2 %res4 = add <2 x i64> %res3, %res2
ret <2 x i64> %res4 ret <2 x i64> %res4
} }
declare <4 x i64> @llvm.x86.avx512.mask.prorv.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.prorv.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_mask_prorv_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) { define <4 x i64>@test_int_x86_avx512_mask_prorv_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_prorv_q_256: ; CHECK-LABEL: test_int_x86_avx512_mask_prorv_q_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vprorvq %ymm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vprorvq %ymm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: vprorvq %ymm1, %ymm0, %ymm3 {%k1} {z} ; CHECK-NEXT: vprorvq %ymm1, %ymm0, %ymm3 {%k1} {z}
; CHECK-NEXT: vprorvq %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vprorvq %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddq %ymm3, %ymm2, %ymm1 ; CHECK-NEXT: vpaddq %ymm3, %ymm2, %ymm1
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.prorv.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) %res = call <4 x i64> @llvm.x86.avx512.mask.prorv.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.prorv.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3) %res1 = call <4 x i64> @llvm.x86.avx512.mask.prorv.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)
%res2 = call <4 x i64> @llvm.x86.avx512.mask.prorv.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 -1) %res2 = call <4 x i64> @llvm.x86.avx512.mask.prorv.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 -1)
%res3 = add <4 x i64> %res, %res1 %res3 = add <4 x i64> %res, %res1
%res4 = add <4 x i64> %res3, %res2 %res4 = add <4 x i64> %res3, %res2
ret <4 x i64> %res4 ret <4 x i64> %res4
} }
declare <4 x i32> @llvm.x86.avx512.mask.prol.d.128(<4 x i32>, i8, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.prol.d.128(<4 x i32>, i8, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_prol_d_128(<4 x i32> %x0, i8 %x1, <4 x i32> %x2, i8 %x3) { define <4 x i32>@test_int_x86_avx512_mask_prol_d_128(<4 x i32> %x0, i8 %x1, <4 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_prol_d_128: ; CHECK-LABEL: test_int_x86_avx512_mask_prol_d_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vprold $3, %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vprold $3, %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vprold $3, %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vprold $3, %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vprold $3, %xmm0, %xmm0 ; CHECK-NEXT: vprold $3, %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.prol.d.128(<4 x i32> %x0, i8 3, <4 x i32> %x2, i8 %x3) %res = call <4 x i32> @llvm.x86.avx512.mask.prol.d.128(<4 x i32> %x0, i8 3, <4 x i32> %x2, i8 %x3)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.prol.d.128(<4 x i32> %x0, i8 3, <4 x i32> zeroinitializer, i8 %x3) %res1 = call <4 x i32> @llvm.x86.avx512.mask.prol.d.128(<4 x i32> %x0, i8 3, <4 x i32> zeroinitializer, i8 %x3)
%res2 = call <4 x i32> @llvm.x86.avx512.mask.prol.d.128(<4 x i32> %x0, i8 3, <4 x i32> %x2, i8 -1) %res2 = call <4 x i32> @llvm.x86.avx512.mask.prol.d.128(<4 x i32> %x0, i8 3, <4 x i32> %x2, i8 -1)
%res3 = add <4 x i32> %res, %res1 %res3 = add <4 x i32> %res, %res1
%res4 = add <4 x i32> %res3, %res2 %res4 = add <4 x i32> %res3, %res2
ret <4 x i32> %res4 ret <4 x i32> %res4
} }
declare <8 x i32> @llvm.x86.avx512.mask.prol.d.256(<8 x i32>, i8, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.prol.d.256(<8 x i32>, i8, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_prol_d_256(<8 x i32> %x0, i8 %x1, <8 x i32> %x2, i8 %x3) { define <8 x i32>@test_int_x86_avx512_mask_prol_d_256(<8 x i32> %x0, i8 %x1, <8 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_prol_d_256: ; CHECK-LABEL: test_int_x86_avx512_mask_prol_d_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vprold $3, %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vprold $3, %ymm0, %ymm1 {%k1}
; CHECK-NEXT: vprold $3, %ymm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vprold $3, %ymm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vprold $3, %ymm0, %ymm0 ; CHECK-NEXT: vprold $3, %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm2, %ymm1, %ymm1 ; CHECK-NEXT: vpaddd %ymm2, %ymm1, %ymm1
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.prol.d.256(<8 x i32> %x0, i8 3, <8 x i32> %x2, i8 %x3) %res = call <8 x i32> @llvm.x86.avx512.mask.prol.d.256(<8 x i32> %x0, i8 3, <8 x i32> %x2, i8 %x3)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.prol.d.256(<8 x i32> %x0, i8 3, <8 x i32> zeroinitializer, i8 %x3) %res1 = call <8 x i32> @llvm.x86.avx512.mask.prol.d.256(<8 x i32> %x0, i8 3, <8 x i32> zeroinitializer, i8 %x3)
%res2 = call <8 x i32> @llvm.x86.avx512.mask.prol.d.256(<8 x i32> %x0, i8 3, <8 x i32> %x2, i8 -1) %res2 = call <8 x i32> @llvm.x86.avx512.mask.prol.d.256(<8 x i32> %x0, i8 3, <8 x i32> %x2, i8 -1)
%res3 = add <8 x i32> %res, %res1 %res3 = add <8 x i32> %res, %res1
%res4 = add <8 x i32> %res3, %res2 %res4 = add <8 x i32> %res3, %res2
ret <8 x i32> %res4 ret <8 x i32> %res4
} }
declare <2 x i64> @llvm.x86.avx512.mask.prol.q.128(<2 x i64>, i8, <2 x i64>, i8) declare <2 x i64> @llvm.x86.avx512.mask.prol.q.128(<2 x i64>, i8, <2 x i64>, i8)
define <2 x i64>@test_int_x86_avx512_mask_prol_q_128(<2 x i64> %x0, i8 %x1, <2 x i64> %x2, i8 %x3) { define <2 x i64>@test_int_x86_avx512_mask_prol_q_128(<2 x i64> %x0, i8 %x1, <2 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_prol_q_128: ; CHECK-LABEL: test_int_x86_avx512_mask_prol_q_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vprolq $3, %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vprolq $3, %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vprolq $3, %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vprolq $3, %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vprolq $3, %xmm0, %xmm0 ; CHECK-NEXT: vprolq $3, %xmm0, %xmm0
; CHECK-NEXT: vpaddq %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpaddq %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.mask.prol.q.128(<2 x i64> %x0, i8 3, <2 x i64> %x2, i8 %x3) %res = call <2 x i64> @llvm.x86.avx512.mask.prol.q.128(<2 x i64> %x0, i8 3, <2 x i64> %x2, i8 %x3)
%res1 = call <2 x i64> @llvm.x86.avx512.mask.prol.q.128(<2 x i64> %x0, i8 3, <2 x i64> zeroinitializer, i8 %x3) %res1 = call <2 x i64> @llvm.x86.avx512.mask.prol.q.128(<2 x i64> %x0, i8 3, <2 x i64> zeroinitializer, i8 %x3)
%res2 = call <2 x i64> @llvm.x86.avx512.mask.prol.q.128(<2 x i64> %x0, i8 3, <2 x i64> %x2, i8 -1) %res2 = call <2 x i64> @llvm.x86.avx512.mask.prol.q.128(<2 x i64> %x0, i8 3, <2 x i64> %x2, i8 -1)
%res3 = add <2 x i64> %res, %res1 %res3 = add <2 x i64> %res, %res1
%res4 = add <2 x i64> %res3, %res2 %res4 = add <2 x i64> %res3, %res2
ret <2 x i64> %res4 ret <2 x i64> %res4
} }
declare <4 x i64> @llvm.x86.avx512.mask.prol.q.256(<4 x i64>, i8, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.prol.q.256(<4 x i64>, i8, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_mask_prol_q_256(<4 x i64> %x0, i8 %x1, <4 x i64> %x2, i8 %x3) { define <4 x i64>@test_int_x86_avx512_mask_prol_q_256(<4 x i64> %x0, i8 %x1, <4 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_prol_q_256: ; CHECK-LABEL: test_int_x86_avx512_mask_prol_q_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vprolq $3, %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vprolq $3, %ymm0, %ymm1 {%k1}
; CHECK-NEXT: vprolq $3, %ymm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vprolq $3, %ymm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vprolq $3, %ymm0, %ymm0 ; CHECK-NEXT: vprolq $3, %ymm0, %ymm0
; CHECK-NEXT: vpaddq %ymm2, %ymm1, %ymm1 ; CHECK-NEXT: vpaddq %ymm2, %ymm1, %ymm1
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.prol.q.256(<4 x i64> %x0, i8 3, <4 x i64> %x2, i8 %x3) %res = call <4 x i64> @llvm.x86.avx512.mask.prol.q.256(<4 x i64> %x0, i8 3, <4 x i64> %x2, i8 %x3)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.prol.q.256(<4 x i64> %x0, i8 3, <4 x i64> zeroinitializer, i8 %x3) %res1 = call <4 x i64> @llvm.x86.avx512.mask.prol.q.256(<4 x i64> %x0, i8 3, <4 x i64> zeroinitializer, i8 %x3)
%res2 = call <4 x i64> @llvm.x86.avx512.mask.prol.q.256(<4 x i64> %x0, i8 3, <4 x i64> %x2, i8 -1) %res2 = call <4 x i64> @llvm.x86.avx512.mask.prol.q.256(<4 x i64> %x0, i8 3, <4 x i64> %x2, i8 -1)
%res3 = add <4 x i64> %res, %res1 %res3 = add <4 x i64> %res, %res1
%res4 = add <4 x i64> %res3, %res2 %res4 = add <4 x i64> %res3, %res2
ret <4 x i64> %res4 ret <4 x i64> %res4
} }
declare <4 x i32> @llvm.x86.avx512.mask.load.d.128(i8*, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.load.d.128(i8*, <4 x i32>, i8)
define <4 x i32> @test_mask_load_aligned_d_128(<4 x i32> %data, i8* %ptr, i8 %mask) { define <4 x i32> @test_mask_load_aligned_d_128(<4 x i32> %data, i8* %ptr, i8 %mask) {
; CHECK-LABEL: test_mask_load_aligned_d_128: ; CHECK-LABEL: test_mask_load_aligned_d_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovdqa32 (%rdi), %xmm0 ; CHECK-NEXT: vmovdqa32 (%rdi), %xmm0
; CHECK-NEXT: vmovdqa32 (%rdi), %xmm0 {%k1} ; CHECK-NEXT: vmovdqa32 (%rdi), %xmm0 {%k1}
; CHECK-NEXT: vmovdqa32 (%rdi), %xmm1 {%k1} {z} ; CHECK-NEXT: vmovdqa32 (%rdi), %xmm1 {%k1} {z}
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.load.d.128(i8* %ptr, <4 x i32> zeroinitializer, i8 -1) %res = call <4 x i32> @llvm.x86.avx512.mask.load.d.128(i8* %ptr, <4 x i32> zeroinitializer, i8 -1)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.load.d.128(i8* %ptr, <4 x i32> %res, i8 %mask) %res1 = call <4 x i32> @llvm.x86.avx512.mask.load.d.128(i8* %ptr, <4 x i32> %res, i8 %mask)
%res2 = call <4 x i32> @llvm.x86.avx512.mask.load.d.128(i8* %ptr, <4 x i32> zeroinitializer, i8 %mask) %res2 = call <4 x i32> @llvm.x86.avx512.mask.load.d.128(i8* %ptr, <4 x i32> zeroinitializer, i8 %mask)
%res4 = add <4 x i32> %res2, %res1 %res4 = add <4 x i32> %res2, %res1
ret <4 x i32> %res4 ret <4 x i32> %res4
} }
declare <8 x i32> @llvm.x86.avx512.mask.load.d.256(i8*, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.load.d.256(i8*, <8 x i32>, i8)
define <8 x i32> @test_mask_load_aligned_d_256(<8 x i32> %data, i8* %ptr, i8 %mask) { define <8 x i32> @test_mask_load_aligned_d_256(<8 x i32> %data, i8* %ptr, i8 %mask) {
; CHECK-LABEL: test_mask_load_aligned_d_256: ; CHECK-LABEL: test_mask_load_aligned_d_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovdqa32 (%rdi), %ymm0 ; CHECK-NEXT: vmovdqa32 (%rdi), %ymm0
; CHECK-NEXT: vmovdqa32 (%rdi), %ymm0 {%k1} ; CHECK-NEXT: vmovdqa32 (%rdi), %ymm0 {%k1}
; CHECK-NEXT: vmovdqa32 (%rdi), %ymm1 {%k1} {z} ; CHECK-NEXT: vmovdqa32 (%rdi), %ymm1 {%k1} {z}
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.load.d.256(i8* %ptr, <8 x i32> zeroinitializer, i8 -1) %res = call <8 x i32> @llvm.x86.avx512.mask.load.d.256(i8* %ptr, <8 x i32> zeroinitializer, i8 -1)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.load.d.256(i8* %ptr, <8 x i32> %res, i8 %mask) %res1 = call <8 x i32> @llvm.x86.avx512.mask.load.d.256(i8* %ptr, <8 x i32> %res, i8 %mask)
%res2 = call <8 x i32> @llvm.x86.avx512.mask.load.d.256(i8* %ptr, <8 x i32> zeroinitializer, i8 %mask) %res2 = call <8 x i32> @llvm.x86.avx512.mask.load.d.256(i8* %ptr, <8 x i32> zeroinitializer, i8 %mask)
%res4 = add <8 x i32> %res2, %res1 %res4 = add <8 x i32> %res2, %res1
ret <8 x i32> %res4 ret <8 x i32> %res4
} }
declare <2 x i64> @llvm.x86.avx512.mask.load.q.128(i8*, <2 x i64>, i8) declare <2 x i64> @llvm.x86.avx512.mask.load.q.128(i8*, <2 x i64>, i8)
define <2 x i64> @test_mask_load_aligned_q_128(<2 x i64> %data, i8* %ptr, i8 %mask) { define <2 x i64> @test_mask_load_aligned_q_128(<2 x i64> %data, i8* %ptr, i8 %mask) {
; CHECK-LABEL: test_mask_load_aligned_q_128: ; CHECK-LABEL: test_mask_load_aligned_q_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovdqa64 (%rdi), %xmm0 ; CHECK-NEXT: vmovdqa64 (%rdi), %xmm0
; CHECK-NEXT: vmovdqa64 (%rdi), %xmm0 {%k1} ; CHECK-NEXT: vmovdqa64 (%rdi), %xmm0 {%k1}
; CHECK-NEXT: vmovdqa64 (%rdi), %xmm1 {%k1} {z} ; CHECK-NEXT: vmovdqa64 (%rdi), %xmm1 {%k1} {z}
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.mask.load.q.128(i8* %ptr, <2 x i64> zeroinitializer, i8 -1) %res = call <2 x i64> @llvm.x86.avx512.mask.load.q.128(i8* %ptr, <2 x i64> zeroinitializer, i8 -1)
%res1 = call <2 x i64> @llvm.x86.avx512.mask.load.q.128(i8* %ptr, <2 x i64> %res, i8 %mask) %res1 = call <2 x i64> @llvm.x86.avx512.mask.load.q.128(i8* %ptr, <2 x i64> %res, i8 %mask)
%res2 = call <2 x i64> @llvm.x86.avx512.mask.load.q.128(i8* %ptr, <2 x i64> zeroinitializer, i8 %mask) %res2 = call <2 x i64> @llvm.x86.avx512.mask.load.q.128(i8* %ptr, <2 x i64> zeroinitializer, i8 %mask)
%res4 = add <2 x i64> %res2, %res1 %res4 = add <2 x i64> %res2, %res1
ret <2 x i64> %res4 ret <2 x i64> %res4
} }
declare <4 x i64> @llvm.x86.avx512.mask.load.q.256(i8*, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.load.q.256(i8*, <4 x i64>, i8)
define <4 x i64> @test_mask_load_aligned_q_256(<4 x i64> %data, i8* %ptr, i8 %mask) { define <4 x i64> @test_mask_load_aligned_q_256(<4 x i64> %data, i8* %ptr, i8 %mask) {
; CHECK-LABEL: test_mask_load_aligned_q_256: ; CHECK-LABEL: test_mask_load_aligned_q_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovdqa64 (%rdi), %ymm0 ; CHECK-NEXT: vmovdqa64 (%rdi), %ymm0
; CHECK-NEXT: vmovdqa64 (%rdi), %ymm0 {%k1} ; CHECK-NEXT: vmovdqa64 (%rdi), %ymm0 {%k1}
; CHECK-NEXT: vmovdqa64 (%rdi), %ymm1 {%k1} {z} ; CHECK-NEXT: vmovdqa64 (%rdi), %ymm1 {%k1} {z}
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.load.q.256(i8* %ptr, <4 x i64> zeroinitializer, i8 -1) %res = call <4 x i64> @llvm.x86.avx512.mask.load.q.256(i8* %ptr, <4 x i64> zeroinitializer, i8 -1)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.load.q.256(i8* %ptr, <4 x i64> %res, i8 %mask) %res1 = call <4 x i64> @llvm.x86.avx512.mask.load.q.256(i8* %ptr, <4 x i64> %res, i8 %mask)
%res2 = call <4 x i64> @llvm.x86.avx512.mask.load.q.256(i8* %ptr, <4 x i64> zeroinitializer, i8 %mask) %res2 = call <4 x i64> @llvm.x86.avx512.mask.load.q.256(i8* %ptr, <4 x i64> zeroinitializer, i8 %mask)
%res4 = add <4 x i64> %res2, %res1 %res4 = add <4 x i64> %res2, %res1
ret <4 x i64> %res4 ret <4 x i64> %res4
} }
declare <4 x i32> @llvm.x86.avx512.mask.prolv.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.prolv.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_prolv_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) { define <4 x i32>@test_int_x86_avx512_mask_prolv_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_prolv_d_128: ; CHECK-LABEL: test_int_x86_avx512_mask_prolv_d_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vprolvd %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vprolvd %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vprolvd %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: vprolvd %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: vprolvd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vprolvd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm3, %xmm2, %xmm1 ; CHECK-NEXT: vpaddd %xmm3, %xmm2, %xmm1
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.prolv.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) %res = call <4 x i32> @llvm.x86.avx512.mask.prolv.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.prolv.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %x3) %res1 = call <4 x i32> @llvm.x86.avx512.mask.prolv.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %x3)
%res2 = call <4 x i32> @llvm.x86.avx512.mask.prolv.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 -1) %res2 = call <4 x i32> @llvm.x86.avx512.mask.prolv.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 -1)
%res3 = add <4 x i32> %res, %res1 %res3 = add <4 x i32> %res, %res1
%res4 = add <4 x i32> %res3, %res2 %res4 = add <4 x i32> %res3, %res2
ret <4 x i32> %res4 ret <4 x i32> %res4
} }
declare <8 x i32> @llvm.x86.avx512.mask.prolv.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.prolv.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_prolv_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) { define <8 x i32>@test_int_x86_avx512_mask_prolv_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_prolv_d_256: ; CHECK-LABEL: test_int_x86_avx512_mask_prolv_d_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vprolvd %ymm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vprolvd %ymm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: vprolvd %ymm1, %ymm0, %ymm3 {%k1} {z} ; CHECK-NEXT: vprolvd %ymm1, %ymm0, %ymm3 {%k1} {z}
; CHECK-NEXT: vprolvd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vprolvd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm3, %ymm2, %ymm1 ; CHECK-NEXT: vpaddd %ymm3, %ymm2, %ymm1
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.prolv.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) %res = call <8 x i32> @llvm.x86.avx512.mask.prolv.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.prolv.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> zeroinitializer, i8 %x3) %res1 = call <8 x i32> @llvm.x86.avx512.mask.prolv.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> zeroinitializer, i8 %x3)
%res2 = call <8 x i32> @llvm.x86.avx512.mask.prolv.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 -1) %res2 = call <8 x i32> @llvm.x86.avx512.mask.prolv.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 -1)
%res3 = add <8 x i32> %res, %res1 %res3 = add <8 x i32> %res, %res1
%res4 = add <8 x i32> %res3, %res2 %res4 = add <8 x i32> %res3, %res2
ret <8 x i32> %res4 ret <8 x i32> %res4
} }
declare <2 x i64> @llvm.x86.avx512.mask.prolv.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8) declare <2 x i64> @llvm.x86.avx512.mask.prolv.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)
define <2 x i64>@test_int_x86_avx512_mask_prolv_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) { define <2 x i64>@test_int_x86_avx512_mask_prolv_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_prolv_q_128: ; CHECK-LABEL: test_int_x86_avx512_mask_prolv_q_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vprolvq %xmm1, %xmm0, %xmm2 {%k1} ; CHECK-NEXT: vprolvq %xmm1, %xmm0, %xmm2 {%k1}
; CHECK-NEXT: vprolvq %xmm1, %xmm0, %xmm3 {%k1} {z} ; CHECK-NEXT: vprolvq %xmm1, %xmm0, %xmm3 {%k1} {z}
; CHECK-NEXT: vprolvq %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vprolvq %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddq %xmm3, %xmm2, %xmm1 ; CHECK-NEXT: vpaddq %xmm3, %xmm2, %xmm1
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.mask.prolv.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) %res = call <2 x i64> @llvm.x86.avx512.mask.prolv.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)
%res1 = call <2 x i64> @llvm.x86.avx512.mask.prolv.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3) %res1 = call <2 x i64> @llvm.x86.avx512.mask.prolv.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)
%res2 = call <2 x i64> @llvm.x86.avx512.mask.prolv.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1) %res2 = call <2 x i64> @llvm.x86.avx512.mask.prolv.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)
%res3 = add <2 x i64> %res, %res1 %res3 = add <2 x i64> %res, %res1
%res4 = add <2 x i64> %res3, %res2 %res4 = add <2 x i64> %res3, %res2
ret <2 x i64> %res4 ret <2 x i64> %res4
} }
declare <4 x i64> @llvm.x86.avx512.mask.prolv.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.prolv.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_mask_prolv_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) { define <4 x i64>@test_int_x86_avx512_mask_prolv_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_prolv_q_256: ; CHECK-LABEL: test_int_x86_avx512_mask_prolv_q_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vprolvq %ymm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vprolvq %ymm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: vprolvq %ymm1, %ymm0, %ymm3 {%k1} {z} ; CHECK-NEXT: vprolvq %ymm1, %ymm0, %ymm3 {%k1} {z}
; CHECK-NEXT: vprolvq %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vprolvq %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddq %ymm3, %ymm2, %ymm1 ; CHECK-NEXT: vpaddq %ymm3, %ymm2, %ymm1
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.prolv.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) %res = call <4 x i64> @llvm.x86.avx512.mask.prolv.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.prolv.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3) %res1 = call <4 x i64> @llvm.x86.avx512.mask.prolv.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)
%res2 = call <4 x i64> @llvm.x86.avx512.mask.prolv.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 -1) %res2 = call <4 x i64> @llvm.x86.avx512.mask.prolv.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 -1)
%res3 = add <4 x i64> %res, %res1 %res3 = add <4 x i64> %res, %res1
%res4 = add <4 x i64> %res3, %res2 %res4 = add <4 x i64> %res3, %res2
ret <4 x i64> %res4 ret <4 x i64> %res4
} }
declare <4 x i32> @llvm.x86.avx512.mask.pror.d.128(<4 x i32>, i8, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.pror.d.128(<4 x i32>, i8, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_pror_d_128(<4 x i32> %x0, i8 %x1, <4 x i32> %x2, i8 %x3) { define <4 x i32>@test_int_x86_avx512_mask_pror_d_128(<4 x i32> %x0, i8 %x1, <4 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_pror_d_128: ; CHECK-LABEL: test_int_x86_avx512_mask_pror_d_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vprord $3, %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vprord $3, %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vprord $3, %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vprord $3, %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vprord $3, %xmm0, %xmm0 ; CHECK-NEXT: vprord $3, %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.pror.d.128(<4 x i32> %x0, i8 3, <4 x i32> %x2, i8 %x3) %res = call <4 x i32> @llvm.x86.avx512.mask.pror.d.128(<4 x i32> %x0, i8 3, <4 x i32> %x2, i8 %x3)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.pror.d.128(<4 x i32> %x0, i8 3, <4 x i32> zeroinitializer, i8 %x3) %res1 = call <4 x i32> @llvm.x86.avx512.mask.pror.d.128(<4 x i32> %x0, i8 3, <4 x i32> zeroinitializer, i8 %x3)
%res2 = call <4 x i32> @llvm.x86.avx512.mask.pror.d.128(<4 x i32> %x0, i8 3, <4 x i32> %x2, i8 -1) %res2 = call <4 x i32> @llvm.x86.avx512.mask.pror.d.128(<4 x i32> %x0, i8 3, <4 x i32> %x2, i8 -1)
%res3 = add <4 x i32> %res, %res1 %res3 = add <4 x i32> %res, %res1
%res4 = add <4 x i32> %res3, %res2 %res4 = add <4 x i32> %res3, %res2
ret <4 x i32> %res4 ret <4 x i32> %res4
} }
declare <8 x i32> @llvm.x86.avx512.mask.pror.d.256(<8 x i32>, i8, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.pror.d.256(<8 x i32>, i8, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_pror_d_256(<8 x i32> %x0, i32 %x1, <8 x i32> %x2, i8 %x3) { define <8 x i32>@test_int_x86_avx512_mask_pror_d_256(<8 x i32> %x0, i32 %x1, <8 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_pror_d_256: ; CHECK-LABEL: test_int_x86_avx512_mask_pror_d_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vprord $3, %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vprord $3, %ymm0, %ymm1 {%k1}
; CHECK-NEXT: vprord $3, %ymm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vprord $3, %ymm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vprord $3, %ymm0, %ymm0 ; CHECK-NEXT: vprord $3, %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm2, %ymm1, %ymm1 ; CHECK-NEXT: vpaddd %ymm2, %ymm1, %ymm1
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.pror.d.256(<8 x i32> %x0, i8 3, <8 x i32> %x2, i8 %x3) %res = call <8 x i32> @llvm.x86.avx512.mask.pror.d.256(<8 x i32> %x0, i8 3, <8 x i32> %x2, i8 %x3)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.pror.d.256(<8 x i32> %x0, i8 3, <8 x i32> zeroinitializer, i8 %x3) %res1 = call <8 x i32> @llvm.x86.avx512.mask.pror.d.256(<8 x i32> %x0, i8 3, <8 x i32> zeroinitializer, i8 %x3)
%res2 = call <8 x i32> @llvm.x86.avx512.mask.pror.d.256(<8 x i32> %x0, i8 3, <8 x i32> %x2, i8 -1) %res2 = call <8 x i32> @llvm.x86.avx512.mask.pror.d.256(<8 x i32> %x0, i8 3, <8 x i32> %x2, i8 -1)
%res3 = add <8 x i32> %res, %res1 %res3 = add <8 x i32> %res, %res1
%res4 = add <8 x i32> %res3, %res2 %res4 = add <8 x i32> %res3, %res2
ret <8 x i32> %res4 ret <8 x i32> %res4
} }
declare <2 x i64> @llvm.x86.avx512.mask.pror.q.128(<2 x i64>, i8, <2 x i64>, i8) declare <2 x i64> @llvm.x86.avx512.mask.pror.q.128(<2 x i64>, i8, <2 x i64>, i8)
define <2 x i64>@test_int_x86_avx512_mask_pror_q_128(<2 x i64> %x0, i8 %x1, <2 x i64> %x2, i8 %x3) { define <2 x i64>@test_int_x86_avx512_mask_pror_q_128(<2 x i64> %x0, i8 %x1, <2 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_pror_q_128: ; CHECK-LABEL: test_int_x86_avx512_mask_pror_q_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vprorq $3, %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vprorq $3, %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vprorq $3, %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vprorq $3, %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vprorq $3, %xmm0, %xmm0 ; CHECK-NEXT: vprorq $3, %xmm0, %xmm0
; CHECK-NEXT: vpaddq %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpaddq %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.mask.pror.q.128(<2 x i64> %x0, i8 3, <2 x i64> %x2, i8 %x3) %res = call <2 x i64> @llvm.x86.avx512.mask.pror.q.128(<2 x i64> %x0, i8 3, <2 x i64> %x2, i8 %x3)
%res1 = call <2 x i64> @llvm.x86.avx512.mask.pror.q.128(<2 x i64> %x0, i8 3, <2 x i64> zeroinitializer, i8 %x3) %res1 = call <2 x i64> @llvm.x86.avx512.mask.pror.q.128(<2 x i64> %x0, i8 3, <2 x i64> zeroinitializer, i8 %x3)
%res2 = call <2 x i64> @llvm.x86.avx512.mask.pror.q.128(<2 x i64> %x0, i8 3, <2 x i64> %x2, i8 -1) %res2 = call <2 x i64> @llvm.x86.avx512.mask.pror.q.128(<2 x i64> %x0, i8 3, <2 x i64> %x2, i8 -1)
%res3 = add <2 x i64> %res, %res1 %res3 = add <2 x i64> %res, %res1
%res4 = add <2 x i64> %res3, %res2 %res4 = add <2 x i64> %res3, %res2
ret <2 x i64> %res4 ret <2 x i64> %res4
} }
declare <4 x i64> @llvm.x86.avx512.mask.pror.q.256(<4 x i64>, i8, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.pror.q.256(<4 x i64>, i8, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_mask_pror_q_256(<4 x i64> %x0, i8 %x1, <4 x i64> %x2, i8 %x3) { define <4 x i64>@test_int_x86_avx512_mask_pror_q_256(<4 x i64> %x0, i8 %x1, <4 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_pror_q_256: ; CHECK-LABEL: test_int_x86_avx512_mask_pror_q_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vprorq $3, %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vprorq $3, %ymm0, %ymm1 {%k1}
; CHECK-NEXT: vprorq $3, %ymm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vprorq $3, %ymm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vprorq $3, %ymm0, %ymm0 ; CHECK-NEXT: vprorq $3, %ymm0, %ymm0
; CHECK-NEXT: vpaddq %ymm2, %ymm1, %ymm1 ; CHECK-NEXT: vpaddq %ymm2, %ymm1, %ymm1
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.pror.q.256(<4 x i64> %x0, i8 3, <4 x i64> %x2, i8 %x3) %res = call <4 x i64> @llvm.x86.avx512.mask.pror.q.256(<4 x i64> %x0, i8 3, <4 x i64> %x2, i8 %x3)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.pror.q.256(<4 x i64> %x0, i8 3, <4 x i64> zeroinitializer, i8 %x3) %res1 = call <4 x i64> @llvm.x86.avx512.mask.pror.q.256(<4 x i64> %x0, i8 3, <4 x i64> zeroinitializer, i8 %x3)
%res2 = call <4 x i64> @llvm.x86.avx512.mask.pror.q.256(<4 x i64> %x0, i8 3, <4 x i64> %x2, i8 -1) %res2 = call <4 x i64> @llvm.x86.avx512.mask.pror.q.256(<4 x i64> %x0, i8 3, <4 x i64> %x2, i8 -1)
%res3 = add <4 x i64> %res, %res1 %res3 = add <4 x i64> %res, %res1
%res4 = add <4 x i64> %res3, %res2 %res4 = add <4 x i64> %res3, %res2
ret <4 x i64> %res4 ret <4 x i64> %res4
} }
declare <4 x i32> @llvm.x86.avx512.mask.pmovzxb.d.128(<16 x i8>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.pmovzxb.d.128(<16 x i8>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_pmovzxb_d_128(<16 x i8> %x0, <4 x i32> %x1, i8 %x2) { define <4 x i32>@test_int_x86_avx512_mask_pmovzxb_d_128(<16 x i8> %x0, <4 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxb_d_128: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxb_d_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovzxbd %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpmovzxbd %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpmovzxbd %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpmovzxbd %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpmovzxbd %xmm0, %xmm0 ; CHECK-NEXT: vpmovzxbd %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.pmovzxb.d.128(<16 x i8> %x0, <4 x i32> %x1, i8 %x2) %res = call <4 x i32> @llvm.x86.avx512.mask.pmovzxb.d.128(<16 x i8> %x0, <4 x i32> %x1, i8 %x2)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.pmovzxb.d.128(<16 x i8> %x0, <4 x i32> zeroinitializer, i8 %x2) %res1 = call <4 x i32> @llvm.x86.avx512.mask.pmovzxb.d.128(<16 x i8> %x0, <4 x i32> zeroinitializer, i8 %x2)
%res2 = call <4 x i32> @llvm.x86.avx512.mask.pmovzxb.d.128(<16 x i8> %x0, <4 x i32> %x1, i8 -1) %res2 = call <4 x i32> @llvm.x86.avx512.mask.pmovzxb.d.128(<16 x i8> %x0, <4 x i32> %x1, i8 -1)
%res3 = add <4 x i32> %res, %res1 %res3 = add <4 x i32> %res, %res1
%res4 = add <4 x i32> %res3, %res2 %res4 = add <4 x i32> %res3, %res2
ret <4 x i32> %res4 ret <4 x i32> %res4
} }
declare <8 x i32> @llvm.x86.avx512.mask.pmovzxb.d.256(<16 x i8>, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.pmovzxb.d.256(<16 x i8>, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_pmovzxb_d_256(<16 x i8> %x0, <8 x i32> %x1, i8 %x2) { define <8 x i32>@test_int_x86_avx512_mask_pmovzxb_d_256(<16 x i8> %x0, <8 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxb_d_256: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxb_d_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovzxbd %xmm0, %ymm1 {%k1} ; CHECK-NEXT: vpmovzxbd %xmm0, %ymm1 {%k1}
; CHECK-NEXT: vpmovzxbd %xmm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpmovzxbd %xmm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vpmovzxbd %xmm0, %ymm0 ; CHECK-NEXT: vpmovzxbd %xmm0, %ymm0
; CHECK-NEXT: vpaddd %ymm2, %ymm1, %ymm1 ; CHECK-NEXT: vpaddd %ymm2, %ymm1, %ymm1
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.pmovzxb.d.256(<16 x i8> %x0, <8 x i32> %x1, i8 %x2) %res = call <8 x i32> @llvm.x86.avx512.mask.pmovzxb.d.256(<16 x i8> %x0, <8 x i32> %x1, i8 %x2)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.pmovzxb.d.256(<16 x i8> %x0, <8 x i32> zeroinitializer, i8 %x2) %res1 = call <8 x i32> @llvm.x86.avx512.mask.pmovzxb.d.256(<16 x i8> %x0, <8 x i32> zeroinitializer, i8 %x2)
%res2 = call <8 x i32> @llvm.x86.avx512.mask.pmovzxb.d.256(<16 x i8> %x0, <8 x i32> %x1, i8 -1) %res2 = call <8 x i32> @llvm.x86.avx512.mask.pmovzxb.d.256(<16 x i8> %x0, <8 x i32> %x1, i8 -1)
%res3 = add <8 x i32> %res, %res1 %res3 = add <8 x i32> %res, %res1
%res4 = add <8 x i32> %res3, %res2 %res4 = add <8 x i32> %res3, %res2
ret <8 x i32> %res4 ret <8 x i32> %res4
} }
declare <2 x i64> @llvm.x86.avx512.mask.pmovzxb.q.128(<16 x i8>, <2 x i64>, i8) declare <2 x i64> @llvm.x86.avx512.mask.pmovzxb.q.128(<16 x i8>, <2 x i64>, i8)
define <2 x i64>@test_int_x86_avx512_mask_pmovzxb_q_128(<16 x i8> %x0, <2 x i64> %x1, i8 %x2) { define <2 x i64>@test_int_x86_avx512_mask_pmovzxb_q_128(<16 x i8> %x0, <2 x i64> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxb_q_128: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxb_q_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovzxbq %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpmovzxbq %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpmovzxbq %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpmovzxbq %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpmovzxbq %xmm0, %xmm0 ; CHECK-NEXT: vpmovzxbq %xmm0, %xmm0
; CHECK-NEXT: vpaddq %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpaddq %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.mask.pmovzxb.q.128(<16 x i8> %x0, <2 x i64> %x1, i8 %x2) %res = call <2 x i64> @llvm.x86.avx512.mask.pmovzxb.q.128(<16 x i8> %x0, <2 x i64> %x1, i8 %x2)
%res1 = call <2 x i64> @llvm.x86.avx512.mask.pmovzxb.q.128(<16 x i8> %x0, <2 x i64> zeroinitializer, i8 %x2) %res1 = call <2 x i64> @llvm.x86.avx512.mask.pmovzxb.q.128(<16 x i8> %x0, <2 x i64> zeroinitializer, i8 %x2)
%res2 = call <2 x i64> @llvm.x86.avx512.mask.pmovzxb.q.128(<16 x i8> %x0, <2 x i64> %x1, i8 -1) %res2 = call <2 x i64> @llvm.x86.avx512.mask.pmovzxb.q.128(<16 x i8> %x0, <2 x i64> %x1, i8 -1)
%res3 = add <2 x i64> %res, %res1 %res3 = add <2 x i64> %res, %res1
%res4 = add <2 x i64> %res3, %res2 %res4 = add <2 x i64> %res3, %res2
ret <2 x i64> %res4 ret <2 x i64> %res4
} }
declare <4 x i64> @llvm.x86.avx512.mask.pmovzxb.q.256(<16 x i8>, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.pmovzxb.q.256(<16 x i8>, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_mask_pmovzxb_q_256(<16 x i8> %x0, <4 x i64> %x1, i8 %x2) { define <4 x i64>@test_int_x86_avx512_mask_pmovzxb_q_256(<16 x i8> %x0, <4 x i64> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxb_q_256: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxb_q_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovzxbq %xmm0, %ymm1 {%k1} ; CHECK-NEXT: vpmovzxbq %xmm0, %ymm1 {%k1}
; CHECK-NEXT: vpmovzxbq %xmm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpmovzxbq %xmm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vpmovzxbq %xmm0, %ymm0 ; CHECK-NEXT: vpmovzxbq %xmm0, %ymm0
; CHECK-NEXT: vpaddq %ymm2, %ymm1, %ymm1 ; CHECK-NEXT: vpaddq %ymm2, %ymm1, %ymm1
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.pmovzxb.q.256(<16 x i8> %x0, <4 x i64> %x1, i8 %x2) %res = call <4 x i64> @llvm.x86.avx512.mask.pmovzxb.q.256(<16 x i8> %x0, <4 x i64> %x1, i8 %x2)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.pmovzxb.q.256(<16 x i8> %x0, <4 x i64> zeroinitializer, i8 %x2) %res1 = call <4 x i64> @llvm.x86.avx512.mask.pmovzxb.q.256(<16 x i8> %x0, <4 x i64> zeroinitializer, i8 %x2)
%res2 = call <4 x i64> @llvm.x86.avx512.mask.pmovzxb.q.256(<16 x i8> %x0, <4 x i64> %x1, i8 -1) %res2 = call <4 x i64> @llvm.x86.avx512.mask.pmovzxb.q.256(<16 x i8> %x0, <4 x i64> %x1, i8 -1)
%res3 = add <4 x i64> %res, %res1 %res3 = add <4 x i64> %res, %res1
%res4 = add <4 x i64> %res3, %res2 %res4 = add <4 x i64> %res3, %res2
ret <4 x i64> %res4 ret <4 x i64> %res4
} }
declare <2 x i64> @llvm.x86.avx512.mask.pmovzxd.q.128(<4 x i32>, <2 x i64>, i8) declare <2 x i64> @llvm.x86.avx512.mask.pmovzxd.q.128(<4 x i32>, <2 x i64>, i8)
define <2 x i64>@test_int_x86_avx512_mask_pmovzxd_q_128(<4 x i32> %x0, <2 x i64> %x1, i8 %x2) { define <2 x i64>@test_int_x86_avx512_mask_pmovzxd_q_128(<4 x i32> %x0, <2 x i64> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxd_q_128: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxd_q_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovzxdq %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpmovzxdq %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpmovzxdq %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpmovzxdq %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpmovzxdq %xmm0, %xmm0 ; CHECK-NEXT: vpmovzxdq %xmm0, %xmm0
; CHECK-NEXT: vpaddq %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpaddq %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.mask.pmovzxd.q.128(<4 x i32> %x0, <2 x i64> %x1, i8 %x2) %res = call <2 x i64> @llvm.x86.avx512.mask.pmovzxd.q.128(<4 x i32> %x0, <2 x i64> %x1, i8 %x2)
%res1 = call <2 x i64> @llvm.x86.avx512.mask.pmovzxd.q.128(<4 x i32> %x0, <2 x i64> zeroinitializer, i8 %x2) %res1 = call <2 x i64> @llvm.x86.avx512.mask.pmovzxd.q.128(<4 x i32> %x0, <2 x i64> zeroinitializer, i8 %x2)
%res2 = call <2 x i64> @llvm.x86.avx512.mask.pmovzxd.q.128(<4 x i32> %x0, <2 x i64> %x1, i8 -1) %res2 = call <2 x i64> @llvm.x86.avx512.mask.pmovzxd.q.128(<4 x i32> %x0, <2 x i64> %x1, i8 -1)
%res3 = add <2 x i64> %res, %res1 %res3 = add <2 x i64> %res, %res1
%res4 = add <2 x i64> %res3, %res2 %res4 = add <2 x i64> %res3, %res2
ret <2 x i64> %res4 ret <2 x i64> %res4
} }
declare <4 x i64> @llvm.x86.avx512.mask.pmovzxd.q.256(<4 x i32>, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.pmovzxd.q.256(<4 x i32>, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_mask_pmovzxd_q_256(<4 x i32> %x0, <4 x i64> %x1, i8 %x2) { define <4 x i64>@test_int_x86_avx512_mask_pmovzxd_q_256(<4 x i32> %x0, <4 x i64> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxd_q_256: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxd_q_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovzxdq %xmm0, %ymm1 {%k1} ; CHECK-NEXT: vpmovzxdq %xmm0, %ymm1 {%k1}
; CHECK-NEXT: vpmovzxdq %xmm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpmovzxdq %xmm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vpmovzxdq %xmm0, %ymm0 ; CHECK-NEXT: vpmovzxdq %xmm0, %ymm0
; CHECK-NEXT: vpaddq %ymm2, %ymm1, %ymm1 ; CHECK-NEXT: vpaddq %ymm2, %ymm1, %ymm1
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.pmovzxd.q.256(<4 x i32> %x0, <4 x i64> %x1, i8 %x2) %res = call <4 x i64> @llvm.x86.avx512.mask.pmovzxd.q.256(<4 x i32> %x0, <4 x i64> %x1, i8 %x2)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.pmovzxd.q.256(<4 x i32> %x0, <4 x i64> zeroinitializer, i8 %x2) %res1 = call <4 x i64> @llvm.x86.avx512.mask.pmovzxd.q.256(<4 x i32> %x0, <4 x i64> zeroinitializer, i8 %x2)
%res2 = call <4 x i64> @llvm.x86.avx512.mask.pmovzxd.q.256(<4 x i32> %x0, <4 x i64> %x1, i8 -1) %res2 = call <4 x i64> @llvm.x86.avx512.mask.pmovzxd.q.256(<4 x i32> %x0, <4 x i64> %x1, i8 -1)
%res3 = add <4 x i64> %res, %res1 %res3 = add <4 x i64> %res, %res1
%res4 = add <4 x i64> %res3, %res2 %res4 = add <4 x i64> %res3, %res2
ret <4 x i64> %res4 ret <4 x i64> %res4
} }
declare <4 x i32> @llvm.x86.avx512.mask.pmovzxw.d.128(<8 x i16>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.pmovzxw.d.128(<8 x i16>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_pmovzxw_d_128(<8 x i16> %x0, <4 x i32> %x1, i8 %x2) { define <4 x i32>@test_int_x86_avx512_mask_pmovzxw_d_128(<8 x i16> %x0, <4 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxw_d_128: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxw_d_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovzxwd %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpmovzxwd %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpmovzxwd %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpmovzxwd %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpmovzxwd %xmm0, %xmm0 ; CHECK-NEXT: vpmovzxwd %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.pmovzxw.d.128(<8 x i16> %x0, <4 x i32> %x1, i8 %x2) %res = call <4 x i32> @llvm.x86.avx512.mask.pmovzxw.d.128(<8 x i16> %x0, <4 x i32> %x1, i8 %x2)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.pmovzxw.d.128(<8 x i16> %x0, <4 x i32> zeroinitializer, i8 %x2) %res1 = call <4 x i32> @llvm.x86.avx512.mask.pmovzxw.d.128(<8 x i16> %x0, <4 x i32> zeroinitializer, i8 %x2)
%res2 = call <4 x i32> @llvm.x86.avx512.mask.pmovzxw.d.128(<8 x i16> %x0, <4 x i32> %x1, i8 -1) %res2 = call <4 x i32> @llvm.x86.avx512.mask.pmovzxw.d.128(<8 x i16> %x0, <4 x i32> %x1, i8 -1)
%res3 = add <4 x i32> %res, %res1 %res3 = add <4 x i32> %res, %res1
%res4 = add <4 x i32> %res3, %res2 %res4 = add <4 x i32> %res3, %res2
ret <4 x i32> %res4 ret <4 x i32> %res4
} }
declare <8 x i32> @llvm.x86.avx512.mask.pmovzxw.d.256(<8 x i16>, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.pmovzxw.d.256(<8 x i16>, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_pmovzxw_d_256(<8 x i16> %x0, <8 x i32> %x1, i8 %x2) { define <8 x i32>@test_int_x86_avx512_mask_pmovzxw_d_256(<8 x i16> %x0, <8 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxw_d_256: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxw_d_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovzxwd %xmm0, %ymm1 {%k1} ; CHECK-NEXT: vpmovzxwd %xmm0, %ymm1 {%k1}
; CHECK-NEXT: vpmovzxwd %xmm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpmovzxwd %xmm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vpmovzxwd %xmm0, %ymm0 ; CHECK-NEXT: vpmovzxwd %xmm0, %ymm0
; CHECK-NEXT: vpaddd %ymm2, %ymm1, %ymm1 ; CHECK-NEXT: vpaddd %ymm2, %ymm1, %ymm1
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.pmovzxw.d.256(<8 x i16> %x0, <8 x i32> %x1, i8 %x2) %res = call <8 x i32> @llvm.x86.avx512.mask.pmovzxw.d.256(<8 x i16> %x0, <8 x i32> %x1, i8 %x2)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.pmovzxw.d.256(<8 x i16> %x0, <8 x i32> zeroinitializer, i8 %x2) %res1 = call <8 x i32> @llvm.x86.avx512.mask.pmovzxw.d.256(<8 x i16> %x0, <8 x i32> zeroinitializer, i8 %x2)
%res2 = call <8 x i32> @llvm.x86.avx512.mask.pmovzxw.d.256(<8 x i16> %x0, <8 x i32> %x1, i8 -1) %res2 = call <8 x i32> @llvm.x86.avx512.mask.pmovzxw.d.256(<8 x i16> %x0, <8 x i32> %x1, i8 -1)
%res3 = add <8 x i32> %res, %res1 %res3 = add <8 x i32> %res, %res1
%res4 = add <8 x i32> %res3, %res2 %res4 = add <8 x i32> %res3, %res2
ret <8 x i32> %res4 ret <8 x i32> %res4
} }
declare <2 x i64> @llvm.x86.avx512.mask.pmovzxw.q.128(<8 x i16>, <2 x i64>, i8) declare <2 x i64> @llvm.x86.avx512.mask.pmovzxw.q.128(<8 x i16>, <2 x i64>, i8)
define <2 x i64>@test_int_x86_avx512_mask_pmovzxw_q_128(<8 x i16> %x0, <2 x i64> %x1, i8 %x2) { define <2 x i64>@test_int_x86_avx512_mask_pmovzxw_q_128(<8 x i16> %x0, <2 x i64> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxw_q_128: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxw_q_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovzxwq %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpmovzxwq %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpmovzxwq %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpmovzxwq %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpmovzxwq %xmm0, %xmm0 ; CHECK-NEXT: vpmovzxwq %xmm0, %xmm0
; CHECK-NEXT: vpaddq %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpaddq %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.mask.pmovzxw.q.128(<8 x i16> %x0, <2 x i64> %x1, i8 %x2) %res = call <2 x i64> @llvm.x86.avx512.mask.pmovzxw.q.128(<8 x i16> %x0, <2 x i64> %x1, i8 %x2)
%res1 = call <2 x i64> @llvm.x86.avx512.mask.pmovzxw.q.128(<8 x i16> %x0, <2 x i64> zeroinitializer, i8 %x2) %res1 = call <2 x i64> @llvm.x86.avx512.mask.pmovzxw.q.128(<8 x i16> %x0, <2 x i64> zeroinitializer, i8 %x2)
%res2 = call <2 x i64> @llvm.x86.avx512.mask.pmovzxw.q.128(<8 x i16> %x0, <2 x i64> %x1, i8 -1) %res2 = call <2 x i64> @llvm.x86.avx512.mask.pmovzxw.q.128(<8 x i16> %x0, <2 x i64> %x1, i8 -1)
%res3 = add <2 x i64> %res, %res1 %res3 = add <2 x i64> %res, %res1
%res4 = add <2 x i64> %res3, %res2 %res4 = add <2 x i64> %res3, %res2
ret <2 x i64> %res4 ret <2 x i64> %res4
} }
declare <4 x i64> @llvm.x86.avx512.mask.pmovzxw.q.256(<8 x i16>, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.pmovzxw.q.256(<8 x i16>, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_mask_pmovzxw_q_256(<8 x i16> %x0, <4 x i64> %x1, i8 %x2) { define <4 x i64>@test_int_x86_avx512_mask_pmovzxw_q_256(<8 x i16> %x0, <4 x i64> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxw_q_256: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovzxw_q_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovzxwq %xmm0, %ymm1 {%k1} ; CHECK-NEXT: vpmovzxwq %xmm0, %ymm1 {%k1}
; CHECK-NEXT: vpmovzxwq %xmm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpmovzxwq %xmm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vpmovzxwq %xmm0, %ymm0 ; CHECK-NEXT: vpmovzxwq %xmm0, %ymm0
; CHECK-NEXT: vpaddq %ymm2, %ymm1, %ymm1 ; CHECK-NEXT: vpaddq %ymm2, %ymm1, %ymm1
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.pmovzxw.q.256(<8 x i16> %x0, <4 x i64> %x1, i8 %x2) %res = call <4 x i64> @llvm.x86.avx512.mask.pmovzxw.q.256(<8 x i16> %x0, <4 x i64> %x1, i8 %x2)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.pmovzxw.q.256(<8 x i16> %x0, <4 x i64> zeroinitializer, i8 %x2) %res1 = call <4 x i64> @llvm.x86.avx512.mask.pmovzxw.q.256(<8 x i16> %x0, <4 x i64> zeroinitializer, i8 %x2)
%res2 = call <4 x i64> @llvm.x86.avx512.mask.pmovzxw.q.256(<8 x i16> %x0, <4 x i64> %x1, i8 -1) %res2 = call <4 x i64> @llvm.x86.avx512.mask.pmovzxw.q.256(<8 x i16> %x0, <4 x i64> %x1, i8 -1)
%res3 = add <4 x i64> %res, %res1 %res3 = add <4 x i64> %res, %res1
%res4 = add <4 x i64> %res3, %res2 %res4 = add <4 x i64> %res3, %res2
ret <4 x i64> %res4 ret <4 x i64> %res4
} }
declare <4 x i32> @llvm.x86.avx512.mask.pmovsxb.d.128(<16 x i8>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.pmovsxb.d.128(<16 x i8>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_pmovsxb_d_128(<16 x i8> %x0, <4 x i32> %x1, i8 %x2) { define <4 x i32>@test_int_x86_avx512_mask_pmovsxb_d_128(<16 x i8> %x0, <4 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxb_d_128: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxb_d_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovsxbd %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpmovsxbd %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpmovsxbd %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpmovsxbd %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpmovsxbd %xmm0, %xmm0 ; CHECK-NEXT: vpmovsxbd %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.pmovsxb.d.128(<16 x i8> %x0, <4 x i32> %x1, i8 %x2) %res = call <4 x i32> @llvm.x86.avx512.mask.pmovsxb.d.128(<16 x i8> %x0, <4 x i32> %x1, i8 %x2)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.pmovsxb.d.128(<16 x i8> %x0, <4 x i32> zeroinitializer, i8 %x2) %res1 = call <4 x i32> @llvm.x86.avx512.mask.pmovsxb.d.128(<16 x i8> %x0, <4 x i32> zeroinitializer, i8 %x2)
%res2 = call <4 x i32> @llvm.x86.avx512.mask.pmovsxb.d.128(<16 x i8> %x0, <4 x i32> %x1, i8 -1) %res2 = call <4 x i32> @llvm.x86.avx512.mask.pmovsxb.d.128(<16 x i8> %x0, <4 x i32> %x1, i8 -1)
%res3 = add <4 x i32> %res, %res1 %res3 = add <4 x i32> %res, %res1
%res4 = add <4 x i32> %res3, %res2 %res4 = add <4 x i32> %res3, %res2
ret <4 x i32> %res4 ret <4 x i32> %res4
} }
declare <8 x i32> @llvm.x86.avx512.mask.pmovsxb.d.256(<16 x i8>, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.pmovsxb.d.256(<16 x i8>, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_pmovsxb_d_256(<16 x i8> %x0, <8 x i32> %x1, i8 %x2) { define <8 x i32>@test_int_x86_avx512_mask_pmovsxb_d_256(<16 x i8> %x0, <8 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxb_d_256: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxb_d_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovsxbd %xmm0, %ymm1 {%k1} ; CHECK-NEXT: vpmovsxbd %xmm0, %ymm1 {%k1}
; CHECK-NEXT: vpmovsxbd %xmm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpmovsxbd %xmm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vpmovsxbd %xmm0, %ymm0 ; CHECK-NEXT: vpmovsxbd %xmm0, %ymm0
; CHECK-NEXT: vpaddd %ymm2, %ymm1, %ymm1 ; CHECK-NEXT: vpaddd %ymm2, %ymm1, %ymm1
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.pmovsxb.d.256(<16 x i8> %x0, <8 x i32> %x1, i8 %x2) %res = call <8 x i32> @llvm.x86.avx512.mask.pmovsxb.d.256(<16 x i8> %x0, <8 x i32> %x1, i8 %x2)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.pmovsxb.d.256(<16 x i8> %x0, <8 x i32> zeroinitializer, i8 %x2) %res1 = call <8 x i32> @llvm.x86.avx512.mask.pmovsxb.d.256(<16 x i8> %x0, <8 x i32> zeroinitializer, i8 %x2)
%res2 = call <8 x i32> @llvm.x86.avx512.mask.pmovsxb.d.256(<16 x i8> %x0, <8 x i32> %x1, i8 -1) %res2 = call <8 x i32> @llvm.x86.avx512.mask.pmovsxb.d.256(<16 x i8> %x0, <8 x i32> %x1, i8 -1)
%res3 = add <8 x i32> %res, %res1 %res3 = add <8 x i32> %res, %res1
%res4 = add <8 x i32> %res3, %res2 %res4 = add <8 x i32> %res3, %res2
ret <8 x i32> %res4 ret <8 x i32> %res4
} }
declare <2 x i64> @llvm.x86.avx512.mask.pmovsxb.q.128(<16 x i8>, <2 x i64>, i8) declare <2 x i64> @llvm.x86.avx512.mask.pmovsxb.q.128(<16 x i8>, <2 x i64>, i8)
define <2 x i64>@test_int_x86_avx512_mask_pmovsxb_q_128(<16 x i8> %x0, <2 x i64> %x1, i8 %x2) { define <2 x i64>@test_int_x86_avx512_mask_pmovsxb_q_128(<16 x i8> %x0, <2 x i64> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxb_q_128: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxb_q_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovsxbq %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpmovsxbq %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpmovsxbq %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpmovsxbq %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpmovsxbq %xmm0, %xmm0 ; CHECK-NEXT: vpmovsxbq %xmm0, %xmm0
; CHECK-NEXT: vpaddq %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpaddq %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.mask.pmovsxb.q.128(<16 x i8> %x0, <2 x i64> %x1, i8 %x2) %res = call <2 x i64> @llvm.x86.avx512.mask.pmovsxb.q.128(<16 x i8> %x0, <2 x i64> %x1, i8 %x2)
%res1 = call <2 x i64> @llvm.x86.avx512.mask.pmovsxb.q.128(<16 x i8> %x0, <2 x i64> zeroinitializer, i8 %x2) %res1 = call <2 x i64> @llvm.x86.avx512.mask.pmovsxb.q.128(<16 x i8> %x0, <2 x i64> zeroinitializer, i8 %x2)
%res2 = call <2 x i64> @llvm.x86.avx512.mask.pmovsxb.q.128(<16 x i8> %x0, <2 x i64> %x1, i8 -1) %res2 = call <2 x i64> @llvm.x86.avx512.mask.pmovsxb.q.128(<16 x i8> %x0, <2 x i64> %x1, i8 -1)
%res3 = add <2 x i64> %res, %res1 %res3 = add <2 x i64> %res, %res1
%res4 = add <2 x i64> %res3, %res2 %res4 = add <2 x i64> %res3, %res2
ret <2 x i64> %res4 ret <2 x i64> %res4
} }
declare <4 x i64> @llvm.x86.avx512.mask.pmovsxb.q.256(<16 x i8>, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.pmovsxb.q.256(<16 x i8>, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_mask_pmovsxb_q_256(<16 x i8> %x0, <4 x i64> %x1, i8 %x2) { define <4 x i64>@test_int_x86_avx512_mask_pmovsxb_q_256(<16 x i8> %x0, <4 x i64> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxb_q_256: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxb_q_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovsxbq %xmm0, %ymm1 {%k1} ; CHECK-NEXT: vpmovsxbq %xmm0, %ymm1 {%k1}
; CHECK-NEXT: vpmovsxbq %xmm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpmovsxbq %xmm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vpmovsxbq %xmm0, %ymm0 ; CHECK-NEXT: vpmovsxbq %xmm0, %ymm0
; CHECK-NEXT: vpaddq %ymm2, %ymm1, %ymm1 ; CHECK-NEXT: vpaddq %ymm2, %ymm1, %ymm1
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.pmovsxb.q.256(<16 x i8> %x0, <4 x i64> %x1, i8 %x2) %res = call <4 x i64> @llvm.x86.avx512.mask.pmovsxb.q.256(<16 x i8> %x0, <4 x i64> %x1, i8 %x2)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.pmovsxb.q.256(<16 x i8> %x0, <4 x i64> zeroinitializer, i8 %x2) %res1 = call <4 x i64> @llvm.x86.avx512.mask.pmovsxb.q.256(<16 x i8> %x0, <4 x i64> zeroinitializer, i8 %x2)
%res2 = call <4 x i64> @llvm.x86.avx512.mask.pmovsxb.q.256(<16 x i8> %x0, <4 x i64> %x1, i8 -1) %res2 = call <4 x i64> @llvm.x86.avx512.mask.pmovsxb.q.256(<16 x i8> %x0, <4 x i64> %x1, i8 -1)
%res3 = add <4 x i64> %res, %res1 %res3 = add <4 x i64> %res, %res1
%res4 = add <4 x i64> %res3, %res2 %res4 = add <4 x i64> %res3, %res2
ret <4 x i64> %res4 ret <4 x i64> %res4
} }
declare <4 x i32> @llvm.x86.avx512.mask.pmovsxw.d.128(<8 x i16>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx512.mask.pmovsxw.d.128(<8 x i16>, <4 x i32>, i8)
define <4 x i32>@test_int_x86_avx512_mask_pmovsxw_d_128(<8 x i16> %x0, <4 x i32> %x1, i8 %x2) { define <4 x i32>@test_int_x86_avx512_mask_pmovsxw_d_128(<8 x i16> %x0, <4 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxw_d_128: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxw_d_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovsxwd %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpmovsxwd %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpmovsxwd %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpmovsxwd %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpmovsxwd %xmm0, %xmm0 ; CHECK-NEXT: vpmovsxwd %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.mask.pmovsxw.d.128(<8 x i16> %x0, <4 x i32> %x1, i8 %x2) %res = call <4 x i32> @llvm.x86.avx512.mask.pmovsxw.d.128(<8 x i16> %x0, <4 x i32> %x1, i8 %x2)
%res1 = call <4 x i32> @llvm.x86.avx512.mask.pmovsxw.d.128(<8 x i16> %x0, <4 x i32> zeroinitializer, i8 %x2) %res1 = call <4 x i32> @llvm.x86.avx512.mask.pmovsxw.d.128(<8 x i16> %x0, <4 x i32> zeroinitializer, i8 %x2)
%res2 = call <4 x i32> @llvm.x86.avx512.mask.pmovsxw.d.128(<8 x i16> %x0, <4 x i32> %x1, i8 -1) %res2 = call <4 x i32> @llvm.x86.avx512.mask.pmovsxw.d.128(<8 x i16> %x0, <4 x i32> %x1, i8 -1)
%res3 = add <4 x i32> %res, %res1 %res3 = add <4 x i32> %res, %res1
%res4 = add <4 x i32> %res3, %res2 %res4 = add <4 x i32> %res3, %res2
ret <4 x i32> %res4 ret <4 x i32> %res4
} }
declare <8 x i32> @llvm.x86.avx512.mask.pmovsxw.d.256(<8 x i16>, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.pmovsxw.d.256(<8 x i16>, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_pmovsxw_d_256(<8 x i16> %x0, <8 x i32> %x1, i8 %x2) { define <8 x i32>@test_int_x86_avx512_mask_pmovsxw_d_256(<8 x i16> %x0, <8 x i32> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxw_d_256: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxw_d_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovsxwd %xmm0, %ymm1 {%k1} ; CHECK-NEXT: vpmovsxwd %xmm0, %ymm1 {%k1}
; CHECK-NEXT: vpmovsxwd %xmm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpmovsxwd %xmm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vpmovsxwd %xmm0, %ymm0 ; CHECK-NEXT: vpmovsxwd %xmm0, %ymm0
; CHECK-NEXT: vpaddd %ymm2, %ymm1, %ymm1 ; CHECK-NEXT: vpaddd %ymm2, %ymm1, %ymm1
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.pmovsxw.d.256(<8 x i16> %x0, <8 x i32> %x1, i8 %x2) %res = call <8 x i32> @llvm.x86.avx512.mask.pmovsxw.d.256(<8 x i16> %x0, <8 x i32> %x1, i8 %x2)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.pmovsxw.d.256(<8 x i16> %x0, <8 x i32> zeroinitializer, i8 %x2) %res1 = call <8 x i32> @llvm.x86.avx512.mask.pmovsxw.d.256(<8 x i16> %x0, <8 x i32> zeroinitializer, i8 %x2)
%res2 = call <8 x i32> @llvm.x86.avx512.mask.pmovsxw.d.256(<8 x i16> %x0, <8 x i32> %x1, i8 -1) %res2 = call <8 x i32> @llvm.x86.avx512.mask.pmovsxw.d.256(<8 x i16> %x0, <8 x i32> %x1, i8 -1)
%res3 = add <8 x i32> %res, %res1 %res3 = add <8 x i32> %res, %res1
%res4 = add <8 x i32> %res3, %res2 %res4 = add <8 x i32> %res3, %res2
ret <8 x i32> %res4 ret <8 x i32> %res4
} }
declare <2 x i64> @llvm.x86.avx512.mask.pmovsxw.q.128(<8 x i16>, <2 x i64>, i8) declare <2 x i64> @llvm.x86.avx512.mask.pmovsxw.q.128(<8 x i16>, <2 x i64>, i8)
define <2 x i64>@test_int_x86_avx512_mask_pmovsxw_q_128(<8 x i16> %x0, <2 x i64> %x1, i8 %x2) { define <2 x i64>@test_int_x86_avx512_mask_pmovsxw_q_128(<8 x i16> %x0, <2 x i64> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxw_q_128: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxw_q_128:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovsxwq %xmm0, %xmm1 {%k1} ; CHECK-NEXT: vpmovsxwq %xmm0, %xmm1 {%k1}
; CHECK-NEXT: vpmovsxwq %xmm0, %xmm2 {%k1} {z} ; CHECK-NEXT: vpmovsxwq %xmm0, %xmm2 {%k1} {z}
; CHECK-NEXT: vpmovsxwq %xmm0, %xmm0 ; CHECK-NEXT: vpmovsxwq %xmm0, %xmm0
; CHECK-NEXT: vpaddq %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpaddq %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.mask.pmovsxw.q.128(<8 x i16> %x0, <2 x i64> %x1, i8 %x2) %res = call <2 x i64> @llvm.x86.avx512.mask.pmovsxw.q.128(<8 x i16> %x0, <2 x i64> %x1, i8 %x2)
%res1 = call <2 x i64> @llvm.x86.avx512.mask.pmovsxw.q.128(<8 x i16> %x0, <2 x i64> zeroinitializer, i8 %x2) %res1 = call <2 x i64> @llvm.x86.avx512.mask.pmovsxw.q.128(<8 x i16> %x0, <2 x i64> zeroinitializer, i8 %x2)
%res2 = call <2 x i64> @llvm.x86.avx512.mask.pmovsxw.q.128(<8 x i16> %x0, <2 x i64> %x1, i8 -1) %res2 = call <2 x i64> @llvm.x86.avx512.mask.pmovsxw.q.128(<8 x i16> %x0, <2 x i64> %x1, i8 -1)
%res3 = add <2 x i64> %res, %res1 %res3 = add <2 x i64> %res, %res1
%res4 = add <2 x i64> %res3, %res2 %res4 = add <2 x i64> %res3, %res2
ret <2 x i64> %res4 ret <2 x i64> %res4
} }
declare <4 x i64> @llvm.x86.avx512.mask.pmovsxw.q.256(<8 x i16>, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.pmovsxw.q.256(<8 x i16>, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_mask_pmovsxw_q_256(<8 x i16> %x0, <4 x i64> %x1, i8 %x2) { define <4 x i64>@test_int_x86_avx512_mask_pmovsxw_q_256(<8 x i16> %x0, <4 x i64> %x1, i8 %x2) {
; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxw_q_256: ; CHECK-LABEL: test_int_x86_avx512_mask_pmovsxw_q_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpmovsxwq %xmm0, %ymm1 {%k1} ; CHECK-NEXT: vpmovsxwq %xmm0, %ymm1 {%k1}
; CHECK-NEXT: vpmovsxwq %xmm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpmovsxwq %xmm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vpmovsxwq %xmm0, %ymm0 ; CHECK-NEXT: vpmovsxwq %xmm0, %ymm0
; CHECK-NEXT: vpaddq %ymm2, %ymm1, %ymm1 ; CHECK-NEXT: vpaddq %ymm2, %ymm1, %ymm1
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.pmovsxw.q.256(<8 x i16> %x0, <4 x i64> %x1, i8 %x2) %res = call <4 x i64> @llvm.x86.avx512.mask.pmovsxw.q.256(<8 x i16> %x0, <4 x i64> %x1, i8 %x2)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.pmovsxw.q.256(<8 x i16> %x0, <4 x i64> zeroinitializer, i8 %x2) %res1 = call <4 x i64> @llvm.x86.avx512.mask.pmovsxw.q.256(<8 x i16> %x0, <4 x i64> zeroinitializer, i8 %x2)
%res2 = call <4 x i64> @llvm.x86.avx512.mask.pmovsxw.q.256(<8 x i16> %x0, <4 x i64> %x1, i8 -1) %res2 = call <4 x i64> @llvm.x86.avx512.mask.pmovsxw.q.256(<8 x i16> %x0, <4 x i64> %x1, i8 -1)
%res3 = add <4 x i64> %res, %res1 %res3 = add <4 x i64> %res, %res1
%res4 = add <4 x i64> %res3, %res2 %res4 = add <4 x i64> %res3, %res2
ret <4 x i64> %res4 ret <4 x i64> %res4
} }
declare <4 x double> @llvm.x86.avx512.mask.perm.df.256(<4 x double>, i8, <4 x double>, i8) declare <4 x double> @llvm.x86.avx512.mask.perm.df.256(<4 x double>, i8, <4 x double>, i8)
define <4 x double>@test_int_x86_avx512_mask_perm_df_256(<4 x double> %x0, i8 %x1, <4 x double> %x2, i8 %x3) { define <4 x double>@test_int_x86_avx512_mask_perm_df_256(<4 x double> %x0, i8 %x1, <4 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_perm_df_256: ; CHECK-LABEL: test_int_x86_avx512_mask_perm_df_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpermpd $3, %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vpermpd $3, %ymm0, %ymm1 {%k1}
; CHECK-NEXT: vpermpd $3, %ymm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpermpd $3, %ymm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vpermpd $3, %ymm0, %ymm0 ; CHECK-NEXT: vpermpd $3, %ymm0, %ymm0
; CHECK-NEXT: ## ymm0 = ymm0[3,0,0,0] ; CHECK-NEXT: ## ymm0 = ymm0[3,0,0,0]
; CHECK-NEXT: vaddpd %ymm2, %ymm1, %ymm1 ; CHECK-NEXT: vaddpd %ymm2, %ymm1, %ymm1
; CHECK-NEXT: vaddpd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vaddpd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x double> @llvm.x86.avx512.mask.perm.df.256(<4 x double> %x0, i8 3, <4 x double> %x2, i8 %x3) %res = call <4 x double> @llvm.x86.avx512.mask.perm.df.256(<4 x double> %x0, i8 3, <4 x double> %x2, i8 %x3)
%res1 = call <4 x double> @llvm.x86.avx512.mask.perm.df.256(<4 x double> %x0, i8 3, <4 x double> zeroinitializer, i8 %x3) %res1 = call <4 x double> @llvm.x86.avx512.mask.perm.df.256(<4 x double> %x0, i8 3, <4 x double> zeroinitializer, i8 %x3)
%res2 = call <4 x double> @llvm.x86.avx512.mask.perm.df.256(<4 x double> %x0, i8 3, <4 x double> %x2, i8 -1) %res2 = call <4 x double> @llvm.x86.avx512.mask.perm.df.256(<4 x double> %x0, i8 3, <4 x double> %x2, i8 -1)
%res3 = fadd <4 x double> %res, %res1 %res3 = fadd <4 x double> %res, %res1
%res4 = fadd <4 x double> %res3, %res2 %res4 = fadd <4 x double> %res3, %res2
ret <4 x double> %res4 ret <4 x double> %res4
} }
declare <4 x i64> @llvm.x86.avx512.mask.perm.di.256(<4 x i64>, i8, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.perm.di.256(<4 x i64>, i8, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_mask_perm_di_256(<4 x i64> %x0, i8 %x1, <4 x i64> %x2, i8 %x3) { define <4 x i64>@test_int_x86_avx512_mask_perm_di_256(<4 x i64> %x0, i8 %x1, <4 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_perm_di_256: ; CHECK-LABEL: test_int_x86_avx512_mask_perm_di_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpermq $3, %ymm0, %ymm1 {%k1} ; CHECK-NEXT: vpermq $3, %ymm0, %ymm1 {%k1}
; CHECK-NEXT: vpermq $3, %ymm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpermq $3, %ymm0, %ymm2 {%k1} {z}
; CHECK-NEXT: vpermq $3, %ymm0, %ymm0 ; CHECK-NEXT: vpermq $3, %ymm0, %ymm0
; CHECK-NEXT: ## ymm0 = ymm0[3,0,0,0] ; CHECK-NEXT: ## ymm0 = ymm0[3,0,0,0]
; CHECK-NEXT: vpaddq %ymm2, %ymm1, %ymm1 ; CHECK-NEXT: vpaddq %ymm2, %ymm1, %ymm1
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.perm.di.256(<4 x i64> %x0, i8 3, <4 x i64> %x2, i8 %x3) %res = call <4 x i64> @llvm.x86.avx512.mask.perm.di.256(<4 x i64> %x0, i8 3, <4 x i64> %x2, i8 %x3)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.perm.di.256(<4 x i64> %x0, i8 3, <4 x i64> zeroinitializer, i8 %x3) %res1 = call <4 x i64> @llvm.x86.avx512.mask.perm.di.256(<4 x i64> %x0, i8 3, <4 x i64> zeroinitializer, i8 %x3)
%res2 = call <4 x i64> @llvm.x86.avx512.mask.perm.di.256(<4 x i64> %x0, i8 3, <4 x i64> %x2, i8 -1) %res2 = call <4 x i64> @llvm.x86.avx512.mask.perm.di.256(<4 x i64> %x0, i8 3, <4 x i64> %x2, i8 -1)
%res3 = add <4 x i64> %res, %res1 %res3 = add <4 x i64> %res, %res1
%res4 = add <4 x i64> %res3, %res2 %res4 = add <4 x i64> %res3, %res2
ret <4 x i64> %res4 ret <4 x i64> %res4
} }
declare <4 x double> @llvm.x86.avx512.mask.permvar.df.256(<4 x double>, <4 x i64>, <4 x double>, i8) declare <4 x double> @llvm.x86.avx512.mask.permvar.df.256(<4 x double>, <4 x i64>, <4 x double>, i8)
define <4 x double>@test_int_x86_avx512_mask_permvar_df_256(<4 x double> %x0, <4 x i64> %x1, <4 x double> %x2, i8 %x3) { define <4 x double>@test_int_x86_avx512_mask_permvar_df_256(<4 x double> %x0, <4 x i64> %x1, <4 x double> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_permvar_df_256: ; CHECK-LABEL: test_int_x86_avx512_mask_permvar_df_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpermpd %ymm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vpermpd %ymm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: vpermpd %ymm1, %ymm0, %ymm3 {%k1} {z} ; CHECK-NEXT: vpermpd %ymm1, %ymm0, %ymm3 {%k1} {z}
; CHECK-NEXT: vpermpd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vpermpd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vaddpd %ymm3, %ymm2, %ymm1 ; CHECK-NEXT: vaddpd %ymm3, %ymm2, %ymm1
; CHECK-NEXT: vaddpd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vaddpd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x double> @llvm.x86.avx512.mask.permvar.df.256(<4 x double> %x0, <4 x i64> %x1, <4 x double> %x2, i8 %x3) %res = call <4 x double> @llvm.x86.avx512.mask.permvar.df.256(<4 x double> %x0, <4 x i64> %x1, <4 x double> %x2, i8 %x3)
%res1 = call <4 x double> @llvm.x86.avx512.mask.permvar.df.256(<4 x double> %x0, <4 x i64> %x1, <4 x double> zeroinitializer, i8 %x3) %res1 = call <4 x double> @llvm.x86.avx512.mask.permvar.df.256(<4 x double> %x0, <4 x i64> %x1, <4 x double> zeroinitializer, i8 %x3)
%res2 = call <4 x double> @llvm.x86.avx512.mask.permvar.df.256(<4 x double> %x0, <4 x i64> %x1, <4 x double> %x2, i8 -1) %res2 = call <4 x double> @llvm.x86.avx512.mask.permvar.df.256(<4 x double> %x0, <4 x i64> %x1, <4 x double> %x2, i8 -1)
%res3 = fadd <4 x double> %res, %res1 %res3 = fadd <4 x double> %res, %res1
%res4 = fadd <4 x double> %res3, %res2 %res4 = fadd <4 x double> %res3, %res2
ret <4 x double> %res4 ret <4 x double> %res4
} }
declare <4 x i64> @llvm.x86.avx512.mask.permvar.di.256(<4 x i64>, <4 x i64>, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.permvar.di.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_mask_permvar_di_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) { define <4 x i64>@test_int_x86_avx512_mask_permvar_di_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_permvar_di_256: ; CHECK-LABEL: test_int_x86_avx512_mask_permvar_di_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpermq %ymm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vpermq %ymm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: vpermq %ymm1, %ymm0, %ymm3 {%k1} {z} ; CHECK-NEXT: vpermq %ymm1, %ymm0, %ymm3 {%k1} {z}
; CHECK-NEXT: vpermq %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vpermq %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddq %ymm3, %ymm2, %ymm1 ; CHECK-NEXT: vpaddq %ymm3, %ymm2, %ymm1
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.mask.permvar.di.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) %res = call <4 x i64> @llvm.x86.avx512.mask.permvar.di.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3)
%res1 = call <4 x i64> @llvm.x86.avx512.mask.permvar.di.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3) %res1 = call <4 x i64> @llvm.x86.avx512.mask.permvar.di.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)
%res2 = call <4 x i64> @llvm.x86.avx512.mask.permvar.di.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 -1) %res2 = call <4 x i64> @llvm.x86.avx512.mask.permvar.di.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 -1)
%res3 = add <4 x i64> %res, %res1 %res3 = add <4 x i64> %res, %res1
%res4 = add <4 x i64> %res3, %res2 %res4 = add <4 x i64> %res3, %res2
ret <4 x i64> %res4 ret <4 x i64> %res4
} }
declare <8 x float> @llvm.x86.avx512.mask.permvar.sf.256(<8 x float>, <8 x i32>, <8 x float>, i8) declare <8 x float> @llvm.x86.avx512.mask.permvar.sf.256(<8 x float>, <8 x i32>, <8 x float>, i8)
define <8 x float>@test_int_x86_avx512_mask_permvar_sf_256(<8 x float> %x0, <8 x i32> %x1, <8 x float> %x2, i8 %x3) { define <8 x float>@test_int_x86_avx512_mask_permvar_sf_256(<8 x float> %x0, <8 x i32> %x1, <8 x float> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_permvar_sf_256: ; CHECK-LABEL: test_int_x86_avx512_mask_permvar_sf_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpermps %ymm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vpermps %ymm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: vpermps %ymm1, %ymm0, %ymm3 {%k1} {z} ; CHECK-NEXT: vpermps %ymm1, %ymm0, %ymm3 {%k1} {z}
; CHECK-NEXT: vpermps %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vpermps %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vaddps %ymm3, %ymm2, %ymm1 ; CHECK-NEXT: vaddps %ymm3, %ymm2, %ymm1
; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx512.mask.permvar.sf.256(<8 x float> %x0, <8 x i32> %x1, <8 x float> %x2, i8 %x3) %res = call <8 x float> @llvm.x86.avx512.mask.permvar.sf.256(<8 x float> %x0, <8 x i32> %x1, <8 x float> %x2, i8 %x3)
%res1 = call <8 x float> @llvm.x86.avx512.mask.permvar.sf.256(<8 x float> %x0, <8 x i32> %x1, <8 x float> zeroinitializer, i8 %x3) %res1 = call <8 x float> @llvm.x86.avx512.mask.permvar.sf.256(<8 x float> %x0, <8 x i32> %x1, <8 x float> zeroinitializer, i8 %x3)
%res2 = call <8 x float> @llvm.x86.avx512.mask.permvar.sf.256(<8 x float> %x0, <8 x i32> %x1, <8 x float> %x2, i8 -1) %res2 = call <8 x float> @llvm.x86.avx512.mask.permvar.sf.256(<8 x float> %x0, <8 x i32> %x1, <8 x float> %x2, i8 -1)
%res3 = fadd <8 x float> %res, %res1 %res3 = fadd <8 x float> %res, %res1
%res4 = fadd <8 x float> %res3, %res2 %res4 = fadd <8 x float> %res3, %res2
ret <8 x float> %res4 ret <8 x float> %res4
} }
declare <8 x i32> @llvm.x86.avx512.mask.permvar.si.256(<8 x i32>, <8 x i32>, <8 x i32>, i8) declare <8 x i32> @llvm.x86.avx512.mask.permvar.si.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)
define <8 x i32>@test_int_x86_avx512_mask_permvar_si_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) { define <8 x i32>@test_int_x86_avx512_mask_permvar_si_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) {
; CHECK-LABEL: test_int_x86_avx512_mask_permvar_si_256: ; CHECK-LABEL: test_int_x86_avx512_mask_permvar_si_256:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpermd %ymm1, %ymm0, %ymm2 {%k1} ; CHECK-NEXT: vpermd %ymm1, %ymm0, %ymm2 {%k1}
; CHECK-NEXT: vpermd %ymm1, %ymm0, %ymm3 {%k1} {z} ; CHECK-NEXT: vpermd %ymm1, %ymm0, %ymm3 {%k1} {z}
; CHECK-NEXT: vpermd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vpermd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vpaddd %ymm3, %ymm2, %ymm1 ; CHECK-NEXT: vpaddd %ymm3, %ymm2, %ymm1
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx512.mask.permvar.si.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) %res = call <8 x i32> @llvm.x86.avx512.mask.permvar.si.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3)
%res1 = call <8 x i32> @llvm.x86.avx512.mask.permvar.si.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> zeroinitializer, i8 %x3) %res1 = call <8 x i32> @llvm.x86.avx512.mask.permvar.si.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> zeroinitializer, i8 %x3)
%res2 = call <8 x i32> @llvm.x86.avx512.mask.permvar.si.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 -1) %res2 = call <8 x i32> @llvm.x86.avx512.mask.permvar.si.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 -1)
%res3 = add <8 x i32> %res, %res1 %res3 = add <8 x i32> %res, %res1
%res4 = add <8 x i32> %res3, %res2 %res4 = add <8 x i32> %res3, %res2
ret <8 x i32> %res4 ret <8 x i32> %res4
} }

llvm/trunk/test/CodeGen/X86/masked_gather_scatter.ll

Show First 20 Lines • Show All 273 Lines • ▼ Show 20 Lines; SKX-NEXT: retq
call void @llvm.masked.scatter.v8i32(<8 x i32> %a1, <8 x i32*> %ptr, i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>) call void @llvm.masked.scatter.v8i32(<8 x i32> %a1, <8 x i32*> %ptr, i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)
ret <8 x i32>%a ret <8 x i32>%a
} }
define <8 x i32> @test7(i32* %base, <8 x i32> %ind, i8 %mask) { define <8 x i32> @test7(i32* %base, <8 x i32> %ind, i8 %mask) {
; ;
; KNL_64-LABEL: test7: ; KNL_64-LABEL: test7:
; KNL_64: # BB#0: ; KNL_64: # BB#0:
; KNL_64-NEXT: movzbl %sil, %eax ; KNL_64-NEXT: kmovw %esi, %k1
; KNL_64-NEXT: kmovw %eax, %k1
; KNL_64-NEXT: vpmovsxdq %ymm0, %zmm0 ; KNL_64-NEXT: vpmovsxdq %ymm0, %zmm0
; KNL_64-NEXT: kmovw %k1, %k2 ; KNL_64-NEXT: kmovw %k1, %k2
; KNL_64-NEXT: vpgatherqd (%rdi,%zmm0,4), %ymm1 {%k2} ; KNL_64-NEXT: vpgatherqd (%rdi,%zmm0,4), %ymm1 {%k2}
; KNL_64-NEXT: vmovaps %zmm1, %zmm2 ; KNL_64-NEXT: vmovaps %zmm1, %zmm2
; KNL_64-NEXT: vpgatherqd (%rdi,%zmm0,4), %ymm2 {%k1} ; KNL_64-NEXT: vpgatherqd (%rdi,%zmm0,4), %ymm2 {%k1}
; KNL_64-NEXT: vpaddd %ymm2, %ymm1, %ymm0 ; KNL_64-NEXT: vpaddd %ymm2, %ymm1, %ymm0
; KNL_64-NEXT: retq ; KNL_64-NEXT: retq
; ;
▲ Show 20 Lines • Show All 831 Lines • ▼ Show 20 Lines; SKX_32-NEXT: retl
%res = call <2 x i32> @llvm.masked.gather.v2i32(<2 x i32*> %gep.random, i32 4, <2 x i1> %mask, <2 x i32> %src0) %res = call <2 x i32> @llvm.masked.gather.v2i32(<2 x i32*> %gep.random, i32 4, <2 x i1> %mask, <2 x i32> %src0)
ret <2 x i32>%res ret <2 x i32>%res
} }
define <2 x i32> @test24(i32* %base, <2 x i32> %ind) { define <2 x i32> @test24(i32* %base, <2 x i32> %ind) {
; KNL_64-LABEL: test24: ; KNL_64-LABEL: test24:
; KNL_64: # BB#0: ; KNL_64: # BB#0:
; KNL_64-NEXT: movb $3, %al ; KNL_64-NEXT: movb $3, %al
; KNL_64-NEXT: movzbl %al, %eax
; KNL_64-NEXT: kmovw %eax, %k1 ; KNL_64-NEXT: kmovw %eax, %k1
; KNL_64-NEXT: vpgatherqq (%rdi,%zmm0,8), %zmm1 {%k1} ; KNL_64-NEXT: vpgatherqq (%rdi,%zmm0,8), %zmm1 {%k1}
; KNL_64-NEXT: vmovaps %zmm1, %zmm0 ; KNL_64-NEXT: vmovaps %zmm1, %zmm0
; KNL_64-NEXT: retq ; KNL_64-NEXT: retq
; ;
; KNL_32-LABEL: test24: ; KNL_32-LABEL: test24:
; KNL_32: # BB#0: ; KNL_32: # BB#0:
; KNL_32-NEXT: movl {{[0-9]+}}(%esp), %eax ; KNL_32-NEXT: movl {{[0-9]+}}(%esp), %eax
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines; SKX_32-NEXT: retl
ret <2 x i64>%res ret <2 x i64>%res
} }
define <2 x i64> @test26(i64* %base, <2 x i32> %ind, <2 x i64> %src0) { define <2 x i64> @test26(i64* %base, <2 x i32> %ind, <2 x i64> %src0) {
; ;
; KNL_64-LABEL: test26: ; KNL_64-LABEL: test26:
; KNL_64: # BB#0: ; KNL_64: # BB#0:
; KNL_64-NEXT: movb $3, %al ; KNL_64-NEXT: movb $3, %al
; KNL_64-NEXT: movzbl %al, %eax
; KNL_64-NEXT: kmovw %eax, %k1 ; KNL_64-NEXT: kmovw %eax, %k1
; KNL_64-NEXT: vpgatherqq (%rdi,%zmm0,8), %zmm1 {%k1} ; KNL_64-NEXT: vpgatherqq (%rdi,%zmm0,8), %zmm1 {%k1}
; KNL_64-NEXT: vmovaps %zmm1, %zmm0 ; KNL_64-NEXT: vmovaps %zmm1, %zmm0
; KNL_64-NEXT: retq ; KNL_64-NEXT: retq
; ;
; KNL_32-LABEL: test26: ; KNL_32-LABEL: test26:
; KNL_32: # BB#0: ; KNL_32: # BB#0:
; KNL_32-NEXT: movl {{[0-9]+}}(%esp), %eax ; KNL_32-NEXT: movl {{[0-9]+}}(%esp), %eax
Show All 28 Lines
; Result type requires widening; all-ones mask ; Result type requires widening; all-ones mask
define <2 x float> @test27(float* %base, <2 x i32> %ind) { define <2 x float> @test27(float* %base, <2 x i32> %ind) {
; ;
; KNL_64-LABEL: test27: ; KNL_64-LABEL: test27:
; KNL_64: # BB#0: ; KNL_64: # BB#0:
; KNL_64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; KNL_64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; KNL_64-NEXT: vpmovsxdq %ymm0, %zmm1 ; KNL_64-NEXT: vpmovsxdq %ymm0, %zmm1
; KNL_64-NEXT: movb $3, %al ; KNL_64-NEXT: movb $3, %al
; KNL_64-NEXT: movzbl %al, %eax
; KNL_64-NEXT: kmovw %eax, %k1 ; KNL_64-NEXT: kmovw %eax, %k1
; KNL_64-NEXT: vgatherqps (%rdi,%zmm1,4), %ymm0 {%k1} ; KNL_64-NEXT: vgatherqps (%rdi,%zmm1,4), %ymm0 {%k1}
; KNL_64-NEXT: retq ; KNL_64-NEXT: retq
; ;
; KNL_32-LABEL: test27: ; KNL_32-LABEL: test27:
; KNL_32: # BB#0: ; KNL_32: # BB#0:
; KNL_32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; KNL_32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; KNL_32-NEXT: movl {{[0-9]+}}(%esp), %eax ; KNL_32-NEXT: movl {{[0-9]+}}(%esp), %eax
; KNL_32-NEXT: vpmovsxdq %ymm0, %zmm1 ; KNL_32-NEXT: vpmovsxdq %ymm0, %zmm1
; KNL_32-NEXT: movb $3, %cl ; KNL_32-NEXT: movb $3, %cl
; KNL_32-NEXT: movzbl %cl, %ecx
; KNL_32-NEXT: kmovw %ecx, %k1 ; KNL_32-NEXT: kmovw %ecx, %k1
; KNL_32-NEXT: vgatherqps (%eax,%zmm1,4), %ymm0 {%k1} ; KNL_32-NEXT: vgatherqps (%eax,%zmm1,4), %ymm0 {%k1}
; KNL_32-NEXT: retl ; KNL_32-NEXT: retl
; ;
; SKX-LABEL: test27: ; SKX-LABEL: test27:
; SKX: # BB#0: ; SKX: # BB#0:
; SKX-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[0,2,2,3] ; SKX-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[0,2,2,3]
; SKX-NEXT: movb $3, %al ; SKX-NEXT: movb $3, %al
Show All 9 Lines
; Data type requires promotion, mask is all-ones ; Data type requires promotion, mask is all-ones
define void @test28(<2 x i32>%a1, <2 x i32*> %ptr) { define void @test28(<2 x i32>%a1, <2 x i32*> %ptr) {
; ;
; ;
; KNL_64-LABEL: test28: ; KNL_64-LABEL: test28:
; KNL_64: # BB#0: ; KNL_64: # BB#0:
; KNL_64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; KNL_64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; KNL_64-NEXT: movb $3, %al ; KNL_64-NEXT: movb $3, %al
; KNL_64-NEXT: movzbl %al, %eax
; KNL_64-NEXT: kmovw %eax, %k1 ; KNL_64-NEXT: kmovw %eax, %k1
; KNL_64-NEXT: vpscatterqd %ymm0, (,%zmm1) {%k1} ; KNL_64-NEXT: vpscatterqd %ymm0, (,%zmm1) {%k1}
; KNL_64-NEXT: retq ; KNL_64-NEXT: retq
; ;
; KNL_32-LABEL: test28: ; KNL_32-LABEL: test28:
; KNL_32: # BB#0: ; KNL_32: # BB#0:
; KNL_32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; KNL_32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; KNL_32-NEXT: vpxord %zmm2, %zmm2, %zmm2 ; KNL_32-NEXT: vpxord %zmm2, %zmm2, %zmm2
▲ Show 20 Lines • Show All 766 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-shuffle-v1.ll

Show First 20 Lines • Show All 156 Lines • ▼ Show 20 Lines
; VL_BW_DQ-NEXT: retq ; VL_BW_DQ-NEXT: retq
%b = shufflevector <32 x i1> %a, <32 x i1> undef, <32 x i32> <i32 3, i32 6, i32 22, i32 12, i32 3, i32 7, i32 7, i32 0, i32 3, i32 6, i32 1, i32 13, i32 3, i32 21, i32 7, i32 0, i32 3, i32 6, i32 22, i32 12, i32 3, i32 7, i32 7, i32 0, i32 3, i32 6, i32 1, i32 13, i32 3, i32 21, i32 7, i32 0> %b = shufflevector <32 x i1> %a, <32 x i1> undef, <32 x i32> <i32 3, i32 6, i32 22, i32 12, i32 3, i32 7, i32 7, i32 0, i32 3, i32 6, i32 1, i32 13, i32 3, i32 21, i32 7, i32 0, i32 3, i32 6, i32 22, i32 12, i32 3, i32 7, i32 7, i32 0, i32 3, i32 6, i32 1, i32 13, i32 3, i32 21, i32 7, i32 0>
ret <32 x i1> %b ret <32 x i1> %b
} }
define <8 x i1> @shuf8i1_u_2_u_u_2_u_2_u(i8 %a) { define <8 x i1> @shuf8i1_u_2_u_u_2_u_2_u(i8 %a) {
; AVX512F-LABEL: shuf8i1_u_2_u_u_2_u_2_u: ; AVX512F-LABEL: shuf8i1_u_2_u_u_2_u_2_u:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
; AVX512F-NEXT: movzbl %dil, %eax ; AVX512F-NEXT: kmovw %edi, %k1
; AVX512F-NEXT: kmovw %eax, %k1
; AVX512F-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 ; AVX512F-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0
; AVX512F-NEXT: vmovdqu64 %zmm0, %zmm1 {%k1} {z} ; AVX512F-NEXT: vmovdqu64 %zmm0, %zmm1 {%k1} {z}
; AVX512F-NEXT: vpbroadcastq {{.*}}(%rip), %zmm2 ; AVX512F-NEXT: vpbroadcastq {{.*}}(%rip), %zmm2
; AVX512F-NEXT: vpermq %zmm1, %zmm2, %zmm1 ; AVX512F-NEXT: vpermq %zmm1, %zmm2, %zmm1
; AVX512F-NEXT: vpsllq $63, %zmm1, %zmm1 ; AVX512F-NEXT: vpsllq $63, %zmm1, %zmm1
; AVX512F-NEXT: vptestmq %zmm1, %zmm1, %k1 ; AVX512F-NEXT: vptestmq %zmm1, %zmm1, %k1
; AVX512F-NEXT: vmovdqu64 %zmm0, %zmm0 {%k1} {z} ; AVX512F-NEXT: vmovdqu64 %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: vpmovqw %zmm0, %xmm0 ; AVX512F-NEXT: vpmovqw %zmm0, %xmm0
Show All 12 Lines; VL_BW_DQ-NEXT: retq
%b = bitcast i8 %a to <8 x i1> %b = bitcast i8 %a to <8 x i1>
%c = shufflevector < 8 x i1> %b, <8 x i1>undef, <8 x i32> <i32 undef, i32 2, i32 undef, i32 undef, i32 2, i32 undef, i32 2, i32 undef> %c = shufflevector < 8 x i1> %b, <8 x i1>undef, <8 x i32> <i32 undef, i32 2, i32 undef, i32 undef, i32 2, i32 undef, i32 2, i32 undef>
ret <8 x i1> %c ret <8 x i1> %c
} }
define i8 @shuf8i1_10_2_9_u_3_u_2_u(i8 %a) { define i8 @shuf8i1_10_2_9_u_3_u_2_u(i8 %a) {
; AVX512F-LABEL: shuf8i1_10_2_9_u_3_u_2_u: ; AVX512F-LABEL: shuf8i1_10_2_9_u_3_u_2_u:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
; AVX512F-NEXT: movzbl %dil, %eax ; AVX512F-NEXT: kmovw %edi, %k1
; AVX512F-NEXT: kmovw %eax, %k1
; AVX512F-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z} ; AVX512F-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z}
; AVX512F-NEXT: vpxord %zmm1, %zmm1, %zmm1 ; AVX512F-NEXT: vpxord %zmm1, %zmm1, %zmm1
; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm2 = <8,2,10,u,3,u,2,u> ; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm2 = <8,2,10,u,3,u,2,u>
; AVX512F-NEXT: vpermt2q %zmm1, %zmm2, %zmm0 ; AVX512F-NEXT: vpermt2q %zmm1, %zmm2, %zmm0
; AVX512F-NEXT: vpsllq $63, %zmm0, %zmm0 ; AVX512F-NEXT: vpsllq $63, %zmm0, %zmm0
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0 ; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0
; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: kmovw %k0, %eax
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
Show All 13 Lines; VL_BW_DQ-NEXT: retq
%c = shufflevector < 8 x i1> %b, <8 x i1> zeroinitializer, <8 x i32> <i32 10, i32 2, i32 9, i32 undef, i32 3, i32 undef, i32 2, i32 undef> %c = shufflevector < 8 x i1> %b, <8 x i1> zeroinitializer, <8 x i32> <i32 10, i32 2, i32 9, i32 undef, i32 3, i32 undef, i32 2, i32 undef>
%d = bitcast <8 x i1> %c to i8 %d = bitcast <8 x i1> %c to i8
ret i8 %d ret i8 %d
} }
define i8 @shuf8i1_0_1_4_5_u_u_u_u(i8 %a) { define i8 @shuf8i1_0_1_4_5_u_u_u_u(i8 %a) {
; AVX512F-LABEL: shuf8i1_0_1_4_5_u_u_u_u: ; AVX512F-LABEL: shuf8i1_0_1_4_5_u_u_u_u:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
; AVX512F-NEXT: movzbl %dil, %eax ; AVX512F-NEXT: kmovw %edi, %k1
; AVX512F-NEXT: kmovw %eax, %k1
; AVX512F-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z} ; AVX512F-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z}
; AVX512F-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,4,5,0,1,0,1] ; AVX512F-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,4,5,0,1,0,1]
; AVX512F-NEXT: vpsllq $63, %zmm0, %zmm0 ; AVX512F-NEXT: vpsllq $63, %zmm0, %zmm0
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0 ; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0
; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: kmovw %k0, %eax
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; VL_BW_DQ-LABEL: shuf8i1_0_1_4_5_u_u_u_u: ; VL_BW_DQ-LABEL: shuf8i1_0_1_4_5_u_u_u_u:
Show All 9 Lines; VL_BW_DQ-NEXT: retq
%c = shufflevector < 8 x i1> %b, <8 x i1> undef, <8 x i32> <i32 0, i32 1, i32 4, i32 5, i32 undef, i32 undef, i32 undef, i32 undef> %c = shufflevector < 8 x i1> %b, <8 x i1> undef, <8 x i32> <i32 0, i32 1, i32 4, i32 5, i32 undef, i32 undef, i32 undef, i32 undef>
%d = bitcast <8 x i1> %c to i8 %d = bitcast <8 x i1> %c to i8
ret i8 %d ret i8 %d
} }
define i8 @shuf8i1_9_6_1_0_3_7_7_0(i8 %a) { define i8 @shuf8i1_9_6_1_0_3_7_7_0(i8 %a) {
; AVX512F-LABEL: shuf8i1_9_6_1_0_3_7_7_0: ; AVX512F-LABEL: shuf8i1_9_6_1_0_3_7_7_0:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
; AVX512F-NEXT: movzbl %dil, %eax ; AVX512F-NEXT: kmovw %edi, %k1
; AVX512F-NEXT: kmovw %eax, %k1
; AVX512F-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z} ; AVX512F-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z}
; AVX512F-NEXT: vpxord %zmm1, %zmm1, %zmm1 ; AVX512F-NEXT: vpxord %zmm1, %zmm1, %zmm1
; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm2 = [8,6,1,0,3,7,7,0] ; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm2 = [8,6,1,0,3,7,7,0]
; AVX512F-NEXT: vpermt2q %zmm1, %zmm2, %zmm0 ; AVX512F-NEXT: vpermt2q %zmm1, %zmm2, %zmm0
; AVX512F-NEXT: vpsllq $63, %zmm0, %zmm0 ; AVX512F-NEXT: vpsllq $63, %zmm0, %zmm0
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0 ; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0
; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: kmovw %k0, %eax
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
Show All 13 Lines; VL_BW_DQ-NEXT: retq
%c = shufflevector <8 x i1> %b, <8 x i1> zeroinitializer, <8 x i32> <i32 9, i32 6, i32 1, i32 0, i32 3, i32 7, i32 7, i32 0> %c = shufflevector <8 x i1> %b, <8 x i1> zeroinitializer, <8 x i32> <i32 9, i32 6, i32 1, i32 0, i32 3, i32 7, i32 7, i32 0>
%d = bitcast <8 x i1>%c to i8 %d = bitcast <8 x i1>%c to i8
ret i8 %d ret i8 %d
} }
define i8 @shuf8i1_9_6_1_10_3_7_7_0(i8 %a) { define i8 @shuf8i1_9_6_1_10_3_7_7_0(i8 %a) {
; AVX512F-LABEL: shuf8i1_9_6_1_10_3_7_7_0: ; AVX512F-LABEL: shuf8i1_9_6_1_10_3_7_7_0:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
; AVX512F-NEXT: movzbl %dil, %eax ; AVX512F-NEXT: kmovw %edi, %k1
; AVX512F-NEXT: kmovw %eax, %k1
; AVX512F-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z} ; AVX512F-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z}
; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm1 = [9,1,2,10,4,5,6,7] ; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm1 = [9,1,2,10,4,5,6,7]
; AVX512F-NEXT: vpxord %zmm2, %zmm2, %zmm2 ; AVX512F-NEXT: vpxord %zmm2, %zmm2, %zmm2
; AVX512F-NEXT: vpermt2q %zmm0, %zmm1, %zmm2 ; AVX512F-NEXT: vpermt2q %zmm0, %zmm1, %zmm2
; AVX512F-NEXT: vpsllq $63, %zmm2, %zmm0 ; AVX512F-NEXT: vpsllq $63, %zmm2, %zmm0
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0 ; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0
; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: kmovw %k0, %eax
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
Show All 13 Lines; VL_BW_DQ-NEXT: retq
%c = shufflevector <8 x i1> zeroinitializer, <8 x i1> %b, <8 x i32> <i32 9, i32 6, i32 1, i32 10, i32 3, i32 7, i32 7, i32 0> %c = shufflevector <8 x i1> zeroinitializer, <8 x i1> %b, <8 x i32> <i32 9, i32 6, i32 1, i32 10, i32 3, i32 7, i32 7, i32 0>
%d = bitcast <8 x i1>%c to i8 %d = bitcast <8 x i1>%c to i8
ret i8 %d ret i8 %d
} }
define i8 @shuf8i1__9_6_1_10_3_7_7_1(i8 %a) { define i8 @shuf8i1__9_6_1_10_3_7_7_1(i8 %a) {
; AVX512F-LABEL: shuf8i1__9_6_1_10_3_7_7_1: ; AVX512F-LABEL: shuf8i1__9_6_1_10_3_7_7_1:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
; AVX512F-NEXT: movzbl %dil, %eax ; AVX512F-NEXT: kmovw %edi, %k1
; AVX512F-NEXT: kmovw %eax, %k1
; AVX512F-NEXT: movb $51, %al ; AVX512F-NEXT: movb $51, %al
; AVX512F-NEXT: movzbl %al, %eax
; AVX512F-NEXT: kmovw %eax, %k2 ; AVX512F-NEXT: kmovw %eax, %k2
; AVX512F-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 ; AVX512F-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0
; AVX512F-NEXT: vmovdqu64 %zmm0, %zmm1 {%k2} {z} ; AVX512F-NEXT: vmovdqu64 %zmm0, %zmm1 {%k2} {z}
; AVX512F-NEXT: vmovdqu64 %zmm0, %zmm0 {%k1} {z} ; AVX512F-NEXT: vmovdqu64 %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm2 = [9,6,1,0,3,7,7,1] ; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm2 = [9,6,1,0,3,7,7,1]
; AVX512F-NEXT: vpermt2q %zmm0, %zmm2, %zmm1 ; AVX512F-NEXT: vpermt2q %zmm0, %zmm2, %zmm1
; AVX512F-NEXT: vpsllq $63, %zmm1, %zmm0 ; AVX512F-NEXT: vpsllq $63, %zmm1, %zmm0
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0 ; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0
▲ Show 20 Lines • Show All 113 Lines • Show Last 20 Lines