[mips][microMIPS][DSP] Implement BALIGN, BITREV, BPOSGE32, CMP*, CMPGDU*, CMPGU* and CMPU* instructions

[zbuljan]

Summary

The patch implements microMIPSDSP instructions: BALIGN, BITREV, BPOSGE32, CMP*, CMPGDU*, CMPGU* and CMPU*.

[zbuljan]

Rebased to work with top of the tree.
Added new template argument (DAGOperand) to existing BPOSGE32_DESC_BASE class.
Desc. class for microMIPSDSP BPOSGE32 now uses brtarget_mm operand instead of brtarget operand.
Removed unnecessary changes in encoder and decoder method of brtarget operand.

[sdardis]

lib/Target/Mips/MicroMipsDSPInstrFormats.td

279 ↗

(On Diff #50393)

Pool occurs twice in the name of this class, is the second mention necessary?

lib/Target/Mips/MicroMipsDSPInstrInfo.td

392–404 ↗

(On Diff #50393)

Can the DESC_BASE be turned into a parameterless class? BALIGN_MMR2_DESC seems to be the only class using the description BASE.

lib/Target/Mips/MipsDSPInstrInfo.td

1230–1232 ↗

(On Diff #50393)

Why was ISA_DSPR2 removed? These instructions are only defined for DSP revision 2.

1270 ↗

(On Diff #50393)

Same here, this instruction is defined for DSP revision 2.

[mpf]

This patch mixes some independent features. If I remember correctly BALIGN and BITREV have been added to the MIPSR6 ISA (and microMIPSR6) and were previously only in DSPR2. The BPOSGE32C instruction is part of DSPR3 and is the only new instruction in DSPR3 with BPOSGE32 being removed from microMIPS DSPR3 but retained in MIPS DSPR3. The CMP* are pre-existing DSPR2 (or may even be DSPR1 I do not know from memory).

[mpf]

Missed a few extra details... DSPR3 requires a minimum of MIPSR6/microMIPSR6 and DSPR1/2 is allowed with MIPSR6 but not allowed with microMIPSR6. The DSP ASE also has flags to set in the .MIPS.abiflags section if this is not already implemented. These details are partly important for correctness and partly for accurate tracking of object content. These need not be dealt with in this patch, just extra things to handle.

[sdardis]

Thanks Matthew, extra change highlighted.

lib/Target/Mips/MicroMipsDSPInstrInfo.td

518 ↗

(On Diff #50393)

This needs to be marked as being unavailable on microMIPSDSPR6.

[zbuljan]

Rebased to work with TOT.
Class POOL32_3RB0_FMT renamed to POOL32_3RB0POOL_FMT.
Changed BALIGN_MMR2_DESC to be parameterless class.
Instruction BPOSGE32 separated from microMIPSDSPR6 using ISA_MIPS1_NOT_32R6_64R6 flag.
ISA_DSPR2 is returned to CMPGDU* and BALIGN because these instructions are for DSP2.
Added valid-dsp.txt and valid-dsp.s for test of microMIPSDSP BPOSGE32 instruction which is removed in microMIPSr6.

[sdardis]

Test that bposge32 is invalid for microMIPS32r6 and microMIPS64r6 invalid.s tests along with a comment noting that it is a DSP instruction.

lib/Target/Mips/MicroMipsDSPInstrFormats.td

279 ↗

(On Diff #56400)

"pool" does not need to be a parameter for this class. Bits 31-26 should correspond to POOL32A's opcode. And it should be named "POOL32A_3RB0_FMT". Sorry for the bikeshedding there.

303 ↗

(On Diff #56400)

Add a class describing POOL32S 3 register bit0 format for cmpgu.<cond>.qb.

lib/Target/Mips/MicroMipsDSPInstrInfo.td

167–172 ↗

(On Diff #56400)

These should inherit from POOL32S_3RB0_FMT.

test/MC/Disassembler/Mips/micromips32r3/valid-dsp.txt

3 ↗

(On Diff #56400)

This should go in the micromips-dsp and micromips-dspr2 sets of tests.

test/MC/Mips/micromips/valid-dsp.s

4 ↗

(On Diff #56400)

This should go in the relevant existing micromips-dsp/micromips-dspr2 tests.

[sdardis]

I hit comment by accident.

Thanks.
Simon

[zbuljan]

Rebased to work with TOT.
Renamed format class POOL32_3RB0_FMT to POOL32S_3RB0_FMT and removed unnecessary parametar.
Test files for microMIPS32r3 + DSPr1 are placed in micromips-dsp folders.
Added invalid tests for BPOSGE32 (BPOSGE32 is microMIPS DSP instruction but it is removed in release 6).

[sdardis]

LGTM with cmp.cond.ph descriptions fixed along with the corresponding tests.

lib/Target/Mips/MicroMipsDSPInstrInfo.td

161–163 ↗

(On Diff #57157)

If I'm reading this right, I suspect you have written down the instructions from the assembly format and written the minor opcodes assuming the encoding description table is in the same order. They are in a different order in the encoding description.

The minor opcodes for cmp.eq.ph and cmp.le.ph are swapped.

llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrFormats.td

 }
 
 class POOL32I_IMMB0_FMT<string opstr, bits<5> op> : MMDSPInst<opstr> {
   bits<16> offset;
 
   let Inst{31-26} = 0b010000;
   let Inst{25-21} = op;
   let Inst{20-16} = 0;
-  let Inst{15-0} = offset;
+  let Inst{15-0}  = offset;
 }
+
+class POOL32A_2RBP_FMT<string opstr> : MMDSPInst<opstr> {
+  bits<5> rt;
+  bits<5> rs;
+  bits<2> bp;
+
+  let Inst{31-26} = 0;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rs;
+  let Inst{15-14} = bp;
+  let Inst{13-6}  = 0b00100010;
+  let Inst{5-0}   = 0b111100;
+}
+
+class POOL32A_2RB0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
+  bits<5> rt;
+  bits<5> rs;
+
+  let Inst{31-26} = 0;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rs;
+  let Inst{15-10} = 0;
+  let Inst{9-0}   = op;
+}
+
+class POOL32S_3RB0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
+  bits<5> rt;
+  bits<5> rs;
+  bits<5> rd;
+
+  let Inst{31-26} = 0b010110;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rs;
+  let Inst{15-11} = rd;
+  let Inst{10}    = 0b0;
+  let Inst{9-0}   = op;
+}
+
+class POOL32A_2R2B0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
+  bits<5> rt;
+  bits<5> rs;
+
+  let Inst{31-26} = 0;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rs;
+  let Inst{15-11} = 0;
+  let Inst{10}    = 0;
+  let Inst{9-0}   = op;
+}

llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrInfo.td

 class SHILO_MM_ENC : POOL32A_4B0SHIFT6AC4B0_FMT<"shilo", 0b0000011101>;
 class SHILOV_MM_ENC : POOL32A_5B01RAC_FMT<"shilov", 0b01001001>;
 class WRDSP_MM_ENC : POOL32A_1RMASK7_FMT<"wrdsp", 0b01011001>;
 class APPEND_MMR2_ENC : POOL32A_2RSA5B0_FMT<"append", 0b1000010101>;
 class MODSUB_MM_ENC : POOL32A_3RB0_FMT<"modsub", 0b1010010101>;
 class MULSA_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"mulsa.w.ph", 0b10110010>;
 class MULSAQ_S_W_PH_MM_ENC : POOL32A_2RAC_FMT<"mulsaq_s.w.ph", 0b11110010>;
 class BPOSGE32C_MMR3_ENC : POOL32I_IMMB0_FMT<"bposge32c", 0b11001>;
+class BITREV_MM_ENC : POOL32A_2R_FMT<"bitrev", 0b0011000100>;
+class BALIGN_MMR2_ENC : POOL32A_2RBP_FMT<"balign">;
+class BPOSGE32_MM_ENC : POOL32I_IMMB0_FMT<"bposge32", 0b11011>;
+class CMP_EQ_PH_MM_ENC : POOL32A_2RB0_FMT<"cmp.eq.ph", 0b0000000101>;
+class CMP_LE_PH_MM_ENC : POOL32A_2RB0_FMT<"cmp.le.ph", 0b0010000101>;
+class CMP_LT_PH_MM_ENC : POOL32A_2RB0_FMT<"cmp.lt.ph", 0b0001000101>;
+class CMPGDU_EQ_QB_MMR2_ENC : POOL32A_3RB0_FMT<"cmpgdu.eq.qb", 0b0110000101>;
+class CMPGDU_LT_QB_MMR2_ENC : POOL32A_3RB0_FMT<"cmpgdu.lt.qb", 0b0111000101>;
+class CMPGDU_LE_QB_MMR2_ENC : POOL32A_3RB0_FMT<"cmpgdu.le.qb", 0b1000000101>;
+class CMPGU_EQ_QB_MM_ENC : POOL32S_3RB0_FMT<"cmpgu.eq.qb", 0b0011000101>;
+class CMPGU_LT_QB_MM_ENC : POOL32S_3RB0_FMT<"cmpgu.lt.qb", 0b0100000101>;
+class CMPGU_LE_QB_MM_ENC : POOL32S_3RB0_FMT<"cmpgu.le.qb", 0b0101000101>;
+class CMPU_EQ_QB_MM_ENC : POOL32A_2R2B0_FMT<"cmpu.eq.qb", 0b1001000101>;
+class CMPU_LT_QB_MM_ENC : POOL32A_2R2B0_FMT<"cmpu.lt.qb", 0b1010000101>;
+class CMPU_LE_QB_MM_ENC : POOL32A_2R2B0_FMT<"cmpu.le.qb", 0b1011000101>;
 
 // Instruction desc.
 class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
                                 InstrItinClass itin, RegisterOperand ROD,
                                 RegisterOperand ROS = ROD> {
   dag OutOperandList = (outs ROD:$rt);
   dag InOperandList = (ins ROS:$rs);
   string AsmString = !strconcat(opstr, "\t$rt, $rs");
class BPOSGE32C_MMR3_DESC {
   dag InOperandList = (ins brtarget1SImm16:$offset);
   string AsmString = !strconcat("bposge32c", "\t$offset");
   InstrItinClass Itinerary = NoItinerary;
   bit isBranch = 1;
   bit isTerminator = 1;
   bit hasDelaySlot = 0;
 }
 
+class BALIGN_MMR2_DESC {
+  dag OutOperandList = (outs GPR32Opnd:$rt);
+  dag InOperandList = (ins GPR32Opnd:$rs, uimm2:$bp, GPR32Opnd:$src);
+  string AsmString = !strconcat("balign", "\t$rt, $rs, $bp");
+  list<dag> Pattern =  [(set GPR32Opnd:$rt, (int_mips_balign GPR32Opnd:$src,
+                                                             GPR32Opnd:$rs,
+                                                             immZExt2:$bp))];
+  InstrItinClass Itinerary = NoItinerary;
+  string Constraints = "$src = $rt";
+}
+
+class BITREV_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<"bitrev", int_mips_bitrev,
+                                                 NoItinerary, GPR32Opnd>;
+
+class BPOSGE32_MM_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget_mm,
+                                            NoItinerary>;
+
 // Instruction defs.
 // microMIPS DSP Rev 1
 def ADDQ_PH_MM : DspMMRel, ADDQ_PH_MM_ENC, ADDQ_PH_DESC;
 def ADDQ_S_PH_MM : DspMMRel, ADDQ_S_PH_MM_ENC, ADDQ_S_PH_DESC;
 def ADDQ_S_W_MM : DspMMRel, ADDQ_S_W_MM_ENC, ADDQ_S_W_DESC;
 def ADDU_QB_MM : DspMMRel, ADDU_QB_MM_ENC, ADDU_QB_DESC;
 def ADDU_S_QB_MM : DspMMRel, ADDU_S_QB_MM_ENC, ADDU_S_QB_DESC;
 def ADDSC_MM : DspMMRel, ADDSC_MM_ENC, ADDSC_DESC;

 def PACKRL_PH_MM : DspMMRel, PACKRL_PH_MM_ENC, PACKRL_PH_DESC;
 def PICK_PH_MM : DspMMRel, PICK_PH_MM_ENC, PICK_PH_DESC;
 def PICK_QB_MM : DspMMRel, PICK_QB_MM_ENC, PICK_QB_DESC;
 def SHILO_MM : DspMMRel, SHILO_MM_ENC, SHILO_DESC;
 def SHILOV_MM : DspMMRel, SHILOV_MM_ENC, SHILOV_DESC;
 def WRDSP_MM : DspMMRel, WRDSP_MM_ENC, WRDSP_MM_DESC;
 def MODSUB_MM : DspMMRel, MODSUB_MM_ENC, MODSUB_DESC;
 def MULSAQ_S_W_PH_MM : DspMMRel, MULSAQ_S_W_PH_MM_ENC, MULSAQ_S_W_PH_DESC;
+def BITREV_MM : DspMMRel, BITREV_MM_ENC, BITREV_MM_DESC;
+def BPOSGE32_MM : DspMMRel, BPOSGE32_MM_ENC, BPOSGE32_MM_DESC,
+                  ISA_MIPS1_NOT_32R6_64R6;
+def CMP_EQ_PH_MM : DspMMRel, CMP_EQ_PH_MM_ENC, CMP_EQ_PH_DESC;
+def CMP_LT_PH_MM : DspMMRel, CMP_LT_PH_MM_ENC, CMP_LT_PH_DESC;
+def CMP_LE_PH_MM : DspMMRel, CMP_LE_PH_MM_ENC, CMP_LE_PH_DESC;
+def CMPGU_EQ_QB_MM : DspMMRel, CMPGU_EQ_QB_MM_ENC, CMPGU_EQ_QB_DESC;
+def CMPGU_LT_QB_MM : DspMMRel, CMPGU_LT_QB_MM_ENC, CMPGU_LT_QB_DESC;
+def CMPGU_LE_QB_MM : DspMMRel, CMPGU_LE_QB_MM_ENC, CMPGU_LE_QB_DESC;
+def CMPU_EQ_QB_MM : DspMMRel, CMPU_EQ_QB_MM_ENC, CMPU_EQ_QB_DESC;
+def CMPU_LT_QB_MM : DspMMRel, CMPU_LT_QB_MM_ENC, CMPU_LT_QB_DESC;
+def CMPU_LE_QB_MM : DspMMRel, CMPU_LE_QB_MM_ENC, CMPU_LE_QB_DESC;
 // microMIPS DSP Rev 2
 def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC,
                      ISA_DSPR2;
 def ADDQH_PH_MMR2 : DspMMRel, ADDQH_PH_MMR2_ENC, ADDQH_PH_DESC, ISA_DSPR2;
 def ADDQH_R_PH_MMR2 : DspMMRel, ADDQH_R_PH_MMR2_ENC, ADDQH_R_PH_DESC, ISA_DSPR2;
 def ADDQH_W_MMR2 : DspMMRel, ADDQH_W_MMR2_ENC, ADDQH_W_DESC, ISA_DSPR2;
 def ADDQH_R_W_MMR2 : DspMMRel, ADDQH_R_W_MMR2_ENC, ADDQH_R_W_DESC, ISA_DSPR2;
 def ADDU_PH_MMR2 : DspMMRel, ADDU_PH_MMR2_ENC, ADDU_PH_DESC, ISA_DSPR2;
 def ADDU_S_PH_MMR2 : DspMMRel, ADDU_S_PH_MMR2_ENC, ADDU_S_PH_DESC, ISA_DSPR2;
 def ADDUH_QB_MMR2 : DspMMRel, ADDUH_QB_MMR2_ENC, ADDUH_QB_DESC, ISA_DSPR2;
 def ADDUH_R_QB_MMR2 : DspMMRel, ADDUH_R_QB_MMR2_ENC, ADDUH_R_QB_DESC, ISA_DSPR2;
 def DPA_W_PH_MMR2 : DspMMRel, DPA_W_PH_MMR2_ENC, DPA_W_PH_DESC, ISA_DSPR2;
 def DPAQX_S_W_PH_MMR2 : DspMMRel, DPAQX_S_W_PH_MMR2_ENC, DPAQX_S_W_PH_DESC,
                         ISA_DSPR2;
 def DPAQX_SA_W_PH_MMR2 : DspMMRel, DPAQX_SA_W_PH_MMR2_ENC, DPAQX_SA_W_PH_DESC,
                          ISA_DSPR2;
 def DPAX_W_PH_MMR2 : DspMMRel, DPAX_W_PH_MMR2_ENC, DPAX_W_PH_DESC, ISA_DSPR2;
 def SHRA_QB_MMR2 : DspMMRel, SHRA_QB_MMR2_ENC, SHRA_QB_MMR2_DESC, ISA_DSPR2;
 def SHRA_R_QB_MMR2 : DspMMRel, SHRA_R_QB_MMR2_ENC, SHRA_R_QB_MMR2_DESC,
                      ISA_DSPR2;
 def SHRAV_QB_MMR2 : DspMMRel, SHRAV_QB_MMR2_ENC, SHRAV_QB_MMR2_DESC, ISA_DSPR2;
 def SHRAV_R_QB_MMR2 : DspMMRel, SHRAV_R_QB_MMR2_ENC, SHRAV_R_QB_MMR2_DESC,
                       ISA_DSPR2;
+def BALIGN_MMR2 : DspMMRel, BALIGN_MMR2_ENC, BALIGN_MMR2_DESC, ISA_DSPR2;
+def CMPGDU_EQ_QB_MMR2 : DspMMRel, CMPGDU_EQ_QB_MMR2_ENC, CMPGDU_EQ_QB_DESC,
+                        ISA_DSPR2;
+def CMPGDU_LT_QB_MMR2 : DspMMRel, CMPGDU_LT_QB_MMR2_ENC, CMPGDU_LT_QB_DESC,
+                        ISA_DSPR2;
+def CMPGDU_LE_QB_MMR2 : DspMMRel, CMPGDU_LE_QB_MMR2_ENC, CMPGDU_LE_QB_DESC,
+                        ISA_DSPR2;
 def SHRL_PH_MMR2 : DspMMRel, SHRL_PH_MMR2_ENC, SHRL_PH_MMR2_DESC, ISA_DSPR2;
 def SHRLV_PH_MMR2 : DspMMRel, SHRLV_PH_MMR2_ENC, SHRLV_PH_MMR2_DESC, ISA_DSPR2;
 def SUBQH_PH_MMR2 : DspMMRel, SUBQH_PH_MMR2_ENC, SUBQH_PH_DESC, ISA_DSPR2;
 def SUBQH_R_PH_MMR2 : DspMMRel, SUBQH_R_PH_MMR2_ENC, SUBQH_R_PH_DESC, ISA_DSPR2;
 def SUBQH_W_MMR2 : DspMMRel, SUBQH_W_MMR2_ENC, SUBQH_W_DESC, ISA_DSPR2;
 def SUBQH_R_W_MMR2 : DspMMRel, SUBQH_R_W_MMR2_ENC, SUBQH_R_W_DESC, ISA_DSPR2;
 def SUBU_PH_MMR2 : DspMMRel, SUBU_PH_MMR2_ENC, SUBU_PH_DESC, ISA_DSPR2;
 def SUBU_S_PH_MMR2 : DspMMRel, SUBU_S_PH_MMR2_ENC, SUBU_S_PH_DESC, ISA_DSPR2;

llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td

 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
                              InstrItinClass itin, RegisterOperand ROS,
                              RegisterOperand ROT = ROS> {
   dag OutOperandList = (outs);
   dag InOperandList = (ins ROS:$rs, ROT:$rt);
   string AsmString = !strconcat(instr_asm, "\t$rs, $rt");
   list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
   InstrItinClass Itinerary = itin;
+  string BaseOpcode = instr_asm;
 }
 
 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
                              InstrItinClass itin, RegisterOperand ROD,
                              RegisterOperand ROS,  RegisterOperand ROT = ROS> {
   dag OutOperandList = (outs ROD:$rd);
   dag InOperandList = (ins ROS:$rs, ROT:$rt);
   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO, InstrItinClass itin> {
   string BaseOpcode = instr_asm;
 }
 
 class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
   MipsPseudo<(outs GPR32Opnd:$dst), (ins), [(set GPR32Opnd:$dst, (OpNode))]> {
   bit usesCustomInserter = 1;
 }
 
-class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> {
+class BPOSGE32_DESC_BASE<string instr_asm, DAGOperand opnd,
+                         InstrItinClass itin> {
   dag OutOperandList = (outs);
-  dag InOperandList = (ins brtarget:$offset);
+  dag InOperandList = (ins opnd:$offset);
   string AsmString = !strconcat(instr_asm, "\t$offset");
   InstrItinClass Itinerary = itin;
   bit isBranch = 1;
   bit isTerminator = 1;
   bit hasDelaySlot = 1;
+  string BaseOpcode = instr_asm;
 }
 
 class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
                      InstrItinClass itin> {
   dag OutOperandList = (outs GPR32Opnd:$rt);
   dag InOperandList = (ins GPR32Opnd:$src, GPR32Opnd:$rs);
   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
   list<dag> Pattern = [(set GPR32Opnd:$rt, (OpNode GPR32Opnd:$src, GPR32Opnd:$rs))];
class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,
                      Uses<[DSPCCond]>;
 
 class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>;
 
 class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>;
 
 class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>;
 
-class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>;
+class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget, NoItinerary>;
 
 // Extr
 class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>,
                   Uses<[DSPPos]>, Defs<[DSPEFI]>;
 
 class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>,
                    Uses<[DSPPos]>, Defs<[DSPEFI]>;
 

 def DPAQ_SA_L_W : DspMMRel, DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
 def DPSQ_SA_L_W : DspMMRel, DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
 def MULT_DSP : DspMMRel, MULT_DSP_ENC, MULT_DSP_DESC;
 def MULTU_DSP : DspMMRel, MULTU_DSP_ENC, MULTU_DSP_DESC;
 def MADD_DSP : DspMMRel, MADD_DSP_ENC, MADD_DSP_DESC;
 def MADDU_DSP : DspMMRel, MADDU_DSP_ENC, MADDU_DSP_DESC;
 def MSUB_DSP : DspMMRel, MSUB_DSP_ENC, MSUB_DSP_DESC;
 def MSUBU_DSP : DspMMRel, MSUBU_DSP_ENC, MSUBU_DSP_DESC;
-def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
-def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
-def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
-def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;
-def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;
-def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
-def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
-def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC;
-def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC;
-def BITREV : BITREV_ENC, BITREV_DESC;
+def CMPU_EQ_QB : DspMMRel, CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
+def CMPU_LT_QB : DspMMRel, CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
+def CMPU_LE_QB : DspMMRel, CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
+def CMPGU_EQ_QB : DspMMRel, CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;
+def CMPGU_LT_QB : DspMMRel, CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;
+def CMPGU_LE_QB : DspMMRel, CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
+def CMP_EQ_PH : DspMMRel, CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
+def CMP_LT_PH : DspMMRel, CMP_LT_PH_ENC, CMP_LT_PH_DESC;
+def CMP_LE_PH : DspMMRel, CMP_LE_PH_ENC, CMP_LE_PH_DESC;
+def BITREV : DspMMRel, BITREV_ENC, BITREV_DESC;
 def PACKRL_PH : DspMMRel, PACKRL_PH_ENC, PACKRL_PH_DESC;
 def REPL_QB : DspMMRel, REPL_QB_ENC, REPL_QB_DESC;
 def REPL_PH : DspMMRel, REPL_PH_ENC, REPL_PH_DESC;
 def REPLV_QB : DspMMRel, REPLV_QB_ENC, REPLV_QB_DESC;
 def REPLV_PH : DspMMRel, REPLV_PH_ENC, REPLV_PH_DESC;
 def PICK_QB : DspMMRel, PICK_QB_ENC, PICK_QB_DESC;
 def PICK_PH : DspMMRel, PICK_PH_ENC, PICK_PH_DESC;
 def LWX : DspMMRel, LWX_ENC, LWX_DESC;
 def LHX : DspMMRel, LHX_ENC, LHX_DESC;
 def LBUX : DspMMRel, LBUX_ENC, LBUX_DESC;
+let AdditionalPredicates = [NotInMicroMips] in {
   def BPOSGE32 : DspMMRel, BPOSGE32_ENC, BPOSGE32_DESC;
+}
 def INSV : DspMMRel, INSV_ENC, INSV_DESC;
 def EXTP : DspMMRel, EXTP_ENC, EXTP_DESC;
 def EXTPV : DspMMRel, EXTPV_ENC, EXTPV_DESC;
 def EXTPDP : DspMMRel, EXTPDP_ENC, EXTPDP_DESC;
 def EXTPDPV : DspMMRel, EXTPDPV_ENC, EXTPDPV_DESC;
 def EXTR_W : DspMMRel, EXTR_W_ENC, EXTR_W_DESC;
 def EXTRV_W : DspMMRel, EXTRV_W_ENC, EXTRV_W_DESC;
 def EXTR_R_W : DspMMRel, EXTR_R_W_ENC, EXTR_R_W_DESC;
let AdditionalPredicates = [NotInMicroMips] in {
   def WRDSP : WRDSP_ENC, WRDSP_DESC;
 }
 
 // MIPS DSP Rev 2
 def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC, ISA_DSPR2;
 def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC, ISA_DSPR2;
 def SUBU_PH : DspMMRel, SUBU_PH_ENC, SUBU_PH_DESC, ISA_DSPR2;
 def SUBU_S_PH : DspMMRel, SUBU_S_PH_ENC, SUBU_S_PH_DESC, ISA_DSPR2;
-def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC, ISA_DSPR2;
-def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC, ISA_DSPR2;
-def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC, ISA_DSPR2;
+def CMPGDU_EQ_QB : DspMMRel, CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC, ISA_DSPR2;
+def CMPGDU_LT_QB : DspMMRel, CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC, ISA_DSPR2;
+def CMPGDU_LE_QB : DspMMRel, CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC, ISA_DSPR2;
 def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC, ISA_DSPR2;
 def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC, ISA_DSPR2;
 def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC, ISA_DSPR2;
 def SUBUH_QB : DspMMRel, SUBUH_QB_ENC, SUBUH_QB_DESC, ISA_DSPR2;
 def SUBUH_R_QB : DspMMRel, SUBUH_R_QB_ENC, SUBUH_R_QB_DESC, ISA_DSPR2;
 def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC, ISA_DSPR2;
 def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC, ISA_DSPR2;
 def SUBQH_PH : DspMMRel, SUBQH_PH_ENC, SUBQH_PH_DESC, ISA_DSPR2;

 def PRECR_SRA_R_PH_W : DspMMRel, PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC, ISA_DSPR2;
 def SHRA_QB : DspMMRel, SHRA_QB_ENC, SHRA_QB_DESC, ISA_DSPR2;
 def SHRAV_QB : DspMMRel, SHRAV_QB_ENC, SHRAV_QB_DESC, ISA_DSPR2;
 def SHRA_R_QB : DspMMRel, SHRA_R_QB_ENC, SHRA_R_QB_DESC, ISA_DSPR2;
 def SHRAV_R_QB : DspMMRel, SHRAV_R_QB_ENC, SHRAV_R_QB_DESC, ISA_DSPR2;
 def SHRL_PH : DspMMRel, SHRL_PH_ENC, SHRL_PH_DESC, ISA_DSPR2;
 def SHRLV_PH : DspMMRel, SHRLV_PH_ENC, SHRLV_PH_DESC, ISA_DSPR2;
 def APPEND : DspMMRel, APPEND_ENC, APPEND_DESC, ISA_DSPR2;
-def BALIGN : BALIGN_ENC, BALIGN_DESC, ISA_DSPR2;
+def BALIGN : DspMMRel, BALIGN_ENC, BALIGN_DESC, ISA_DSPR2;
 def PREPEND : DspMMRel, PREPEND_ENC, PREPEND_DESC, ISA_DSPR2;
 
 // Pseudos.
 let isPseudo = 1, isCodeGenOnly = 1 in {
   // Pseudo instructions for loading and storing accumulator registers.
   def LOAD_ACC64DSP  : Load<"", ACC64DSPOpnd>;
   def STORE_ACC64DSP : Store<"", ACC64DSPOpnd>;
 

llvm/trunk/test/MC/Disassembler/Mips/micromips-dsp/valid-micromips32r3.txt

+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r3 -mattr=micromips -mattr=+dsp | FileCheck %s
+
+0x43 0x60 0x00 0xab # CHECK: bposge32 342

llvm/trunk/test/MC/Disassembler/Mips/micromips-dsp/valid.txt

 0x00 0x30 0x05 0xfc # CHECK: repl.qb $1, 128
 0x00 0x22 0x03 0x3c # CHECK: replv.ph $1, $2
 0x00 0x22 0x13 0x3c # CHECK: replv.qb $1, $2
 0x00 0x01 0x82 0x7c # CHECK: mthlip $1, $ac2
 0x00 0xa7 0xd6 0x7c # CHECK: wrdsp $5
 0x00 0xa0 0x96 0x7c # CHECK: wrdsp $5, 2
 0x00 0xc5 0x22 0x95 # CHECK: modsub $4, $5, $6
 0x00 0x43 0x3c 0xbc # CHECK: mulsaq_s.w.ph $ac0, $3, $2
+0x00 0x43 0x31 0x3c # CHECK: bitrev $2, $3
+0x00 0x62 0x00 0x05 # CHECK: cmp.eq.ph $2, $3
+0x00 0x62 0x00 0x85 # CHECK: cmp.le.ph $2, $3
+0x00 0x62 0x00 0x45 # CHECK: cmp.lt.ph $2, $3
+0x58 0x62 0x08 0xc5 # CHECK: cmpgu.eq.qb $1, $2, $3
+0x58 0x62 0x09 0x05 # CHECK: cmpgu.lt.qb $1, $2, $3
+0x58 0x62 0x09 0x45 # CHECK: cmpgu.le.qb $1, $2, $3
+0x00 0x41 0x02 0x45 # CHECK: cmpu.eq.qb $1, $2
+0x00 0x41 0x02 0x85 # CHECK: cmpu.lt.qb $1, $2
+0x00 0x41 0x02 0xc5 # CHECK: cmpu.le.qb $1, $2

llvm/trunk/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt

 0x00 0x62 0x08 0x95 # CHECK: muleu_s.ph.qbl $1, $2, $3
 0x00 0x62 0x08 0xd5 # CHECK: muleu_s.ph.qbr $1, $2, $3
 0x00,0x62,0x09,0x15 # CHECK: mulq_rs.ph $1, $2, $3
 0x00 0x22 0x1a 0x55 # CHECK: prepend $1, $2, 3
 0x00 0xa7 0xd6 0x7c # CHECK: wrdsp $5
 0x00 0xa0 0x96 0x7c # CHECK: wrdsp $5, 2
 0x00 0x64 0x2a 0x15 # CHECK: append $3, $4, 5
 0x00 0x43 0x2c 0xbc # CHECK: mulsa.w.ph $ac0, $3, $2
+0x00 0x43 0xc8 0xbc # CHECK: balign $2, $3, 3
+0x00 0x43 0x31 0x3c # CHECK: bitrev $2, $3
+0x00 0x62 0x00 0x05 # CHECK: cmp.eq.ph $2, $3
+0x00 0x62 0x00 0x85 # CHECK: cmp.le.ph $2, $3
+0x00 0x62 0x00 0x45 # CHECK: cmp.lt.ph $2, $3
+0x00 0x62 0x09 0x85 # CHECK: cmpgdu.eq.qb $1, $2, $3
+0x00 0x62 0x09 0xc5 # CHECK: cmpgdu.lt.qb $1, $2, $3
+0x00 0x62 0x0a 0x05 # CHECK: cmpgdu.le.qb $1, $2, $3
+0x58 0x62 0x08 0xc5 # CHECK: cmpgu.eq.qb $1, $2, $3
+0x58 0x62 0x09 0x05 # CHECK: cmpgu.lt.qb $1, $2, $3
+0x58 0x62 0x09 0x45 # CHECK: cmpgu.le.qb $1, $2, $3
+0x00 0x41 0x02 0x45 # CHECK: cmpu.eq.qb $1, $2
+0x00 0x41 0x02 0x85 # CHECK: cmpu.lt.qb $1, $2
+0x00 0x41 0x02 0xc5 # CHECK: cmpu.le.qb $1, $2

llvm/trunk/test/MC/Mips/micromips-dsp/invalid.s

# RUN: FileCheck %s < %t1
   shra_r.ph $3, $4, -1     # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate
   // FIXME: Following invalid tests are temporarely disabled, until operand check for uimm5 is added
   shra_r.w $3, $4, 32      # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
   shra_r.w $3, $4, -1      # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
   shrl.qb $3, $4, 8        # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
   shrl.qb $3, $4, -1       # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
   shilo $ac1, 64           # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate
   shilo $ac1, -64          # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate
+                           # bposge32 is microMIPS DSP instruction but it is removed in Release 6
+  bposge32 342             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

llvm/trunk/test/MC/Mips/micromips-dsp/valid-micromips32r3.s

+# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r3 -mattr=micromips -mattr=+dsp | FileCheck %s
+
+  .set noat
+  bposge32 342                 # CHECK: bposge32 342            # encoding: [0x43,0x60,0x00,0xab]

llvm/trunk/test/MC/Mips/micromips-dsp/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dsp | FileCheck %s
   replv.ph $1, $2              # CHECK: replv.ph $1, $2         # encoding: [0x00,0x22,0x03,0x3c]
   replv.qb $1, $2              # CHECK: replv.qb $1, $2         # encoding: [0x00,0x22,0x13,0x3c]
   mthlip $1, $ac2              # CHECK: mthlip $1, $ac2         # encoding: [0x00,0x01,0x82,0x7c]
   wrdsp $5                     # CHECK: wrdsp $5                # encoding: [0x00,0xa7,0xd6,0x7c]
   wrdsp $5, 2                  # CHECK: wrdsp $5, 2             # encoding: [0x00,0xa0,0x96,0x7c]
   wrdsp $5, 31                 # CHECK: wrdsp $5                # encoding: [0x00,0xa7,0xd6,0x7c]
   modsub $4, $5, $6            # CHECK: modsub $4, $5, $6       # encoding: [0x00,0xc5,0x22,0x95]
   mulsaq_s.w.ph $ac0, $3, $2   # CHECK: mulsaq_s.w.ph $ac0, $3, $2 # encoding: [0x00,0x43,0x3c,0xbc]
+  bitrev $2, $3                # CHECK: bitrev $2, $3           # encoding: [0x00,0x43,0x31,0x3c]
+  cmp.eq.ph $2, $3             # CHECK: cmp.eq.ph $2, $3        # encoding: [0x00,0x62,0x00,0x05]
+  cmp.le.ph $2, $3             # CHECK: cmp.le.ph $2, $3        # encoding: [0x00,0x62,0x00,0x85]
+  cmp.lt.ph $2, $3             # CHECK: cmp.lt.ph $2, $3        # encoding: [0x00,0x62,0x00,0x45]
+  cmpgu.eq.qb $1, $2, $3       # CHECK: cmpgu.eq.qb $1, $2, $3  # encoding: [0x58,0x62,0x08,0xc5]
+  cmpgu.lt.qb $1, $2, $3       # CHECK: cmpgu.lt.qb $1, $2, $3  # encoding: [0x58,0x62,0x09,0x05]
+  cmpgu.le.qb $1, $2, $3       # CHECK: cmpgu.le.qb $1, $2, $3  # encoding: [0x58,0x62,0x09,0x45]
+  cmpu.eq.qb $1, $2            # CHECK: cmpu.eq.qb $1, $2       # encoding: [0x00,0x41,0x02,0x45]
+  cmpu.lt.qb $1, $2            # CHECK: cmpu.lt.qb $1, $2       # encoding: [0x00,0x41,0x02,0x85]
+  cmpu.le.qb $1, $2            # CHECK: cmpu.le.qb $1, $2       # encoding: [0x00,0x41,0x02,0xc5]

llvm/trunk/test/MC/Mips/micromips-dspr2/invalid.s

 # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dspr2 2>%t1
 # RUN: FileCheck %s < %t1
 
+  balign $2, $3, -1        # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate
+  balign $2, $3, 4         # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate
   shra.qb $3, $4, 8        # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
   shra.qb $3, $4, -1       # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
   shra_r.qb $3, $4, 8      # CHECK: :[[@LINE]]:21: error: expected 3-bit unsigned immediate
   shra_r.qb $3, $4, -1     # CHECK: :[[@LINE]]:21: error: expected 3-bit unsigned immediate
   shrl.ph $3, $4, 16       # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
   shrl.ph $3, $4, -1       # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
   append $3, $4, 32           # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
   append $3, $4, -1           # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
   mulsa.w.ph $8, $3, $2       # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
   mulsa.w.ph $31, $3, $2      # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
   mulsaq_s.w.ph $8, $3, $2    # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
   mulsaq_s.w.ph $31, $3, $2   # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+                              # bposge32 is microMIPS DSP instruction but it is removed in Release 6
+  bposge32 342                # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

llvm/trunk/test/MC/Mips/micromips-dspr2/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dspr2 | FileCheck %s
   muleu_s.ph.qbr $1, $2, $3    # CHECK: muleu_s.ph.qbr $1, $2, $3  # encoding: [0x00,0x62,0x08,0xd5]
   mulq_rs.ph $1, $2, $3        # CHECK: mulq_rs.ph $1, $2, $3      # encoding: [0x00,0x62,0x09,0x15]
   prepend $1, $2, 3            # CHECK: prepend $1, $2, 3          # encoding: [0x00,0x22,0x1a,0x55]
   wrdsp $5                     # CHECK: wrdsp $5                # encoding: [0x00,0xa7,0xd6,0x7c]
   wrdsp $5, 2                  # CHECK: wrdsp $5, 2             # encoding: [0x00,0xa0,0x96,0x7c]
   wrdsp $5, 31                 # CHECK: wrdsp $5                # encoding: [0x00,0xa7,0xd6,0x7c]
   append $3, $4, 5             # CHECK: append $3, $4, 5           # encoding: [0x00,0x64,0x2a,0x15]
   mulsa.w.ph $ac0, $3, $2      # CHECK: mulsa.w.ph $ac0, $3, $2    # encoding: [0x00,0x43,0x2c,0xbc]
+  balign $2, $3, 3             # CHECK: balign $2, $3, 3        # encoding: [0x00,0x43,0xc8,0xbc]
+  bitrev $2, $3                # CHECK: bitrev $2, $3           # encoding: [0x00,0x43,0x31,0x3c]
+  cmp.eq.ph $2, $3             # CHECK: cmp.eq.ph $2, $3        # encoding: [0x00,0x62,0x00,0x05]
+  cmp.le.ph $2, $3             # CHECK: cmp.le.ph $2, $3        # encoding: [0x00,0x62,0x00,0x85]
+  cmp.lt.ph $2, $3             # CHECK: cmp.lt.ph $2, $3        # encoding: [0x00,0x62,0x00,0x45]
+  cmpgdu.eq.qb $1, $2, $3      # CHECK: cmpgdu.eq.qb $1, $2, $3 # encoding: [0x00,0x62,0x09,0x85]
+  cmpgdu.lt.qb $1, $2, $3      # CHECK: cmpgdu.lt.qb $1, $2, $3 # encoding: [0x00,0x62,0x09,0xc5]
+  cmpgdu.le.qb $1, $2, $3      # CHECK: cmpgdu.le.qb $1, $2, $3 # encoding: [0x00,0x62,0x0a,0x05]
+  cmpgu.eq.qb $1, $2, $3       # CHECK: cmpgu.eq.qb $1, $2, $3  # encoding: [0x58,0x62,0x08,0xc5]
+  cmpgu.lt.qb $1, $2, $3       # CHECK: cmpgu.lt.qb $1, $2, $3  # encoding: [0x58,0x62,0x09,0x05]
+  cmpgu.le.qb $1, $2, $3       # CHECK: cmpgu.le.qb $1, $2, $3  # encoding: [0x58,0x62,0x09,0x45]
+  cmpu.eq.qb $1, $2            # CHECK: cmpu.eq.qb $1, $2       # encoding: [0x00,0x41,0x02,0x45]
+  cmpu.lt.qb $1, $2            # CHECK: cmpu.lt.qb $1, $2       # encoding: [0x00,0x41,0x02,0x85]
+  cmpu.le.qb $1, $2            # CHECK: cmpu.le.qb $1, $2       # encoding: [0x00,0x41,0x02,0xc5]

llvm/trunk/test/MC/Mips/micromips32r6/invalid.s

# RUN: FileCheck %s < %t1
   lwp $31, 8($4)           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
                            # FIXME: This ought to point at the $34 but memory is treated as one operand.
   lwp $16, 8($34)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
   lwp $16, 4096($4)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
   lwp $16, 8($16)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
   swp $31, 8($4)           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swp $16, 8($34)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
   swp $16, 4096($4)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
+                           # bposge32 is microMIPS DSP instruction
+  bposge32 342             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

llvm/trunk/test/MC/Mips/micromips64r6/invalid.s

# RUN: FileCheck %s < %t1
   dsll $3, $4, 64              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
   dsll $3, $4, -1              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
   dsll32 $3, $4, 32            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
   dsll32 $3, $4, -1            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
   dsra $4, $5, 64              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
   dsra $4, $5, -1              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
   dsra32 $4, $5, 32            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
   dsra32 $4, $5, -1            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
+                               # bposge32 is microMIPS DSP instruction
+  bposge32 342                 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled