[mips] Correct operand order in DSP's mthi/mtlo

[dsanders]

Summary

The result register is the second operand as per the other mt* instructions.

[vkalintiris]

LGTM.

lib/Target/Mips/MipsSEInstrInfo.cpp

void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB,
   // to these two instructions:
   //  mtlo $gpr0
   //  mthi $gpr1
 
   DebugLoc DL = I->getDebugLoc();
   const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
   MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc));
   MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc));
-  LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
-  HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
 
   // Add lo/hi registers if the mtlo/hi instructions created have explicit
   // def registers.
   if (HasExplicitDef) {
     unsigned DstReg = I->getOperand(0).getReg();
     unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
     unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
     LoInst.addReg(DstLo, RegState::Define);
     HiInst.addReg(DstHi, RegState::Define);
   }
+
+  LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
+  HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
 }
 
 void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
                                      MachineBasicBlock::iterator I,
                                      unsigned CvtOpc, unsigned MovOpc,
                                      bool IsI64) const {
   const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
   const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);

test/CodeGen/Mips/madd-msub.ll

 
 ; 32-DAG:        sra $[[T0:[0-9]+]], $6, 31
 ; 32-DAG:        mtlo $6
 ; 32-DAG:        [[m:m]]add ${{[45]}}, ${{[45]}}
 ; 32-DAG:        [[m]]fhi $2
 ; 32-DAG:        [[m]]flo $3
 
 ; DSP-DAG:       sra $[[T0:[0-9]+]], $6, 31
-; DSP-DAG:       mtlo $[[AC:ac[0-3]+]], $6
+; DSP-DAG:       mtlo $6, $[[AC:ac[0-3]+]]
 ; DSP-DAG:       madd $[[AC]], ${{[45]}}, ${{[45]}}
 ; DSP-DAG:       mfhi $2, $[[AC]]
 ; DSP-DAG:       mflo $3, $[[AC]]
 
 ; 32R6-DAG:      mul  $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
 ; 32R6-DAG:      addu $[[T1:[0-9]+]], $[[T0]], $6
 ; 32R6-DAG:      sltu $[[T2:[0-9]+]], $[[T1]], $6
 ; 32R6-DAG:      sra  $[[T3:[0-9]+]], $6, 31

 ; FIXME: We don't really need this instruction
 ; 32-DAG:        addiu $[[T0:[0-9]+]], $zero, 0
 ; 32-DAG:        mtlo $6
 ; 32-DAG:        [[m:m]]addu ${{[45]}}, ${{[45]}}
 ; 32-DAG:        [[m]]fhi $2
 ; 32-DAG:        [[m]]flo $3
 
 ; DSP-DAG:       addiu $[[T0:[0-9]+]], $zero, 0
-; DSP-DAG:       mtlo $[[AC:ac[0-3]+]], $6
+; DSP-DAG:       mtlo $6, $[[AC:ac[0-3]+]]
 ; DSP-DAG:       maddu $[[AC]], ${{[45]}}, ${{[45]}}
 ; DSP-DAG:       mfhi $2, $[[AC]]
 ; DSP-DAG:       mflo $3, $[[AC]]
 
 ; 32R6-DAG:      mul  $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
 ; 32R6-DAG:      addu $[[T1:[0-9]+]], $[[T0]], $6
 ; 32R6-DAG:      sltu $[[T2:[0-9]+]], $[[T1]], $6
 ; FIXME: There's a redundant move here. We should remove it

 ; ALL-LABEL: madd3:
 
 ; 32-DAG:        mthi $6
 ; 32-DAG:        mtlo $7
 ; 32-DAG:        [[m:m]]add ${{[45]}}, ${{[45]}}
 ; 32-DAG:        [[m]]fhi $2
 ; 32-DAG:        [[m]]flo $3
 
-; DSP-DAG:       mthi $[[AC:ac[0-3]+]], $6
-; DSP-DAG:       mtlo $[[AC]], $7
+; DSP-DAG:       mthi $6, $[[AC:ac[0-3]+]]
+; DSP-DAG:       mtlo $7, $[[AC]]
 ; DSP-DAG:       madd $[[AC]], ${{[45]}}, ${{[45]}}
 ; DSP-DAG:       mfhi $2, $[[AC]]
 ; DSP-DAG:       mflo $3, $[[AC]]
 
 ; 32R6-DAG:      mul  $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
 ; 32R6-DAG:      addu $[[T1:[0-9]+]], $[[T0]], $7
 ; 32R6-DAG:      sltu $[[T2:[0-9]+]], $[[T1]], $7
 ; 32R6-DAG:      addu $[[T4:[0-9]+]], $[[T2]], $6

 
 ; 32-DAG:        sra $[[T0:[0-9]+]], $6, 31
 ; 32-DAG:        mtlo $6
 ; 32-DAG:        [[m:m]]sub ${{[45]}}, ${{[45]}}
 ; 32-DAG:        [[m]]fhi $2
 ; 32-DAG:        [[m]]flo $3
 
 ; DSP-DAG:       sra $[[T0:[0-9]+]], $6, 31
-; DSP-DAG:       mtlo $[[AC:ac[0-3]+]], $6
+; DSP-DAG:       mtlo $6, $[[AC:ac[0-3]+]]
 ; DSP-DAG:       msub $[[AC]], ${{[45]}}, ${{[45]}}
 ; DSP-DAG:       mfhi $2, $[[AC]]
 ; DSP-DAG:       mflo $3, $[[AC]]
 
 ; 32R6-DAG:      muh  $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
 ; 32R6-DAG:      mul  $[[T1:[0-9]+]], ${{[45]}}, ${{[45]}}
 ; 32R6-DAG:      sltu $[[T3:[0-9]+]], $6, $[[T1]]
 ; 32R6-DAG:      addu $[[T4:[0-9]+]], $[[T3]], $[[T0]]

 ; FIXME: We don't really need this instruction
 ; 32-DAG:        addiu $[[T0:[0-9]+]], $zero, 0
 ; 32-DAG:        mtlo $6
 ; 32-DAG:        [[m:m]]subu ${{[45]}}, ${{[45]}}
 ; 32-DAG:        [[m]]fhi $2
 ; 32-DAG:        [[m]]flo $3
 
 ; DSP-DAG:       addiu $[[T0:[0-9]+]], $zero, 0
-; DSP-DAG:       mtlo $[[AC:ac[0-3]+]], $6
+; DSP-DAG:       mtlo $6, $[[AC:ac[0-3]+]]
 ; DSP-DAG:       msubu $[[AC]], ${{[45]}}, ${{[45]}}
 ; DSP-DAG:       mfhi $2, $[[AC]]
 ; DSP-DAG:       mflo $3, $[[AC]]
 
 ; 32R6-DAG:      muhu $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
 ; 32R6-DAG:      mul $[[T1:[0-9]+]], ${{[45]}}, ${{[45]}}
 
 ; 32R6-DAG:      sltu $[[T2:[0-9]+]], $6, $[[T1]]

 ; FIXME: We don't really need this instruction
 ; 32-DAG:        mthi $6
 ; 32-DAG:        mtlo $7
 ; 32-DAG:        [[m:m]]sub ${{[45]}}, ${{[45]}}
 ; 32-DAG:        [[m]]fhi $2
 ; 32-DAG:        [[m]]flo $3
 
 ; DSP-DAG:       addiu $[[T0:[0-9]+]], $zero, 0
-; DSP-DAG:       mtlo $[[AC:ac[0-3]+]], $6
+; DSP-DAG:       mtlo $6, $[[AC:ac[0-3]+]]
 ; DSP-DAG:       msub $[[AC]], ${{[45]}}, ${{[45]}}
 ; DSP-DAG:       mfhi $2, $[[AC]]
 ; DSP-DAG:       mflo $3, $[[AC]]
 
 ; 32R6-DAG:      muh $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
 ; 32R6-DAG:      mul $[[T1:[0-9]+]], ${{[45]}}, ${{[45]}}
 ; 32R6-DAG:      sltu $[[T2:[0-9]+]], $7, $[[T1]]
 ; 32R6-DAG:      addu $[[T3:[0-9]+]], $[[T2]], $[[T0]]