[WebAssembly] Support constant offsets on loads and stores

[dschuff]

Summary

Includes the syntax for the immediate offset field of load and store instructions, but doesn't pattern-match anything other than 0 yet.

[dschuff]

lib/Target/WebAssembly/WebAssemblyInstrMemory.td

106 ↗

(On Diff #41776)

writing the offset operand as 'imm:$off' turns out to be critical here to getting an immediate in the output. If you say just $off or I32:$off you still get a pattern match but it generates an i32.const and uses that instead of putting it directly as an immediate in the store instruction. (The same applies if you use this kind of pattern to match a load, but if you put it directly in the definition for the load as I did here, then it doesn't matter if you use the imm: prefix or not). I'm not sure why that is.

[sunfish]

This looks like a good direction. I like how it uses def : Pat instead of needing custom code in WebAssemblyISelDAGToDAG.cpp :-).

One tricky thing though is that wasm's constant offsets are unsigned, so we can't support negative values. I think we'll need to add a predicate on the pattern-match which checks this. I think it's fine if you'd prefer to just add a FIXME for this for now and we can address it later though. Or if you want to simplify things, we could also defer pattern-matching for constant offsets altogether for now, since framepointer lowering doesn't actually require it.

lib/Target/WebAssembly/WebAssemblyInstrMemory.td

106 ↗

(On Diff #41776)

If you say I32:$off, it refers to the I32 register class (defined in lib/Target/WebAssembly/WebAssemblyRegisterInfo.td), which effectively says that you need the value in a register of that class, which forces the instruction selector to use an i32.const to get the value into a register. I don't know the rules if you just say $off by itself. I'd suggest using the imm: prefix to avoid trouble :-).

[jfb]

In D15197#301756, @sunfish wrote:

This looks like a good direction. I like how it uses def : Pat instead of needing custom code in WebAssemblyISelDAGToDAG.cpp :-).

Agreed.

One tricky thing though is that wasm's constant offsets are unsigned, so we can't support negative values. I think we'll need to add a predicate on the pattern-match which checks this.

We'll also want to optimize things so that LLVM knows to generate positive offsets instead of negative ones (post-increment as much as possible). Do you know if there's a knob for that? It's just an optimization so maybe just mention it in the list of work to do in the README?

and we can address it later though.

I see what you did there, "address". :o)

[sunfish]

We'll also want to optimize things so that LLVM knows to generate positive offsets instead of negative ones (post-increment as much as possible). Do you know if there's a knob for that? It's just an optimization so maybe just mention it in the list of work to do in the README?

The main hook we can use is WebAssemblyTargetLowering::isLegalAddressingMode, and there's a TODO for it in WebAssemblyInstrMemory.md.

[dschuff]

• Include all loads and stores
• rebase

[dschuff]

Updated to include all loads and stores, and remove the pattern match for now.
I couldn't figure out a way to constrain the match for unsigned immediates with just tablegen yet.

[sunfish]

Sounds good to me.

llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrMemory.td

 
 // WebAssembly has i8/i16/i32/i64/f32/f64 memory types, but doesn't have i8/i16
 // local types. These memory-only types instead zero- or sign-extend into local
 // types when loading, and truncate when storing.
 
 let Defs = [ARGUMENTS] in {
 
 // Basic load.
-def LOAD_I32 : I<(outs I32:$dst), (ins I32:$addr),
-                 [(set I32:$dst, (load I32:$addr))],
-                 "i32.load\t$dst, $addr">;
-def LOAD_I64 : I<(outs I64:$dst), (ins I32:$addr),
-                 [(set I64:$dst, (load I32:$addr))],
-                 "i64.load\t$dst, $addr">;
-def LOAD_F32 : I<(outs F32:$dst), (ins I32:$addr),
-                 [(set F32:$dst, (load I32:$addr))],
-                 "f32.load\t$dst, $addr">;
-def LOAD_F64 : I<(outs F64:$dst), (ins I32:$addr),
-                 [(set F64:$dst, (load I32:$addr))],
-                 "f64.load\t$dst, $addr">;
+def LOAD_I32 : I<(outs I32:$dst), (ins I32:$off, I32:$addr), [],
+                 "i32.load\t$dst, $off($addr)">;
+def LOAD_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [],
+                 "i64.load\t$dst, $off($addr)">;
+def LOAD_F32 : I<(outs F32:$dst), (ins I32:$off, I32:$addr), [],
+                 "f32.load\t$dst, $off($addr)">;
+def LOAD_F64 : I<(outs F64:$dst), (ins I32:$off, I32:$addr), [],
+                 "f64.load\t$dst, $off($addr)">;
 
 // Extending load.
-def LOAD8_S_I32  : I<(outs I32:$dst), (ins I32:$addr),
-                     [(set I32:$dst, (sextloadi8 I32:$addr))],
-                     "i32.load8_s\t$dst, $addr">;
-def LOAD8_U_I32  : I<(outs I32:$dst), (ins I32:$addr),
-                     [(set I32:$dst, (zextloadi8 I32:$addr))],
-                     "i32.load8_u\t$dst, $addr">;
-def LOAD16_S_I32 : I<(outs I32:$dst), (ins I32:$addr),
-                     [(set I32:$dst, (sextloadi16 I32:$addr))],
-                     "i32.load16_s\t$dst, $addr">;
-def LOAD16_U_I32 : I<(outs I32:$dst), (ins I32:$addr),
-                     [(set I32:$dst, (zextloadi16 I32:$addr))],
-                     "i32.load16_u\t$dst, $addr">;
-def LOAD8_S_I64  : I<(outs I64:$dst), (ins I32:$addr),
-                     [(set I64:$dst, (sextloadi8 I32:$addr))],
-                     "i64.load8_s\t$dst, $addr">;
-def LOAD8_U_I64  : I<(outs I64:$dst), (ins I32:$addr),
-                     [(set I64:$dst, (zextloadi8 I32:$addr))],
-                     "i64.load8_u\t$dst, $addr">;
-def LOAD16_S_I64 : I<(outs I64:$dst), (ins I32:$addr),
-                     [(set I64:$dst, (sextloadi16 I32:$addr))],
-                     "i64.load16_s\t$dst, $addr">;
-def LOAD16_U_I64 : I<(outs I64:$dst), (ins I32:$addr),
-                     [(set I64:$dst, (zextloadi16 I32:$addr))],
-                     "i64.load16_u\t$dst, $addr">;
-def LOAD32_S_I64 : I<(outs I64:$dst), (ins I32:$addr),
-                     [(set I64:$dst, (sextloadi32 I32:$addr))],
-                     "i64.load32_s\t$dst, $addr">;
-def LOAD32_U_I64 : I<(outs I64:$dst), (ins I32:$addr),
-                     [(set I64:$dst, (zextloadi32 I32:$addr))],
-                     "i64.load32_u\t$dst, $addr">;
+def LOAD8_S_I32  : I<(outs I32:$dst), (ins I32:$off, I32:$addr), [],
+                     "i32.load8_s\t$dst, $off($addr)">;
+def LOAD8_U_I32  : I<(outs I32:$dst), (ins I32:$off, I32:$addr), [],
+                     "i32.load8_u\t$dst, $off($addr)">;
+def LOAD16_S_I32 : I<(outs I32:$dst), (ins I32:$off, I32:$addr), [],
+                     "i32.load16_s\t$dst, $off($addr)">;
+def LOAD16_U_I32 : I<(outs I32:$dst), (ins I32:$off, I32:$addr), [],
+                     "i32.load16_u\t$dst, $off($addr)">;
+def LOAD8_S_I64  : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [],
+                     "i64.load8_s\t$dst, $off($addr)">;
+def LOAD8_U_I64  : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [],
+                     "i64.load8_u\t$dst, $off($addr)">;
+def LOAD16_S_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [],
+                     "i64.load16_s\t$dst, $off($addr)">;
+def LOAD16_U_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [],
+                     "i64.load16_u\t$dst, $off($addr)">;
+def LOAD32_S_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [],
+                     "i64.load32_s\t$dst, $off($addr)">;
+def LOAD32_U_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr), [],
+                     "i64.load32_u\t$dst, $off($addr)">;
 
 } // Defs = [ARGUMENTS]
 
+// Select loads with no constant offset.
+def : Pat<(i32 (load I32:$addr)), (LOAD_I32 0, $addr)>;
+def : Pat<(i64 (load I32:$addr)), (LOAD_I64 0, $addr)>;
+def : Pat<(f32 (load I32:$addr)), (LOAD_F32 0, $addr)>;
+def : Pat<(f64 (load I32:$addr)), (LOAD_F64 0, $addr)>;
+
+// Select extending loads with no constant offset.
+def : Pat<(i32 (sextloadi8 I32:$addr)), (LOAD8_S_I32 0, $addr)>;
+def : Pat<(i32 (zextloadi8 I32:$addr)), (LOAD8_U_I32 0, $addr)>;
+def : Pat<(i32 (sextloadi16 I32:$addr)), (LOAD16_S_I32 0, $addr)>;
+def : Pat<(i32 (zextloadi16 I32:$addr)), (LOAD16_U_I32 0, $addr)>;
+def : Pat<(i64 (sextloadi8 I32:$addr)), (LOAD8_S_I64 0, $addr)>;
+def : Pat<(i64 (zextloadi8 I32:$addr)), (LOAD8_U_I64 0, $addr)>;
+def : Pat<(i64 (sextloadi16 I32:$addr)), (LOAD16_S_I64 0, $addr)>;
+def : Pat<(i64 (zextloadi16 I32:$addr)), (LOAD16_U_I64 0, $addr)>;
+def : Pat<(i64 (sextloadi32 I32:$addr)), (LOAD32_S_I64 0, $addr)>;
+def : Pat<(i64 (zextloadi32 I32:$addr)), (LOAD32_U_I64 0, $addr)>;
+
 // "Don't care" extending load become zero-extending load.
-def : Pat<(i32 (extloadi8 I32:$addr)),  (LOAD8_U_I32 $addr)>;
-def : Pat<(i32 (extloadi16 I32:$addr)), (LOAD16_U_I32 $addr)>;
-def : Pat<(i64 (extloadi8 I32:$addr)),  (LOAD8_U_I64 $addr)>;
-def : Pat<(i64 (extloadi16 I32:$addr)), (LOAD16_U_I64 $addr)>;
-def : Pat<(i64 (extloadi32 I32:$addr)), (LOAD32_U_I64 $addr)>;
+def : Pat<(i32 (extloadi8 I32:$addr)),  (LOAD8_U_I32 0, $addr)>;
+def : Pat<(i32 (extloadi16 I32:$addr)), (LOAD16_U_I32 0, $addr)>;
+def : Pat<(i64 (extloadi8 I32:$addr)),  (LOAD8_U_I64 0, $addr)>;
+def : Pat<(i64 (extloadi16 I32:$addr)), (LOAD16_U_I64 0, $addr)>;
+def : Pat<(i64 (extloadi32 I32:$addr)), (LOAD32_U_I64 0, $addr)>;
 
 let Defs = [ARGUMENTS] in {
 
 // Basic store.
 // Note that we split the patterns out of the instruction definitions because
 // WebAssembly's stores return their operand value, and tablegen doesn't like
 // instruction definition patterns that don't reference all of the output
 // operands.
 // Note: WebAssembly inverts SelectionDAG's usual operand order.
-def STORE_I32  : I<(outs I32:$dst), (ins I32:$addr, I32:$val), [],
-                   "i32.store\t$dst, $addr, $val">;
-def STORE_I64  : I<(outs I64:$dst), (ins I32:$addr, I64:$val), [],
-                   "i64.store\t$dst, $addr, $val">;
-def STORE_F32  : I<(outs F32:$dst), (ins I32:$addr, F32:$val), [],
-                   "f32.store\t$dst, $addr, $val">;
-def STORE_F64  : I<(outs F64:$dst), (ins I32:$addr, F64:$val), [],
-                   "f64.store\t$dst, $addr, $val">;
+def STORE_I32  : I<(outs I32:$dst), (ins I32:$off, I32:$addr, I32:$val), [],
+                   "i32.store\t$dst, $off($addr), $val">;
+def STORE_I64  : I<(outs I64:$dst), (ins I32:$off, I32:$addr, I64:$val), [],
+                   "i64.store\t$dst, $off($addr), $val">;
+def STORE_F32  : I<(outs F32:$dst), (ins I32:$off, I32:$addr, F32:$val), [],
+                   "f32.store\t$dst, $off($addr), $val">;
+def STORE_F64  : I<(outs F64:$dst), (ins I32:$off, I32:$addr, F64:$val), [],
+                   "f64.store\t$dst, $off($addr), $val">;
 
 } // Defs = [ARGUMENTS]
 
-def : Pat<(store I32:$val, I32:$addr), (STORE_I32 I32:$addr, I32:$val)>;
-def : Pat<(store I64:$val, I32:$addr), (STORE_I64 I32:$addr, I64:$val)>;
-def : Pat<(store F32:$val, I32:$addr), (STORE_F32 I32:$addr, F32:$val)>;
-def : Pat<(store F64:$val, I32:$addr), (STORE_F64 I32:$addr, F64:$val)>;
+def : Pat<(store I32:$val, I32:$addr), (STORE_I32 0, I32:$addr, I32:$val)>;
+def : Pat<(store I64:$val, I32:$addr), (STORE_I64 0, I32:$addr, I64:$val)>;
+def : Pat<(store F32:$val, I32:$addr), (STORE_F32 0, I32:$addr, F32:$val)>;
+def : Pat<(store F64:$val, I32:$addr), (STORE_F64 0, I32:$addr, F64:$val)>;
+
+// FIXME: This pattern matches an immediate to actually use the offset field
+// in the store instruction; however only unsigned offsets are supported in
+// wasm, so we need to constrain the immediate we match. This may require
+// custom code rather than a simple pattern.
+// def : Pat<(store I32:$val, (add I32:$addr, (i32 imm:$off))),
+//           (STORE_I32 imm:$off, I32:$addr, I32:$val)>;
 
 let Defs = [ARGUMENTS] in {
 
 // Truncating store.
-def STORE8_I32  : I<(outs I32:$dst), (ins I32:$addr, I32:$val), [],
-                    "i32.store8\t$dst, $addr, $val">;
-def STORE16_I32 : I<(outs I32:$dst), (ins I32:$addr, I32:$val), [],
-                    "i32.store16\t$dst, $addr, $val">;
-def STORE8_I64  : I<(outs I64:$dst), (ins I32:$addr, I64:$val), [],
-                    "i64.store8\t$dst, $addr, $val">;
-def STORE16_I64 : I<(outs I64:$dst), (ins I32:$addr, I64:$val), [],
-                    "i64.store16\t$dst, $addr, $val">;
-def STORE32_I64 : I<(outs I64:$dst), (ins I32:$addr, I64:$val), [],
-                    "i64.store32\t$dst, $addr, $val">;
+def STORE8_I32  : I<(outs I32:$dst), (ins I32:$off, I32:$addr, I32:$val), [],
+                    "i32.store8\t$dst, $off($addr), $val">;
+def STORE16_I32 : I<(outs I32:$dst), (ins I32:$off, I32:$addr, I32:$val), [],
+                    "i32.store16\t$dst, $off($addr), $val">;
+def STORE8_I64  : I<(outs I64:$dst), (ins I32:$off, I32:$addr, I64:$val), [],
+                    "i64.store8\t$dst, $off($addr), $val">;
+def STORE16_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr, I64:$val), [],
+                    "i64.store16\t$dst, $off($addr), $val">;
+def STORE32_I64 : I<(outs I64:$dst), (ins I32:$off, I32:$addr, I64:$val), [],
+                    "i64.store32\t$dst, $off($addr), $val">;
 
 } // Defs = [ARGUMENTS]
 
 def : Pat<(truncstorei8 I32:$val, I32:$addr),
-          (STORE8_I32 I32:$addr, I32:$val)>;
+          (STORE8_I32 0, I32:$addr, I32:$val)>;
 def : Pat<(truncstorei16 I32:$val, I32:$addr),
-          (STORE16_I32 I32:$addr, I32:$val)>;
+          (STORE16_I32 0, I32:$addr, I32:$val)>;
 def : Pat<(truncstorei8 I64:$val, I32:$addr),
-          (STORE8_I64 I32:$addr, I64:$val)>;
+          (STORE8_I64 0, I32:$addr, I64:$val)>;
 def : Pat<(truncstorei16 I64:$val, I32:$addr),
-          (STORE16_I64 I32:$addr, I64:$val)>;
+          (STORE16_I64 0, I32:$addr, I64:$val)>;
 def : Pat<(truncstorei32 I64:$val, I32:$addr),
-          (STORE32_I64 I32:$addr, I64:$val)>;
+          (STORE32_I64 0, I32:$addr, I64:$val)>;
 
 let Defs = [ARGUMENTS] in {
 
 // Memory size.
 def MEMORY_SIZE_I32 : I<(outs I32:$dst), (ins),
                         [(set I32:$dst, (int_wasm_memory_size))],
                         "memory_size\t$dst">,
                       Requires<[HasAddr32]>;

llvm/trunk/lib/Target/WebAssembly/WebAssemblyStoreResults.cpp

for (auto &MI : MBB)
       case WebAssembly::STORE8_I64:
       case WebAssembly::STORE16_I64:
       case WebAssembly::STORE32_I64:
       case WebAssembly::STORE_F32:
       case WebAssembly::STORE_F64:
       case WebAssembly::STORE_I32:
       case WebAssembly::STORE_I64:
         unsigned ToReg = MI.getOperand(0).getReg();
-        unsigned FromReg = MI.getOperand(2).getReg();
+        unsigned FromReg = MI.getOperand(3).getReg();
         for (auto I = MRI.use_begin(FromReg), E = MRI.use_end(); I != E;) {
           MachineOperand &O = *I++;
           MachineInstr *Where = O.getParent();
           if (Where->getOpcode() == TargetOpcode::PHI) {
             // PHIs use their operands on their incoming CFG edges rather than
             // in their parent blocks. Get the basic block paired with this use
             // of FromReg and check that MI's block dominates it.
             MachineBasicBlock *Pred =

llvm/trunk/test/CodeGen/WebAssembly/cfg-stackify.ll

 entry:
   store volatile i32 0, i32* %p
   ret i32 0
 }
 
 ; CHECK-LABEL: minimal_loop:
 ; CHECK-NOT: br
 ; CHECK: BB7_1:
-; CHECK: i32.store $discard=, $0, $pop{{[0-9]+}}{{$}}
+; CHECK: i32.store $discard=, 0($0), $pop{{[0-9]+}}{{$}}
 ; CHECK: br BB7_1{{$}}
 ; CHECK: BB7_2:
 define i32 @minimal_loop(i32* %p) {
 entry:
   store volatile i32 0, i32* %p
   br label %loop
 loop:
   store volatile i32 1, i32* %p

llvm/trunk/test/CodeGen/WebAssembly/global.ll

 ; RUN: llc < %s -asm-verbose=false | FileCheck %s
 
 ; Test that globals assemble as expected.
 
 target datalayout = "e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-NOT: llvm.used
 ; CHECK-NOT: llvm.metadata
 @llvm.used = appending global [1 x i32*] [i32* @g], section "llvm.metadata"
 
 ; CHECK: foo:
 ; CHECK: i32.const $push0=, answer{{$}}
-; CHECK-NEXT: i32.load $push1=, $pop0{{$}}
+; CHECK-NEXT: i32.load $push1=, 0($pop0){{$}}
 ; CHECK-NEXT: return $pop1{{$}}
 define i32 @foo() {
   %a = load i32, i32* @answer
   ret i32 %a
 }
 
 ; CHECK-LABEL: call_memcpy:
 ; CHECK-NEXT: .param          i32, i32, i32{{$}}

llvm/trunk/test/CodeGen/WebAssembly/load-ext.ll

 ; RUN: llc < %s -asm-verbose=false | FileCheck %s
 
 ; Test that extending loads are assembled properly.
 
 target datalayout = "e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: sext_i8_i32:
-; CHECK: i32.load8_s $push0=, $0{{$}}
+; CHECK: i32.load8_s $push0=, 0($0){{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @sext_i8_i32(i8 *%p) {
   %v = load i8, i8* %p
   %e = sext i8 %v to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: zext_i8_i32:
-; CHECK: i32.load8_u $push0=, $0{{$}}
+; CHECK: i32.load8_u $push0=, 0($0){{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @zext_i8_i32(i8 *%p) {
   %v = load i8, i8* %p
   %e = zext i8 %v to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: sext_i16_i32:
-; CHECK: i32.load16_s $push0=, $0{{$}}
+; CHECK: i32.load16_s $push0=, 0($0){{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @sext_i16_i32(i16 *%p) {
   %v = load i16, i16* %p
   %e = sext i16 %v to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: zext_i16_i32:
-; CHECK: i32.load16_u $push0=, $0{{$}}
+; CHECK: i32.load16_u $push0=, 0($0){{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i32 @zext_i16_i32(i16 *%p) {
   %v = load i16, i16* %p
   %e = zext i16 %v to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: sext_i8_i64:
-; CHECK: i64.load8_s $push0=, $0{{$}}
+; CHECK: i64.load8_s $push0=, 0($0){{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @sext_i8_i64(i8 *%p) {
   %v = load i8, i8* %p
   %e = sext i8 %v to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: zext_i8_i64:
-; CHECK: i64.load8_u $push0=, $0{{$}}
+; CHECK: i64.load8_u $push0=, 0($0){{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @zext_i8_i64(i8 *%p) {
   %v = load i8, i8* %p
   %e = zext i8 %v to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: sext_i16_i64:
-; CHECK: i64.load16_s $push0=, $0{{$}}
+; CHECK: i64.load16_s $push0=, 0($0){{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @sext_i16_i64(i16 *%p) {
   %v = load i16, i16* %p
   %e = sext i16 %v to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: zext_i16_i64:
-; CHECK: i64.load16_u $push0=, $0{{$}}
+; CHECK: i64.load16_u $push0=, 0($0){{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @zext_i16_i64(i16 *%p) {
   %v = load i16, i16* %p
   %e = zext i16 %v to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: sext_i32_i64:
-; CHECK: i64.load32_s $push0=, $0{{$}}
+; CHECK: i64.load32_s $push0=, 0($0){{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @sext_i32_i64(i32 *%p) {
   %v = load i32, i32* %p
   %e = sext i32 %v to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: zext_i32_i64:
-; CHECK: i64.load32_u $push0=, $0{{$}}
+; CHECK: i64.load32_u $push0=, 0($0){{$}}
 ; CHECK: return $pop0{{$}}
 define i64 @zext_i32_i64(i32 *%p) {
   %v = load i32, i32* %p
   %e = zext i32 %v to i64
   ret i64 %e
 }

llvm/trunk/test/CodeGen/WebAssembly/load-store-i1.ll

 ; RUN: llc < %s -asm-verbose=false | FileCheck %s
 
 ; Test that i1 extending loads and truncating stores are assembled properly.
 
 target datalayout = "e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: load_u_i1_i32:
-; CHECK:      i32.load8_u $push[[NUM0:[0-9]+]]=, $0{{$}}
+; CHECK:      i32.load8_u $push[[NUM0:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[NUM0]]{{$}}
 define i32 @load_u_i1_i32(i1* %p) {
   %v = load i1, i1* %p
   %e = zext i1 %v to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: load_s_i1_i32:
-; CHECK:      i32.load8_u $push[[NUM0:[0-9]+]]=, $0{{$}}
+; CHECK:      i32.load8_u $push[[NUM0:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: i32.const $[[NUM1:[0-9]+]]=, 31{{$}}
 ; CHECK-NEXT: shl $push[[NUM2:[0-9]+]]=, $pop[[NUM0]], $[[NUM1]]{{$}}
 ; CHECK-NEXT: shr_s $push[[NUM3:[0-9]+]]=, $pop[[NUM2]], $[[NUM1]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM3]]{{$}}
 define i32 @load_s_i1_i32(i1* %p) {
   %v = load i1, i1* %p
   %e = sext i1 %v to i32
   ret i32 %e
 }
 
 ; CHECK-LABEL: load_u_i1_i64:
-; CHECK:      i64.load8_u $push[[NUM0:[0-9]+]]=, $0{{$}}
+; CHECK:      i64.load8_u $push[[NUM0:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[NUM0]]{{$}}
 define i64 @load_u_i1_i64(i1* %p) {
   %v = load i1, i1* %p
   %e = zext i1 %v to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: load_s_i1_i64:
-; CHECK:      i64.load8_u $push[[NUM0:[0-9]+]]=, $0{{$}}
+; CHECK:      i64.load8_u $push[[NUM0:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: i64.const $[[NUM1:[0-9]+]]=, 63{{$}}
 ; CHECK-NEXT: shl $push[[NUM2:[0-9]+]]=, $pop[[NUM0]], $[[NUM1]]{{$}}
 ; CHECK-NEXT: shr_s $push[[NUM3:[0-9]+]]=, $pop[[NUM2]], $[[NUM1]]{{$}}
 ; CHECK-NEXT: return $pop[[NUM3]]{{$}}
 define i64 @load_s_i1_i64(i1* %p) {
   %v = load i1, i1* %p
   %e = sext i1 %v to i64
   ret i64 %e
 }
 
 ; CHECK-LABEL: store_i32_i1:
 ; CHECK:      i32.const $push[[NUM0:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i32.and $push[[NUM1:[0-9]+]]=, $1, $pop[[NUM0]]{{$}}
-; CHECK-NEXT: i32.store8 $discard=, $0, $pop[[NUM1]]{{$}}
+; CHECK-NEXT: i32.store8 $discard=, 0($0), $pop[[NUM1]]{{$}}
 define void @store_i32_i1(i1* %p, i32 %v) {
   %t = trunc i32 %v to i1
   store i1 %t, i1* %p
   ret void
 }
 
 ; CHECK-LABEL: store_i64_i1:
 ; CHECK:      i64.const $push[[NUM0:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i64.and $push[[NUM1:[0-9]+]]=, $1, $pop[[NUM0]]{{$}}
-; CHECK-NEXT: i64.store8 $discard=, $0, $pop[[NUM1]]{{$}}
+; CHECK-NEXT: i64.store8 $discard=, 0($0), $pop[[NUM1]]{{$}}
 define void @store_i64_i1(i1* %p, i64 %v) {
   %t = trunc i64 %v to i1
   store i1 %t, i1* %p
   ret void
 }

llvm/trunk/test/CodeGen/WebAssembly/load.ll

 ; RUN: llc < %s -asm-verbose=false | FileCheck %s
 
 ; Test that basic loads are assembled properly.
 
 target datalayout = "e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: ldi32:
 ; CHECK-NEXT: .param i32{{$}}
 ; CHECK-NEXT: .result i32{{$}}
-; CHECK-NEXT: i32.load $push[[NUM:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: i32.load $push[[NUM:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i32 @ldi32(i32 *%p) {
   %v = load i32, i32* %p
   ret i32 %v
 }
 
 ; CHECK-LABEL: ldi64:
 ; CHECK-NEXT: .param i32{{$}}
 ; CHECK-NEXT: .result i64{{$}}
-; CHECK-NEXT: i64.load $push[[NUM:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: i64.load $push[[NUM:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define i64 @ldi64(i64 *%p) {
   %v = load i64, i64* %p
   ret i64 %v
 }
 
 ; CHECK-LABEL: ldf32:
 ; CHECK-NEXT: .param i32{{$}}
 ; CHECK-NEXT: .result f32{{$}}
-; CHECK-NEXT: f32.load $push[[NUM:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: f32.load $push[[NUM:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define float @ldf32(float *%p) {
   %v = load float, float* %p
   ret float %v
 }
 
 ; CHECK-LABEL: ldf64:
 ; CHECK-NEXT: .param i32{{$}}
 ; CHECK-NEXT: .result f64{{$}}
-; CHECK-NEXT: f64.load $push[[NUM:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: f64.load $push[[NUM:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define double @ldf64(double *%p) {
   %v = load double, double* %p
   ret double %v
 }

llvm/trunk/test/CodeGen/WebAssembly/store-results.ll

 ; RUN: llc < %s -asm-verbose=false | FileCheck %s
 
 ; Test that the wasm-store-results pass makes users of stored values use the
 ; result of store expressions to reduce get_local/set_local traffic.
 
 target datalayout = "e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: single_block:
 ; CHECK-NOT: .local
 ; CHECK: i32.const $push{{[0-9]+}}=, 0
-; CHECK: i32.store $push[[STORE:[0-9]+]]=, $0, $pop{{[0-9]+}}
+; CHECK: i32.store $push[[STORE:[0-9]+]]=, 0($0), $pop{{[0-9]+}}
 ; CHECK: return $pop[[STORE]]{{$}}
 define i32 @single_block(i32* %p) {
 entry:
   store i32 0, i32* %p
   ret i32 0
 }
 
 ; Test interesting corner cases for wasm-store-results, in which the operand of
 ; a store ends up getting used by a phi, which needs special handling in the
 ; dominance test, since phis use their operands on their incoming edges.
 
 %class.Vec3 = type { float, float, float }
 
 @pos = global %class.Vec3 zeroinitializer, align 4
 
 ; CHECK-LABEL: foo:
-; CHECK: i32.store $discard=, $pop0, $0
+; CHECK: i32.store $discard=, 0($pop0), $0
 define void @foo() {
 for.body.i:
   br label %for.body5.i
 
 for.body5.i:
   %i.0168.i = phi i32 [ 0, %for.body.i ], [ %inc.i, %for.body5.i ]
   %conv6.i = sitofp i32 %i.0168.i to float
   store volatile float 0.0, float* getelementptr inbounds (%class.Vec3, %class.Vec3* @pos, i32 0, i32 0)
   %inc.i = add nuw nsw i32 %i.0168.i, 1
   %exitcond.i = icmp eq i32 %inc.i, 256
   br i1 %exitcond.i, label %for.cond.cleanup4.i, label %for.body5.i
 
 for.cond.cleanup4.i:
   ret void
 }
 
 ; CHECK-LABEL: bar:
-; CHECK: i32.store $discard=, $0, $pop0
+; CHECK: i32.store $discard=, 0($0), $pop0
 define void @bar() {
 for.body.i:
   br label %for.body5.i
 
 for.body5.i:
   %i.0168.i = phi float [ 0.0, %for.body.i ], [ %inc.i, %for.body5.i ]
   store volatile float 0.0, float* getelementptr inbounds (%class.Vec3, %class.Vec3* @pos, i32 0, i32 0)
   %inc.i = fadd float %i.0168.i, 1.0
   %exitcond.i = fcmp oeq float %inc.i, 256.0
   br i1 %exitcond.i, label %for.cond.cleanup4.i, label %for.body5.i
 
 for.cond.cleanup4.i:
   ret void
 }

llvm/trunk/test/CodeGen/WebAssembly/store-trunc.ll

 ; RUN: llc < %s -asm-verbose=false | FileCheck %s
 
 ; Test that truncating stores are assembled properly.
 
 target datalayout = "e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: trunc_i8_i32:
-; CHECK: i32.store8 $discard=, $0, $1{{$}}
+; CHECK: i32.store8 $discard=, 0($0), $1{{$}}
 define void @trunc_i8_i32(i8 *%p, i32 %v) {
   %t = trunc i32 %v to i8
   store i8 %t, i8* %p
   ret void
 }
 
 ; CHECK-LABEL: trunc_i16_i32:
-; CHECK: i32.store16 $discard=, $0, $1{{$}}
+; CHECK: i32.store16 $discard=, 0($0), $1{{$}}
 define void @trunc_i16_i32(i16 *%p, i32 %v) {
   %t = trunc i32 %v to i16
   store i16 %t, i16* %p
   ret void
 }
 
 ; CHECK-LABEL: trunc_i8_i64:
-; CHECK: i64.store8 $discard=, $0, $1{{$}}
+; CHECK: i64.store8 $discard=, 0($0), $1{{$}}
 define void @trunc_i8_i64(i8 *%p, i64 %v) {
   %t = trunc i64 %v to i8
   store i8 %t, i8* %p
   ret void
 }
 
 ; CHECK-LABEL: trunc_i16_i64:
-; CHECK: i64.store16 $discard=, $0, $1{{$}}
+; CHECK: i64.store16 $discard=, 0($0), $1{{$}}
 define void @trunc_i16_i64(i16 *%p, i64 %v) {
   %t = trunc i64 %v to i16
   store i16 %t, i16* %p
   ret void
 }
 
 ; CHECK-LABEL: trunc_i32_i64:
-; CHECK: i64.store32 $discard=, $0, $1{{$}}
+; CHECK: i64.store32 $discard=, 0($0), $1{{$}}
 define void @trunc_i32_i64(i32 *%p, i64 %v) {
   %t = trunc i64 %v to i32
   store i32 %t, i32* %p
   ret void
 }

llvm/trunk/test/CodeGen/WebAssembly/store.ll

 ; RUN: llc < %s -asm-verbose=false | FileCheck %s
 
 ; Test that basic stores are assembled properly.
 
 target datalayout = "e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: sti32:
 ; CHECK-NEXT: .param i32, i32{{$}}
-; CHECK-NEXT: i32.store $discard=, $0, $1{{$}}
+; CHECK-NEXT: i32.store $discard=, 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti32(i32 *%p, i32 %v) {
   store i32 %v, i32* %p
   ret void
 }
 
 ; CHECK-LABEL: sti64:
 ; CHECK-NEXT: .param i32, i64{{$}}
-; CHECK-NEXT: i64.store $discard=, $0, $1{{$}}
+; CHECK-NEXT: i64.store $discard=, 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti64(i64 *%p, i64 %v) {
   store i64 %v, i64* %p
   ret void
 }
 
 ; CHECK-LABEL: stf32:
 ; CHECK-NEXT: .param i32, f32{{$}}
-; CHECK-NEXT: f32.store $discard=, $0, $1{{$}}
+; CHECK-NEXT: f32.store $discard=, 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @stf32(float *%p, float %v) {
   store float %v, float* %p
   ret void
 }
 
 ; CHECK-LABEL: stf64:
 ; CHECK-NEXT: .param i32, f64{{$}}
-; CHECK-NEXT: f64.store $discard=, $0, $1{{$}}
+; CHECK-NEXT: f64.store $discard=, 0($0), $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @stf64(double *%p, double %v) {
   store double %v, double* %p
   ret void
 }

llvm/trunk/test/CodeGen/WebAssembly/varargs.ll

entry:
   call void @llvm.va_end(i8* %0)
   ret void
 }
 
 ; Test va_copy.
 
 ; CHECK-LABEL: copy:
 ; CHECK-NEXT: .param i32, i32{{$}}
-; CHECK-NEXT: i32.load  $push0=, $1{{$}}
-; CHECK-NEXT: i32.store $discard=, $0, $pop0{{$}}
+; CHECK-NEXT: i32.load  $push0=, 0($1){{$}}
+; CHECK-NEXT: i32.store $discard=, 0($0), $pop0{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @copy(i8** %ap, i8** %bp) {
 entry:
   %0 = bitcast i8** %ap to i8*
   %1 = bitcast i8** %bp to i8*
   call void @llvm.va_copy(i8* %0, i8* %1)
   ret void
 }
 
 ; Test va_arg with an i8 argument.
 
 ; CHECK-LABEL: arg_i8:
 ; CHECK-NEXT: .param     i32{{$}}
 ; CHECK-NEXT: .result    i32{{$}}
 ; CHECK-NEXT: .local     i32{{$}}
-; CHECK-NEXT: i32.load   $1=, $0{{$}}
+; CHECK-NEXT: i32.load   $1=, 0($0){{$}}
 ; CHECK-NEXT: i32.const  $push0=, 4{{$}}
 ; CHECK-NEXT: i32.add    $push1=, $1, $pop0{{$}}
-; CHECK-NEXT: i32.store  $discard=, $0, $pop1{{$}}
-; CHECK-NEXT: i32.load   $push2=, $1{{$}}
+; CHECK-NEXT: i32.store  $discard=, 0($0), $pop1{{$}}
+; CHECK-NEXT: i32.load   $push2=, 0($1){{$}}
 ; CHECK-NEXT: return     $pop2{{$}}
 define i8 @arg_i8(i8** %ap) {
 entry:
   %t = va_arg i8** %ap, i8
   ret i8 %t
 }
 
 ; Test va_arg with an i32 argument.
 
 ; CHECK-LABEL: arg_i32:
 ; CHECK-NEXT: .param     i32{{$}}
 ; CHECK-NEXT: .result    i32{{$}}
 ; CHECK-NEXT: .local     i32{{$}}
-; CHECK-NEXT: i32.load   $push0=, $0{{$}}
+; CHECK-NEXT: i32.load   $push0=, 0($0){{$}}
 ; CHECK-NEXT: i32.const  $push1=, 3{{$}}
 ; CHECK-NEXT: i32.add    $push2=, $pop0, $pop1{{$}}
 ; CHECK-NEXT: i32.const  $push3=, -4{{$}}
 ; CHECK-NEXT: i32.and    $1=, $pop2, $pop3{{$}}
 ; CHECK-NEXT: i32.const  $push4=, 4{{$}}
 ; CHECK-NEXT: i32.add    $push5=, $1, $pop4{{$}}
-; CHECK-NEXT: i32.store  $discard=, $0, $pop5{{$}}
-; CHECK-NEXT: i32.load   $push6=, $1{{$}}
+; CHECK-NEXT: i32.store  $discard=, 0($0), $pop5{{$}}
+; CHECK-NEXT: i32.load   $push6=, 0($1){{$}}
 ; CHECK-NEXT: return     $pop6{{$}}
 define i32 @arg_i32(i8** %ap) {
 entry:
   %t = va_arg i8** %ap, i32
   ret i32 %t
 }
 
 ; Test va_arg with an i128 argument.