This is an archive of the discontinued LLVM Phabricator instance.

Differential D14704

[mips][ias] Replace anchor comments with anchor instructions in tests.
ClosedPublic

Authored by dsanders on Nov 16 2015, 7:09 AM.

Details

Reviewers
vkalintiris
Commits
rGf2b5bff84342: [mips][ias] Replace anchor comments with anchor instructions in tests.
rL254147: [mips][ias] Replace anchor comments with anchor instructions in tests.
Summary

This is because IAS will delete the comments. NFC at the moment but it will
prevent a failure once IAS is the default.

Diff Detail

Event Timeline

dsanders updated this revision to Diff 40284.Nov 16 2015, 7:09 AM
dsanders retitled this revision from to [mips][ias] Replace anchor comments with anchor instructions in tests..
dsanders updated this object.
dsanders added a reviewer: vkalintiris.
dsanders added a subscriber: llvm-commits.
Herald added a subscriber: dsanders. · View Herald TranscriptNov 16 2015, 7:09 AM
vkalintiris accepted this revision.Nov 18 2015, 2:16 AM
vkalintiris edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Nov 18 2015, 2:16 AM
dsanders closed this revision.Nov 26 2015, 2:29 AM

Revision Contents

PathSize
test/
CodeGen/
Mips/
cconv/
72 lines
16 lines

Diff 40284

test/CodeGen/Mips/cconv/arguments-varargs.ll

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; N32-DAG: sw [[VA]], 0([[SP]]) ; N32-DAG: sw [[VA]], 0([[SP]])
; N64-DAG: daddiu [[VA:\$[0-9]+]], [[SP]], 8 ; N64-DAG: daddiu [[VA:\$[0-9]+]], [[SP]], 8
; N64-DAG: sd [[VA]], 0([[SP]]) ; N64-DAG: sd [[VA]], 0([[SP]])
; Store [[VA]] ; Store [[VA]]
; O32-DAG: sw [[VA]], 0([[SP]]) ; O32-DAG: sw [[VA]], 0([[SP]])
; ALL: # ANCHOR1 ; ALL: teqi $zero, 1
; Increment [[VA]] ; Increment [[VA]]
; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4 ; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4
; O32-DAG: sw [[VA2]], 0([[SP]]) ; O32-DAG: sw [[VA2]], 0([[SP]])
; N32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) ; N32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
; N32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 8 ; N32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 8
Show All 17 Lines
; O32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords) ; O32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords)
; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords) ; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords)
; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(hwords)( ; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(hwords)(
; ALL-DAG: sh [[ARG1]], 2([[GV]]) ; ALL-DAG: sh [[ARG1]], 2([[GV]])
; ALL: # ANCHOR2 ; ALL: teqi $zero, 2
; Increment [[VA]] again. ; Increment [[VA]] again.
; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4 ; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4
; O32-DAG: sw [[VA2]], 0([[SP]]) ; O32-DAG: sw [[VA2]], 0([[SP]])
; N32-DAG: lw [[VA2:\$[0-9]+]], 0([[SP]]) ; N32-DAG: lw [[VA2:\$[0-9]+]], 0([[SP]])
; N32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 8 ; N32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 8
Show All 11 Lines
; Copy the arg to the global ; Copy the arg to the global
; ALL-DAG: sh [[ARG2]], 4([[GV]]) ; ALL-DAG: sh [[ARG2]], 4([[GV]])
%ap = alloca i8*, align 8 %ap = alloca i8*, align 8
%ap2 = bitcast i8** %ap to i8* %ap2 = bitcast i8** %ap to i8*
call void @llvm.va_start(i8* %ap2) call void @llvm.va_start(i8* %ap2)
call void asm sideeffect "# ANCHOR1", ""() call void asm sideeffect "teqi $$zero, 1", ""()
%arg1 = va_arg i8** %ap, i16 %arg1 = va_arg i8** %ap, i16
%e1 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 1 %e1 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 1
store volatile i16 %arg1, i16* %e1, align 2 store volatile i16 %arg1, i16* %e1, align 2
call void asm sideeffect "# ANCHOR2", ""() call void asm sideeffect "teqi $$zero, 2", ""()
%arg2 = va_arg i8** %ap, i16 %arg2 = va_arg i8** %ap, i16
%e2 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 2 %e2 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 2
store volatile i16 %arg2, i16* %e2, align 2 store volatile i16 %arg2, i16* %e2, align 2
call void @llvm.va_end(i8* %ap2) call void @llvm.va_end(i8* %ap2)
ret void ret void
} }
Show All 34 Lines
; N32-DAG: sw [[VA]], 0([[SP]]) ; N32-DAG: sw [[VA]], 0([[SP]])
; N64-DAG: daddiu [[VA:\$[0-9]+]], [[SP]], 8 ; N64-DAG: daddiu [[VA:\$[0-9]+]], [[SP]], 8
; N64-DAG: sd [[VA]], 0([[SP]]) ; N64-DAG: sd [[VA]], 0([[SP]])
; Store [[VA]] ; Store [[VA]]
; O32-DAG: sw [[VA]], 0([[SP]]) ; O32-DAG: sw [[VA]], 0([[SP]])
; ALL: # ANCHOR1 ; ALL: teqi $zero, 1
; Increment [[VA]] ; Increment [[VA]]
; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4 ; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4
; O32-DAG: sw [[VA2]], 0([[SP]]) ; O32-DAG: sw [[VA2]], 0([[SP]])
; N32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) ; N32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
; N32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 8 ; N32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 8
Show All 17 Lines
; O32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words) ; O32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words)
; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words) ; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words)
; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(words)( ; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(words)(
; ALL-DAG: sw [[ARG1]], 4([[GV]]) ; ALL-DAG: sw [[ARG1]], 4([[GV]])
; ALL: # ANCHOR2 ; ALL: teqi $zero, 2
; Increment [[VA]] again. ; Increment [[VA]] again.
; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4 ; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4
; O32-DAG: sw [[VA2]], 0([[SP]]) ; O32-DAG: sw [[VA2]], 0([[SP]])
; N32-DAG: lw [[VA2:\$[0-9]+]], 0([[SP]]) ; N32-DAG: lw [[VA2:\$[0-9]+]], 0([[SP]])
; N32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 8 ; N32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 8
Show All 11 Lines
; Copy the arg to the global ; Copy the arg to the global
; ALL-DAG: sw [[ARG2]], 8([[GV]]) ; ALL-DAG: sw [[ARG2]], 8([[GV]])
%ap = alloca i8*, align 8 %ap = alloca i8*, align 8
%ap2 = bitcast i8** %ap to i8* %ap2 = bitcast i8** %ap to i8*
call void @llvm.va_start(i8* %ap2) call void @llvm.va_start(i8* %ap2)
call void asm sideeffect "# ANCHOR1", ""() call void asm sideeffect "teqi $$zero, 1", ""()
%arg1 = va_arg i8** %ap, i32 %arg1 = va_arg i8** %ap, i32
%e1 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 1 %e1 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 1
store volatile i32 %arg1, i32* %e1, align 4 store volatile i32 %arg1, i32* %e1, align 4
call void asm sideeffect "# ANCHOR2", ""() call void asm sideeffect "teqi $$zero, 2", ""()
%arg2 = va_arg i8** %ap, i32 %arg2 = va_arg i8** %ap, i32
%e2 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 2 %e2 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 2
store volatile i32 %arg2, i32* %e2, align 4 store volatile i32 %arg2, i32* %e2, align 4
call void @llvm.va_end(i8* %ap2) call void @llvm.va_end(i8* %ap2)
ret void ret void
} }
Show All 34 Lines
; N32-DAG: sw [[VA]], 0([[SP]]) ; N32-DAG: sw [[VA]], 0([[SP]])
; N64-DAG: daddiu [[VA:\$[0-9]+]], [[SP]], 8 ; N64-DAG: daddiu [[VA:\$[0-9]+]], [[SP]], 8
; N64-DAG: sd [[VA]], 0([[SP]]) ; N64-DAG: sd [[VA]], 0([[SP]])
; Store [[VA]] ; Store [[VA]]
; O32-DAG: sw [[VA]], 0([[SP]]) ; O32-DAG: sw [[VA]], 0([[SP]])
; ALL: # ANCHOR1 ; ALL: teqi $zero, 1
; Increment [[VA]] (and realign pointer for O32) ; Increment [[VA]] (and realign pointer for O32)
; O32: lw [[VA:\$[0-9]+]], 0([[SP]]) ; O32: lw [[VA:\$[0-9]+]], 0([[SP]])
; O32-DAG: addiu [[VA_TMP0:\$[0-9]+]], [[VA]], 7 ; O32-DAG: addiu [[VA_TMP0:\$[0-9]+]], [[VA]], 7
; O32-DAG: addiu [[VA_TMP1:\$[0-9]+]], $zero, -8 ; O32-DAG: addiu [[VA_TMP1:\$[0-9]+]], $zero, -8
; O32-DAG: and [[VA_TMP2:\$[0-9]+]], [[VA_TMP0]], [[VA_TMP1]] ; O32-DAG: and [[VA_TMP2:\$[0-9]+]], [[VA_TMP0]], [[VA_TMP1]]
; O32-DAG: ori [[VA2:\$[0-9]+]], [[VA_TMP2]], 4 ; O32-DAG: ori [[VA2:\$[0-9]+]], [[VA_TMP2]], 4
; O32-DAG: sw [[VA2]], 0([[SP]]) ; O32-DAG: sw [[VA2]], 0([[SP]])
Show All 20 Lines
; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]]) ; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])
; O32-DAG: sw [[ARG1]], 12([[GV]]) ; O32-DAG: sw [[ARG1]], 12([[GV]])
; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords) ; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)
; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(dwords)( ; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(dwords)(
; NEW-DAG: ld [[ARG1:\$[0-9]+]], 0([[VA]]) ; NEW-DAG: ld [[ARG1:\$[0-9]+]], 0([[VA]])
; NEW-DAG: sd [[ARG1]], 8([[GV]]) ; NEW-DAG: sd [[ARG1]], 8([[GV]])
; ALL: # ANCHOR2 ; ALL: teqi $zero, 2
; Increment [[VA]] again. ; Increment [[VA]] again.
; FIXME: We're still aligned from the last one but CodeGen doesn't spot that. ; FIXME: We're still aligned from the last one but CodeGen doesn't spot that.
; O32: lw [[VA:\$[0-9]+]], 0([[SP]]) ; O32: lw [[VA:\$[0-9]+]], 0([[SP]])
; O32-DAG: addiu [[VA_TMP0:\$[0-9]+]], [[VA]], 7 ; O32-DAG: addiu [[VA_TMP0:\$[0-9]+]], [[VA]], 7
; O32-DAG: and [[VA_TMP2:\$[0-9]+]], [[VA_TMP0]], [[VA_TMP1]] ; O32-DAG: and [[VA_TMP2:\$[0-9]+]], [[VA_TMP0]], [[VA_TMP1]]
; O32-DAG: ori [[VA2:\$[0-9]+]], [[VA_TMP2]], 4 ; O32-DAG: ori [[VA2:\$[0-9]+]], [[VA_TMP2]], 4
; O32-DAG: sw [[VA2]], 0([[SP]]) ; O32-DAG: sw [[VA2]], 0([[SP]])
Show All 17 Lines
; NEW-DAG: ld [[ARG2:\$[0-9]+]], 0([[VA2]]) ; NEW-DAG: ld [[ARG2:\$[0-9]+]], 0([[VA2]])
; NEW-DAG: sd [[ARG2]], 16([[GV]]) ; NEW-DAG: sd [[ARG2]], 16([[GV]])
%ap = alloca i8*, align 8 %ap = alloca i8*, align 8
%ap2 = bitcast i8** %ap to i8* %ap2 = bitcast i8** %ap to i8*
call void @llvm.va_start(i8* %ap2) call void @llvm.va_start(i8* %ap2)
call void asm sideeffect "# ANCHOR1", ""() call void asm sideeffect "teqi $$zero, 1", ""()
%arg1 = va_arg i8** %ap, i64 %arg1 = va_arg i8** %ap, i64
%e1 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 1 %e1 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 1
store volatile i64 %arg1, i64* %e1, align 8 store volatile i64 %arg1, i64* %e1, align 8
call void asm sideeffect "# ANCHOR2", ""() call void asm sideeffect "teqi $$zero, 2", ""()
%arg2 = va_arg i8** %ap, i64 %arg2 = va_arg i8** %ap, i64
%e2 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 2 %e2 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 2
store volatile i64 %arg2, i64* %e2, align 8 store volatile i64 %arg2, i64* %e2, align 8
call void @llvm.va_end(i8* %ap2) call void @llvm.va_end(i8* %ap2)
ret void ret void
} }
Show All 34 Lines
; N32-DAG: sw [[VA]], 0([[SP]]) ; N32-DAG: sw [[VA]], 0([[SP]])
; N64-DAG: daddiu [[VA:\$[0-9]+]], [[SP]], 8 ; N64-DAG: daddiu [[VA:\$[0-9]+]], [[SP]], 8
; N64-DAG: sd [[VA]], 0([[SP]]) ; N64-DAG: sd [[VA]], 0([[SP]])
; Store [[VA]] ; Store [[VA]]
; O32-DAG: sw [[VA]], 0([[SP]]) ; O32-DAG: sw [[VA]], 0([[SP]])
; ALL: # ANCHOR1 ; ALL: teqi $zero, 1
; Increment [[VA]] ; Increment [[VA]]
; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4 ; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4
; O32-DAG: sw [[VA2]], 0([[SP]]) ; O32-DAG: sw [[VA2]], 0([[SP]])
; N32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) ; N32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
; N32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 8 ; N32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 8
Show All 17 Lines
; O32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords) ; O32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords)
; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords) ; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords)
; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(hwords)( ; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(hwords)(
; ALL-DAG: sh [[ARG1]], 2([[GV]]) ; ALL-DAG: sh [[ARG1]], 2([[GV]])
; ALL: # ANCHOR2 ; ALL: teqi $zero, 2
; Increment [[VA]] again. ; Increment [[VA]] again.
; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4 ; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4
; O32-DAG: sw [[VA2]], 0([[SP]]) ; O32-DAG: sw [[VA2]], 0([[SP]])
; N32-DAG: lw [[VA2:\$[0-9]+]], 0([[SP]]) ; N32-DAG: lw [[VA2:\$[0-9]+]], 0([[SP]])
; N32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 8 ; N32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 8
Show All 11 Lines
; Copy the arg to the global ; Copy the arg to the global
; ALL-DAG: sh [[ARG2]], 4([[GV]]) ; ALL-DAG: sh [[ARG2]], 4([[GV]])
%ap = alloca i8*, align 8 %ap = alloca i8*, align 8
%ap2 = bitcast i8** %ap to i8* %ap2 = bitcast i8** %ap to i8*
call void @llvm.va_start(i8* %ap2) call void @llvm.va_start(i8* %ap2)
call void asm sideeffect "# ANCHOR1", ""() call void asm sideeffect "teqi $$zero, 1", ""()
%arg1 = va_arg i8** %ap, i16 %arg1 = va_arg i8** %ap, i16
%e1 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 1 %e1 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 1
store volatile i16 %arg1, i16* %e1, align 2 store volatile i16 %arg1, i16* %e1, align 2
call void asm sideeffect "# ANCHOR2", ""() call void asm sideeffect "teqi $$zero, 2", ""()
%arg2 = va_arg i8** %ap, i16 %arg2 = va_arg i8** %ap, i16
%e2 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 2 %e2 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 2
store volatile i16 %arg2, i16* %e2, align 2 store volatile i16 %arg2, i16* %e2, align 2
call void @llvm.va_end(i8* %ap2) call void @llvm.va_end(i8* %ap2)
ret void ret void
} }
Show All 34 Lines
; N32-DAG: sw [[VA]], 0([[SP]]) ; N32-DAG: sw [[VA]], 0([[SP]])
; N64-DAG: daddiu [[VA:\$[0-9]+]], [[SP]], 8 ; N64-DAG: daddiu [[VA:\$[0-9]+]], [[SP]], 8
; N64-DAG: sd [[VA]], 0([[SP]]) ; N64-DAG: sd [[VA]], 0([[SP]])
; Store [[VA]] ; Store [[VA]]
; O32-DAG: sw [[VA]], 0([[SP]]) ; O32-DAG: sw [[VA]], 0([[SP]])
; ALL: # ANCHOR1 ; ALL: teqi $zero, 1
; Increment [[VA]] ; Increment [[VA]]
; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4 ; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4
; O32-DAG: sw [[VA2]], 0([[SP]]) ; O32-DAG: sw [[VA2]], 0([[SP]])
; N32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) ; N32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
; N32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 8 ; N32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 8
Show All 17 Lines
; O32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words) ; O32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words)
; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words) ; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words)
; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(words)( ; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(words)(
; ALL-DAG: sw [[ARG1]], 4([[GV]]) ; ALL-DAG: sw [[ARG1]], 4([[GV]])
; ALL: # ANCHOR2 ; ALL: teqi $zero, 2
; Increment [[VA]] again. ; Increment [[VA]] again.
; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4 ; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4
; O32-DAG: sw [[VA2]], 0([[SP]]) ; O32-DAG: sw [[VA2]], 0([[SP]])
; N32-DAG: lw [[VA2:\$[0-9]+]], 0([[SP]]) ; N32-DAG: lw [[VA2:\$[0-9]+]], 0([[SP]])
; N32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 8 ; N32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 8
Show All 11 Lines
; Copy the arg to the global ; Copy the arg to the global
; ALL-DAG: sw [[ARG2]], 8([[GV]]) ; ALL-DAG: sw [[ARG2]], 8([[GV]])
%ap = alloca i8*, align 8 %ap = alloca i8*, align 8
%ap2 = bitcast i8** %ap to i8* %ap2 = bitcast i8** %ap to i8*
call void @llvm.va_start(i8* %ap2) call void @llvm.va_start(i8* %ap2)
call void asm sideeffect "# ANCHOR1", ""() call void asm sideeffect "teqi $$zero, 1", ""()
%arg1 = va_arg i8** %ap, i32 %arg1 = va_arg i8** %ap, i32
%e1 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 1 %e1 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 1
store volatile i32 %arg1, i32* %e1, align 4 store volatile i32 %arg1, i32* %e1, align 4
call void asm sideeffect "# ANCHOR2", ""() call void asm sideeffect "teqi $$zero, 2", ""()
%arg2 = va_arg i8** %ap, i32 %arg2 = va_arg i8** %ap, i32
%e2 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 2 %e2 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 2
store volatile i32 %arg2, i32* %e2, align 4 store volatile i32 %arg2, i32* %e2, align 4
call void @llvm.va_end(i8* %ap2) call void @llvm.va_end(i8* %ap2)
ret void ret void
} }
Show All 34 Lines
; N32-DAG: sw [[VA]], 0([[SP]]) ; N32-DAG: sw [[VA]], 0([[SP]])
; N64-DAG: daddiu [[VA:\$[0-9]+]], [[SP]], 8 ; N64-DAG: daddiu [[VA:\$[0-9]+]], [[SP]], 8
; N64-DAG: sd [[VA]], 0([[SP]]) ; N64-DAG: sd [[VA]], 0([[SP]])
; Store [[VA]] ; Store [[VA]]
; O32-DAG: sw [[VA]], 0([[SP]]) ; O32-DAG: sw [[VA]], 0([[SP]])
; ALL: # ANCHOR1 ; ALL: teqi $zero, 1
; Increment [[VA]] (and realign pointer for O32) ; Increment [[VA]] (and realign pointer for O32)
; O32: lw [[VA:\$[0-9]+]], 0([[SP]]) ; O32: lw [[VA:\$[0-9]+]], 0([[SP]])
; O32-DAG: addiu [[VA_TMP0:\$[0-9]+]], [[VA]], 7 ; O32-DAG: addiu [[VA_TMP0:\$[0-9]+]], [[VA]], 7
; O32-DAG: addiu [[VA_TMP1:\$[0-9]+]], $zero, -8 ; O32-DAG: addiu [[VA_TMP1:\$[0-9]+]], $zero, -8
; O32-DAG: and [[VA_TMP2:\$[0-9]+]], [[VA_TMP0]], [[VA_TMP1]] ; O32-DAG: and [[VA_TMP2:\$[0-9]+]], [[VA_TMP0]], [[VA_TMP1]]
; O32-DAG: ori [[VA2:\$[0-9]+]], [[VA_TMP2]], 4 ; O32-DAG: ori [[VA2:\$[0-9]+]], [[VA_TMP2]], 4
; O32-DAG: sw [[VA2]], 0([[SP]]) ; O32-DAG: sw [[VA2]], 0([[SP]])
Show All 20 Lines
; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]]) ; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])
; O32-DAG: sw [[ARG1]], 12([[GV]]) ; O32-DAG: sw [[ARG1]], 12([[GV]])
; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords) ; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)
; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(dwords)( ; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(dwords)(
; NEW-DAG: ld [[ARG1:\$[0-9]+]], 0([[VA]]) ; NEW-DAG: ld [[ARG1:\$[0-9]+]], 0([[VA]])
; NEW-DAG: sd [[ARG1]], 8([[GV]]) ; NEW-DAG: sd [[ARG1]], 8([[GV]])
; ALL: # ANCHOR2 ; ALL: teqi $zero, 2
; Increment [[VA]] again. ; Increment [[VA]] again.
; FIXME: We're still aligned from the last one but CodeGen doesn't spot that. ; FIXME: We're still aligned from the last one but CodeGen doesn't spot that.
; O32: lw [[VA:\$[0-9]+]], 0([[SP]]) ; O32: lw [[VA:\$[0-9]+]], 0([[SP]])
; O32-DAG: addiu [[VA_TMP0:\$[0-9]+]], [[VA]], 7 ; O32-DAG: addiu [[VA_TMP0:\$[0-9]+]], [[VA]], 7
; O32-DAG: and [[VA_TMP2:\$[0-9]+]], [[VA_TMP0]], [[VA_TMP1]] ; O32-DAG: and [[VA_TMP2:\$[0-9]+]], [[VA_TMP0]], [[VA_TMP1]]
; O32-DAG: ori [[VA2:\$[0-9]+]], [[VA_TMP2]], 4 ; O32-DAG: ori [[VA2:\$[0-9]+]], [[VA_TMP2]], 4
; O32-DAG: sw [[VA2]], 0([[SP]]) ; O32-DAG: sw [[VA2]], 0([[SP]])
Show All 17 Lines
; NEW-DAG: ld [[ARG2:\$[0-9]+]], 0([[VA2]]) ; NEW-DAG: ld [[ARG2:\$[0-9]+]], 0([[VA2]])
; NEW-DAG: sd [[ARG2]], 16([[GV]]) ; NEW-DAG: sd [[ARG2]], 16([[GV]])
%ap = alloca i8*, align 8 %ap = alloca i8*, align 8
%ap2 = bitcast i8** %ap to i8* %ap2 = bitcast i8** %ap to i8*
call void @llvm.va_start(i8* %ap2) call void @llvm.va_start(i8* %ap2)
call void asm sideeffect "# ANCHOR1", ""() call void asm sideeffect "teqi $$zero, 1", ""()
%arg1 = va_arg i8** %ap, i64 %arg1 = va_arg i8** %ap, i64
%e1 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 1 %e1 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 1
store volatile i64 %arg1, i64* %e1, align 8 store volatile i64 %arg1, i64* %e1, align 8
call void asm sideeffect "# ANCHOR2", ""() call void asm sideeffect "teqi $$zero, 2", ""()
%arg2 = va_arg i8** %ap, i64 %arg2 = va_arg i8** %ap, i64
%e2 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 2 %e2 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 2
store volatile i64 %arg2, i64* %e2, align 8 store volatile i64 %arg2, i64* %e2, align 8
call void @llvm.va_end(i8* %ap2) call void @llvm.va_end(i8* %ap2)
ret void ret void
} }
Show All 33 Lines
; N32-DAG: sw [[VA]], 0([[SP]]) ; N32-DAG: sw [[VA]], 0([[SP]])
; N64-DAG: daddiu [[VA:\$[0-9]+]], [[SP]], 8 ; N64-DAG: daddiu [[VA:\$[0-9]+]], [[SP]], 8
; N64-DAG: sd [[VA]], 0([[SP]]) ; N64-DAG: sd [[VA]], 0([[SP]])
; Store [[VA]] ; Store [[VA]]
; O32-DAG: sw [[VA]], 0([[SP]]) ; O32-DAG: sw [[VA]], 0([[SP]])
; ALL: # ANCHOR1 ; ALL: teqi $zero, 1
; Increment [[VA]] ; Increment [[VA]]
; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4 ; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4
; O32-DAG: sw [[VA2]], 0([[SP]]) ; O32-DAG: sw [[VA2]], 0([[SP]])
; N32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) ; N32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
; N32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 8 ; N32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 8
Show All 17 Lines
; O32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords) ; O32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords)
; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords) ; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords)
; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(hwords)( ; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(hwords)(
; ALL-DAG: sh [[ARG1]], 2([[GV]]) ; ALL-DAG: sh [[ARG1]], 2([[GV]])
; ALL: # ANCHOR2 ; ALL: teqi $zero, 2
; Increment [[VA]] again. ; Increment [[VA]] again.
; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4 ; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4
; O32-DAG: sw [[VA2]], 0([[SP]]) ; O32-DAG: sw [[VA2]], 0([[SP]])
; N32-DAG: lw [[VA2:\$[0-9]+]], 0([[SP]]) ; N32-DAG: lw [[VA2:\$[0-9]+]], 0([[SP]])
; N32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 8 ; N32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 8
Show All 11 Lines
; Copy the arg to the global ; Copy the arg to the global
; ALL-DAG: sh [[ARG2]], 4([[GV]]) ; ALL-DAG: sh [[ARG2]], 4([[GV]])
%ap = alloca i8*, align 8 %ap = alloca i8*, align 8
%ap2 = bitcast i8** %ap to i8* %ap2 = bitcast i8** %ap to i8*
call void @llvm.va_start(i8* %ap2) call void @llvm.va_start(i8* %ap2)
call void asm sideeffect "# ANCHOR1", ""() call void asm sideeffect "teqi $$zero, 1", ""()
%arg1 = va_arg i8** %ap, i16 %arg1 = va_arg i8** %ap, i16
%e1 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 1 %e1 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 1
store volatile i16 %arg1, i16* %e1, align 2 store volatile i16 %arg1, i16* %e1, align 2
call void asm sideeffect "# ANCHOR2", ""() call void asm sideeffect "teqi $$zero, 2", ""()
%arg2 = va_arg i8** %ap, i16 %arg2 = va_arg i8** %ap, i16
%e2 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 2 %e2 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 2
store volatile i16 %arg2, i16* %e2, align 2 store volatile i16 %arg2, i16* %e2, align 2
call void @llvm.va_end(i8* %ap2) call void @llvm.va_end(i8* %ap2)
ret void ret void
} }
Show All 33 Lines
; N32-DAG: sw [[VA]], 0([[SP]]) ; N32-DAG: sw [[VA]], 0([[SP]])
; N64-DAG: daddiu [[VA:\$[0-9]+]], [[SP]], 8 ; N64-DAG: daddiu [[VA:\$[0-9]+]], [[SP]], 8
; N64-DAG: sd [[VA]], 0([[SP]]) ; N64-DAG: sd [[VA]], 0([[SP]])
; Store [[VA]] ; Store [[VA]]
; O32-DAG: sw [[VA]], 0([[SP]]) ; O32-DAG: sw [[VA]], 0([[SP]])
; ALL: # ANCHOR1 ; ALL: teqi $zero, 1
; Increment [[VA]] ; Increment [[VA]]
; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4 ; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4
; O32-DAG: sw [[VA2]], 0([[SP]]) ; O32-DAG: sw [[VA2]], 0([[SP]])
; N32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) ; N32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
; N32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 8 ; N32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 8
Show All 17 Lines
; O32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words) ; O32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words)
; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words) ; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words)
; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(words)( ; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(words)(
; ALL-DAG: sw [[ARG1]], 4([[GV]]) ; ALL-DAG: sw [[ARG1]], 4([[GV]])
; ALL: # ANCHOR2 ; ALL: teqi $zero, 2
; Increment [[VA]] again. ; Increment [[VA]] again.
; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4 ; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4
; O32-DAG: sw [[VA2]], 0([[SP]]) ; O32-DAG: sw [[VA2]], 0([[SP]])
; N32-DAG: lw [[VA2:\$[0-9]+]], 0([[SP]]) ; N32-DAG: lw [[VA2:\$[0-9]+]], 0([[SP]])
; N32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 8 ; N32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 8
Show All 11 Lines
; Copy the arg to the global ; Copy the arg to the global
; ALL-DAG: sw [[ARG2]], 8([[GV]]) ; ALL-DAG: sw [[ARG2]], 8([[GV]])
%ap = alloca i8*, align 8 %ap = alloca i8*, align 8
%ap2 = bitcast i8** %ap to i8* %ap2 = bitcast i8** %ap to i8*
call void @llvm.va_start(i8* %ap2) call void @llvm.va_start(i8* %ap2)
call void asm sideeffect "# ANCHOR1", ""() call void asm sideeffect "teqi $$zero, 1", ""()
%arg1 = va_arg i8** %ap, i32 %arg1 = va_arg i8** %ap, i32
%e1 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 1 %e1 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 1
store volatile i32 %arg1, i32* %e1, align 4 store volatile i32 %arg1, i32* %e1, align 4
call void asm sideeffect "# ANCHOR2", ""() call void asm sideeffect "teqi $$zero, 2", ""()
%arg2 = va_arg i8** %ap, i32 %arg2 = va_arg i8** %ap, i32
%e2 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 2 %e2 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 2
store volatile i32 %arg2, i32* %e2, align 4 store volatile i32 %arg2, i32* %e2, align 4
call void @llvm.va_end(i8* %ap2) call void @llvm.va_end(i8* %ap2)
ret void ret void
} }
Show All 33 Lines
; N32-DAG: sw [[VA]], 0([[SP]]) ; N32-DAG: sw [[VA]], 0([[SP]])
; N64-DAG: daddiu [[VA:\$[0-9]+]], [[SP]], 8 ; N64-DAG: daddiu [[VA:\$[0-9]+]], [[SP]], 8
; N64-DAG: sd [[VA]], 0([[SP]]) ; N64-DAG: sd [[VA]], 0([[SP]])
; Store [[VA]] ; Store [[VA]]
; O32-DAG: sw [[VA]], 0([[SP]]) ; O32-DAG: sw [[VA]], 0([[SP]])
; ALL: # ANCHOR1 ; ALL: teqi $zero, 1
; Increment [[VA]] (and realign pointer for O32) ; Increment [[VA]] (and realign pointer for O32)
; O32: lw [[VA:\$[0-9]+]], 0([[SP]]) ; O32: lw [[VA:\$[0-9]+]], 0([[SP]])
; O32-DAG: addiu [[VA_TMP0:\$[0-9]+]], [[VA]], 7 ; O32-DAG: addiu [[VA_TMP0:\$[0-9]+]], [[VA]], 7
; O32-DAG: addiu [[VA_TMP1:\$[0-9]+]], $zero, -8 ; O32-DAG: addiu [[VA_TMP1:\$[0-9]+]], $zero, -8
; O32-DAG: and [[VA_TMP2:\$[0-9]+]], [[VA_TMP0]], [[VA_TMP1]] ; O32-DAG: and [[VA_TMP2:\$[0-9]+]], [[VA_TMP0]], [[VA_TMP1]]
; O32-DAG: ori [[VA2:\$[0-9]+]], [[VA_TMP2]], 4 ; O32-DAG: ori [[VA2:\$[0-9]+]], [[VA_TMP2]], 4
; O32-DAG: sw [[VA2]], 0([[SP]]) ; O32-DAG: sw [[VA2]], 0([[SP]])
Show All 20 Lines
; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]]) ; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])
; O32-DAG: sw [[ARG1]], 12([[GV]]) ; O32-DAG: sw [[ARG1]], 12([[GV]])
; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords) ; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)
; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(dwords)( ; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(dwords)(
; NEW-DAG: ld [[ARG1:\$[0-9]+]], 0([[VA]]) ; NEW-DAG: ld [[ARG1:\$[0-9]+]], 0([[VA]])
; NEW-DAG: sd [[ARG1]], 8([[GV]]) ; NEW-DAG: sd [[ARG1]], 8([[GV]])
; ALL: # ANCHOR2 ; ALL: teqi $zero, 2
; Increment [[VA]] again. ; Increment [[VA]] again.
; FIXME: We're still aligned from the last one but CodeGen doesn't spot that. ; FIXME: We're still aligned from the last one but CodeGen doesn't spot that.
; O32: lw [[VA:\$[0-9]+]], 0([[SP]]) ; O32: lw [[VA:\$[0-9]+]], 0([[SP]])
; O32-DAG: addiu [[VA_TMP0:\$[0-9]+]], [[VA]], 7 ; O32-DAG: addiu [[VA_TMP0:\$[0-9]+]], [[VA]], 7
; O32-DAG: and [[VA_TMP2:\$[0-9]+]], [[VA_TMP0]], [[VA_TMP1]] ; O32-DAG: and [[VA_TMP2:\$[0-9]+]], [[VA_TMP0]], [[VA_TMP1]]
; O32-DAG: ori [[VA2:\$[0-9]+]], [[VA_TMP2]], 4 ; O32-DAG: ori [[VA2:\$[0-9]+]], [[VA_TMP2]], 4
; O32-DAG: sw [[VA2]], 0([[SP]]) ; O32-DAG: sw [[VA2]], 0([[SP]])
Show All 17 Lines
; NEW-DAG: ld [[ARG2:\$[0-9]+]], 0([[VA2]]) ; NEW-DAG: ld [[ARG2:\$[0-9]+]], 0([[VA2]])
; NEW-DAG: sd [[ARG2]], 16([[GV]]) ; NEW-DAG: sd [[ARG2]], 16([[GV]])
%ap = alloca i8*, align 8 %ap = alloca i8*, align 8
%ap2 = bitcast i8** %ap to i8* %ap2 = bitcast i8** %ap to i8*
call void @llvm.va_start(i8* %ap2) call void @llvm.va_start(i8* %ap2)
call void asm sideeffect "# ANCHOR1", ""() call void asm sideeffect "teqi $$zero, 1", ""()
%arg1 = va_arg i8** %ap, i64 %arg1 = va_arg i8** %ap, i64
%e1 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 1 %e1 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 1
store volatile i64 %arg1, i64* %e1, align 8 store volatile i64 %arg1, i64* %e1, align 8
call void asm sideeffect "# ANCHOR2", ""() call void asm sideeffect "teqi $$zero, 2", ""()
%arg2 = va_arg i8** %ap, i64 %arg2 = va_arg i8** %ap, i64
%e2 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 2 %e2 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 2
store volatile i64 %arg2, i64* %e2, align 8 store volatile i64 %arg2, i64* %e2, align 8
call void @llvm.va_end(i8* %ap2) call void @llvm.va_end(i8* %ap2)
ret void ret void
} }
declare void @llvm.va_start(i8*) declare void @llvm.va_start(i8*)
declare void @llvm.va_end(i8*) declare void @llvm.va_end(i8*)

test/CodeGen/Mips/no-odd-spreg-msa.ll

Show All 13 Linesentry:
; ;
; The intention is that if odd single precision registers are permitted, the ; The intention is that if odd single precision registers are permitted, the
; allocator will choose $f12/$w12 for the vector and $f13 for the float to ; allocator will choose $f12/$w12 for the vector and $f13 for the float to
; avoid the spill/reload. ; avoid the spill/reload.
; ;
; On the other hand, if odd single precision registers are not permitted, it ; On the other hand, if odd single precision registers are not permitted, it
; must copy $f13 to an even-numbered register before inserting into the ; must copy $f13 to an even-numbered register before inserting into the
; vector. ; vector.
call void asm sideeffect "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"() call void asm sideeffect "teqi $$zero, 1", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
%1 = insertelement <4 x float> %0, float %b, i32 0 %1 = insertelement <4 x float> %0, float %b, i32 0
store <4 x float> %1, <4 x float>* @v4f32 store <4 x float> %1, <4 x float>* @v4f32
ret void ret void
} }
; ALL-LABEL: msa_insert_0: ; ALL-LABEL: msa_insert_0:
; ALL: mov.s $f13, $f12 ; ALL: mov.s $f13, $f12
; ALL: lw $[[R0:[0-9]+]], %got(v4f32)( ; ALL: lw $[[R0:[0-9]+]], %got(v4f32)(
; ALL: ld.w $w[[W0:[0-9]+]], 0($[[R0]]) ; ALL: ld.w $w[[W0:[0-9]+]], 0($[[R0]])
; NOODDSPREG: mov.s $f[[F0:[0-9]+]], $f13 ; NOODDSPREG: mov.s $f[[F0:[0-9]+]], $f13
; NOODDSPREG: insve.w $w[[W0]][0], $w[[F0]][0] ; NOODDSPREG: insve.w $w[[W0]][0], $w[[F0]][0]
; ODDSPREG: insve.w $w[[W0]][0], $w13[0] ; ODDSPREG: insve.w $w[[W0]][0], $w13[0]
; ALL: # Clobber ; ALL: teqi $zero, 1
; ALL-NOT: sdc1 ; ALL-NOT: sdc1
; ALL-NOT: ldc1 ; ALL-NOT: ldc1
; ALL: st.w $w[[W0]], 0($[[R0]]) ; ALL: st.w $w[[W0]], 0($[[R0]])
define void @msa_insert_1(float %a) { define void @msa_insert_1(float %a) {
entry: entry:
; Force the float into an odd-numbered register using named registers and ; Force the float into an odd-numbered register using named registers and
; load the vector. ; load the vector.
%b = call float asm sideeffect "mov.s $0, $1", "={$f13},{$f12}" (float %a) %b = call float asm sideeffect "mov.s $0, $1", "={$f13},{$f12}" (float %a)
%0 = load volatile <4 x float>, <4 x float>* @v4f32 %0 = load volatile <4 x float>, <4 x float>* @v4f32
; Clobber all except $f12/$w12 and $f13 ; Clobber all except $f12/$w12 and $f13
; ;
; The intention is that if odd single precision registers are permitted, the ; The intention is that if odd single precision registers are permitted, the
; allocator will choose $f12/$w12 for the vector and $f13 for the float to ; allocator will choose $f12/$w12 for the vector and $f13 for the float to
; avoid the spill/reload. ; avoid the spill/reload.
; ;
; On the other hand, if odd single precision registers are not permitted, it ; On the other hand, if odd single precision registers are not permitted, it
; must copy $f13 to an even-numbered register before inserting into the ; must copy $f13 to an even-numbered register before inserting into the
; vector. ; vector.
call void asm sideeffect "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"() call void asm sideeffect "teqi $$zero, 1", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
%1 = insertelement <4 x float> %0, float %b, i32 1 %1 = insertelement <4 x float> %0, float %b, i32 1
store <4 x float> %1, <4 x float>* @v4f32 store <4 x float> %1, <4 x float>* @v4f32
ret void ret void
} }
; ALL-LABEL: msa_insert_1: ; ALL-LABEL: msa_insert_1:
; ALL: mov.s $f13, $f12 ; ALL: mov.s $f13, $f12
; ALL: lw $[[R0:[0-9]+]], %got(v4f32)( ; ALL: lw $[[R0:[0-9]+]], %got(v4f32)(
; ALL: ld.w $w[[W0:[0-9]+]], 0($[[R0]]) ; ALL: ld.w $w[[W0:[0-9]+]], 0($[[R0]])
; NOODDSPREG: mov.s $f[[F0:[0-9]+]], $f13 ; NOODDSPREG: mov.s $f[[F0:[0-9]+]], $f13
; NOODDSPREG: insve.w $w[[W0]][1], $w[[F0]][0] ; NOODDSPREG: insve.w $w[[W0]][1], $w[[F0]][0]
; ODDSPREG: insve.w $w[[W0]][1], $w13[0] ; ODDSPREG: insve.w $w[[W0]][1], $w13[0]
; ALL: # Clobber ; ALL: teqi $zero, 1
; ALL-NOT: sdc1 ; ALL-NOT: sdc1
; ALL-NOT: ldc1 ; ALL-NOT: ldc1
; ALL: st.w $w[[W0]], 0($[[R0]]) ; ALL: st.w $w[[W0]], 0($[[R0]])
define float @msa_extract_0() { define float @msa_extract_0() {
entry: entry:
%0 = load volatile <4 x float>, <4 x float>* @v4f32 %0 = load volatile <4 x float>, <4 x float>* @v4f32
%1 = call <4 x float> asm sideeffect "move.v $0, $1", "={$w13},{$w12}" (<4 x float> %0) %1 = call <4 x float> asm sideeffect "move.v $0, $1", "={$w13},{$w12}" (<4 x float> %0)
; Clobber all except $f12, and $f13 ; Clobber all except $f12, and $f13
; ;
; The intention is that if odd single precision registers are permitted, the ; The intention is that if odd single precision registers are permitted, the
; allocator will choose $f13/$w13 for the vector since that saves on moves. ; allocator will choose $f13/$w13 for the vector since that saves on moves.
; ;
; On the other hand, if odd single precision registers are not permitted, it ; On the other hand, if odd single precision registers are not permitted, it
; must move it to $f12/$w12. ; must move it to $f12/$w12.
call void asm sideeffect "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"() call void asm sideeffect "teqi $$zero, 1", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
%2 = extractelement <4 x float> %1, i32 0 %2 = extractelement <4 x float> %1, i32 0
ret float %2 ret float %2
} }
; ALL-LABEL: msa_extract_0: ; ALL-LABEL: msa_extract_0:
; ALL: lw $[[R0:[0-9]+]], %got(v4f32)( ; ALL: lw $[[R0:[0-9]+]], %got(v4f32)(
; ALL: ld.w $w12, 0($[[R0]]) ; ALL: ld.w $w12, 0($[[R0]])
; ALL: move.v $w[[W0:13]], $w12 ; ALL: move.v $w[[W0:13]], $w12
; NOODDSPREG: move.v $w[[W0:12]], $w13 ; NOODDSPREG: move.v $w[[W0:12]], $w13
; ALL: # Clobber ; ALL: teqi $zero, 1
; ALL-NOT: st.w ; ALL-NOT: st.w
; ALL-NOT: ld.w ; ALL-NOT: ld.w
; ALL: mov.s $f0, $f[[W0]] ; ALL: mov.s $f0, $f[[W0]]
define float @msa_extract_1() { define float @msa_extract_1() {
entry: entry:
%0 = load volatile <4 x float>, <4 x float>* @v4f32 %0 = load volatile <4 x float>, <4 x float>* @v4f32
%1 = call <4 x float> asm sideeffect "move.v $0, $1", "={$w13},{$w12}" (<4 x float> %0) %1 = call <4 x float> asm sideeffect "move.v $0, $1", "={$w13},{$w12}" (<4 x float> %0)
; Clobber all except $f13 ; Clobber all except $f13
; ;
; The intention is that if odd single precision registers are permitted, the ; The intention is that if odd single precision registers are permitted, the
; allocator will choose $f13/$w13 for the vector since that saves on moves. ; allocator will choose $f13/$w13 for the vector since that saves on moves.
; ;
; On the other hand, if odd single precision registers are not permitted, it ; On the other hand, if odd single precision registers are not permitted, it
; must be spilled. ; must be spilled.
call void asm sideeffect "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f12},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"() call void asm sideeffect "teqi $$zero, 1", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f12},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
%2 = extractelement <4 x float> %1, i32 1 %2 = extractelement <4 x float> %1, i32 1
ret float %2 ret float %2
} }
; ALL-LABEL: msa_extract_1: ; ALL-LABEL: msa_extract_1:
; ALL: lw $[[R0:[0-9]+]], %got(v4f32)( ; ALL: lw $[[R0:[0-9]+]], %got(v4f32)(
; ALL: ld.w $w12, 0($[[R0]]) ; ALL: ld.w $w12, 0($[[R0]])
; ALL: splati.w $w[[W0:[0-9]+]], $w13[1] ; ALL: splati.w $w[[W0:[0-9]+]], $w13[1]
; NOODDSPREG: st.w $w[[W0]], 0($sp) ; NOODDSPREG: st.w $w[[W0]], 0($sp)
; ODDSPREG-NOT: st.w ; ODDSPREG-NOT: st.w
; ODDSPREG-NOT: ld.w ; ODDSPREG-NOT: ld.w
; ALL: # Clobber ; ALL: teqi $zero, 1
; ODDSPREG-NOT: st.w ; ODDSPREG-NOT: st.w
; ODDSPREG-NOT: ld.w ; ODDSPREG-NOT: ld.w
; NOODDSPREG: ld.w $w0, 0($sp) ; NOODDSPREG: ld.w $w0, 0($sp)
; ODDSPREG: mov.s $f0, $f[[W0]] ; ODDSPREG: mov.s $f0, $f[[W0]]