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[X86] DAGCombine should not introduce FILD in soft-float mode
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Authored by mkuper on Nov 1 2015, 1:48 AM.

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Reviewers

nadav
mbodart
mkuper

Summary

The x86 "sitofp i64 to double" dag combine, in 32-bit mode, lowers the sitofp directly to X86ISD::FILD (or FILD_FLAG).
This should not be done in soft-float mode.

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Event Timeline

mkuper updated this revision to Diff 38840.Nov 1 2015, 1:48 AM

mkuper retitled this revision from to [X86] DAGCombine should not introduce FILD in soft-float mode.

mkuper updated this object.

mkuper added reviewers: nadav, mbodart.

mkuper added a subscriber: llvm-commits.

LGTM

LGTM.

mkuper accepted this revision.Nov 4 2015, 3:21 AM

mkuper added a reviewer: mkuper.

This revision is now accepted and ready to land.Nov 4 2015, 3:21 AM

Closed by r252042

Revision Contents

Path

Size

lib/

Target/

X86/

	X86ISelLowering.cpp
	X86ISelLowering.cpp (revision 251397)

4 lines

test/

CodeGen/

X86/

	soft-sitofp.ll
	soft-sitofp.ll (revision 0)

15 lines

Diff 38840

lib/Target/X86/X86ISelLowering.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

Show First 20 Lines • Show All 26,440 Lines • ▼ Show 20 Lines	if (InVT.isVector() && (InSVT == MVT::i8 \|\| InSVT == MVT::i16)) {
SDLoc dl(N);		SDLoc dl(N);
EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,		EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
InVT.getVectorNumElements());		InVT.getVectorNumElements());
SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);		SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);		return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
}		}

// Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have		// Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
// a 32-bit target where SSE doesn't support i64->FP operations.		// a 32-bit target where SSE doesn't support i64->FP operations.
if (Op0.getOpcode() == ISD::LOAD) {		if (!Subtarget->useSoftFloat() && Op0.getOpcode() == ISD::LOAD) {
LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());		LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
EVT LdVT = Ld->getValueType(0);		EVT LdVT = Ld->getValueType(0);

// This transformation is not supported if the result type is f16		// This transformation is not supported if the result type is f16
if (VT == MVT::f16)		if (VT == MVT::f16)
return SDValue();		return SDValue();

if (!Ld->isVolatile() && !VT.isVector() &&		if (!Ld->isVolatile() && !VT.isVector() &&
▲ Show 20 Lines • Show All 1,087 Lines • Show Last 20 Lines

test/CodeGen/X86/soft-sitofp.ll

				; RUN: llc < %s \| FileCheck %s

				target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
				target triple = "i386-pc-linux"

				; Function Attrs: nounwind
				; CHECK-LABEL: ll_to_d:
				; CHECK: calll __floatdidf
				define double @ll_to_d(i64 %n) #0 {
				entry:
				%conv = sitofp i64 %n to double
				ret double %conv
				}

				attributes #0 = { nounwind "use-soft-float"="true" }