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sgt on i1s also encodes implication
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Authored by reames on Oct 14 2015, 4:33 PM.

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Summary

Follow on to http://reviews.llvm.org/D13074, implementing something pointed out by Sanjoy. His truth table from his comment on that bug summarizes things well:
LHS | RHS | LHS >=s RHS | LHS implies RHS
0 | 0 | 1 (0 >= 0) | 1
0 | 1 | 1 (0 >= -1) | 1
1 | 0 | 0 (-1 >= 0) | 0
1 | 1 | 1 (-1 >= -1) | 1

The key point is that an "i1 1" is the value "-1", not "1".

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rL LLVM

Event Timeline

reames updated this revision to Diff 37423.Oct 14 2015, 4:33 PM
reames retitled this revision from to sgt on i1s also encodes implication.
reames updated this object.
reames added a reviewer: sanjoy.
reames added a subscriber: llvm-commits.
sanjoy accepted this revision.Oct 22 2015, 1:42 PM
sanjoy edited edge metadata.

The change itself is fine, but I think the comments on what inequalities are equivalent to implication should not be on implies itself; but on the code that simplifies inequalities as implication.

This revision is now accepted and ready to land.Oct 22 2015, 1:42 PM
This revision was automatically updated to reflect the committed changes.